Парвки кода.

CodeVerilog/readme.md

@@ -55,8 +55,8 @@ reg dataValid_d1;
 reg dataValid_d2;
 
 always @(posedge Clk_i) begin
-	dataValid_d1 <= dataValid;
-	dataValid_d2 <= dataValid_d1;
+    dataValid_d1 <= dataValid;
+    dataValid_d2 <= dataValid_d1;
 end
 
 reg [3:0] dataValidShReg;