Переработан EpSubsystem

CDC/Cdc.sv

@@ -20,24 +20,23 @@
 //////////////////////////////////////////////////////////////////////////////////
 module CDC #(
 	parameter WIDTH = 32,
-	parameter STAGES = 3,
-	parameter SPI_NUM = 7
+	parameter STAGES = 3
 )
 (
 	input ClkFast_i,
-	input [SPI_NUM-1:0] ClkSlow_i,
+	input ClkSlow_i,
 
 	/* Arrays of inputs */
-	input [WIDTH-1:0] SpiCtrlReg_i [SPI_NUM-1:0],
-	input [WIDTH-1:0] SpiCsCtrlReg_i [SPI_NUM-1:0],
-	input [WIDTH-1:0] SpiCsDelayReg_i [SPI_NUM-1:0],
-	input [WIDTH-1:0] SpiTxRxFifoCtrlReg_i [SPI_NUM-1:0],
+	input [WIDTH-1:0] SpiCtrlReg_i,
+	input [WIDTH-1:0] SpiCsCtrlReg_i,
+	input [WIDTH-1:0] SpiCsDelayReg_i,
+	input [WIDTH-1:0] SpiTxRxFifoCtrlReg_i,
 
 	/* Arrays of outputs */
-	output [WIDTH-1:0] SpiCtrlReg_o [SPI_NUM-1:0],
-	output [WIDTH-1:0] SpiCsCtrlReg_o [SPI_NUM-1:0],
-	output [WIDTH-1:0] SpiCsDelayReg_o [SPI_NUM-1:0],
-	output [WIDTH-1:0] SpiTxRxFifoCtrlReg_o [SPI_NUM-1:0]
+	output [WIDTH-1:0] SpiCtrlReg_o,
+	output [WIDTH-1:0] SpiCsCtrlReg_o,
+	output [WIDTH-1:0] SpiCsDelayReg_o,
+	output [WIDTH-1:0] SpiTxRxFifoCtrlReg_o
 	
 );
 
@@ -45,29 +44,25 @@ module CDC #(
 //  REG/WIRE
 //================================================================================
 /* Arrays of launch registers */
-reg [WIDTH-1:0] spiCtrlReg [SPI_NUM-1:0];
-reg [WIDTH-1:0] spiCsCtrlReg [SPI_NUM-1:0];
-reg [WIDTH-1:0] spiCsDelayReg [SPI_NUM-1:0];
-reg [WIDTH-1:0] spiTxRxFifoCtrlReg [SPI_NUM-1:0];
+reg [WIDTH-1:0] spiCtrlReg;
+reg [WIDTH-1:0] spiCsCtrlReg;
+reg [WIDTH-1:0] spiCsDelayReg;
+reg [WIDTH-1:0] spiTxRxFifoCtrlReg;
 
 /* Array of capture regs */
-(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spiCtrlReg_c [SPI_NUM-1:0];
-(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spiCsCtrlReg_c [SPI_NUM-1:0];
-(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spiCsDelayReg_c [SPI_NUM-1:0];
-(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spiTxRxFifoCtrlReg_c [SPI_NUM-1:0];
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spiCtrlReg_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spiCsCtrlReg_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spiCsDelayReg_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spiTxRxFifoCtrlReg_c;
 
 //================================================================================
 //	ASSIGNMENTS
 //================================================================================
-genvar i ;
-generate 
-	for (i = 0; i < SPI_NUM; i = i + 1) begin : CDC_ASSIGN_OUT
-		assign SpiCtrlReg_o[i] = spiCtrlReg_c[i][STAGES*WIDTH-1:(STAGES-1)*WIDTH];
-		assign SpiCsCtrlReg_o[i] = spiCsCtrlReg_c[i][STAGES*WIDTH-1:(STAGES-1)*WIDTH];
-		assign SpiCsDelayReg_o[i] = spiCsDelayReg_c[i][STAGES*WIDTH-1:(STAGES-1)*WIDTH];
-		assign SpiTxRxFifoCtrlReg_o[i] = spiTxRxFifoCtrlReg_c[i][STAGES*WIDTH-1:(STAGES-1)*WIDTH];
-	end
-endgenerate
+
+assign SpiCtrlReg_o = spiCtrlReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign SpiCsCtrlReg_o = spiCsCtrlReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign SpiCsDelayReg_o = spiCsDelayReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign SpiTxRxFifoCtrlReg_o = spiTxRxFifoCtrlReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 
 //================================================================================
 //	LOCALPARAMS
@@ -83,15 +78,12 @@ always_ff @(posedge ClkFast_i) begin
 	spiTxRxFifoCtrlReg <= SpiTxRxFifoCtrlReg_i;
 end
 
-generate 
-	for (i = 0; i < SPI_NUM; i = i + 1) begin : CDC_GEN
-		always_ff @(posedge ClkSlow_i[i]) begin : CDC_CAPTURE
-			spiCtrlReg_c[i] <= {spiCtrlReg_c[i][(STAGES-1)*WIDTH-1:0], spiCtrlReg[i]};
-			spiCsCtrlReg_c[i] <= {spiCsCtrlReg_c[i][(STAGES-1)*WIDTH-1:0], spiCsCtrlReg[i]};
-			spiCsDelayReg_c[i] <= {spiCsDelayReg_c[i][(STAGES-1)*WIDTH-1:0], spiCsDelayReg[i]};
-			spiTxRxFifoCtrlReg_c[i] <= {spiTxRxFifoCtrlReg_c[i][(STAGES-1)*WIDTH-1:0], spiTxRxFifoCtrlReg[i]};
-		end
-	end
-endgenerate
+
+always_ff @(posedge ClkSlow_i) begin : CDC_CAPTURE
+	spiCtrlReg_c <= {spiCtrlReg_c[(STAGES-1)*WIDTH-1:0], spiCtrlReg};
+	spiCsCtrlReg_c <= {spiCsCtrlReg_c[(STAGES-1)*WIDTH-1:0], spiCsCtrlReg};
+	spiCsDelayReg_c <= {spiCsDelayReg_c[(STAGES-1)*WIDTH-1:0], spiCsDelayReg};
+	spiTxRxFifoCtrlReg_c <= {spiTxRxFifoCtrlReg_c[(STAGES-1)*WIDTH-1:0], spiTxRxFifoCtrlReg};
+end
 
 endmodule

ClkManager/ClkManager.sv

@@ -22,16 +22,19 @@
 
 module ClkManager 
 #(
-	parameter	SPI_NUM	=	7,
-	parameter	STAGES	=	3
+	parameter SPI_NUM	=	7,
+	parameter STAGES	=	3,
+	parameter AXI_DATA_WIDTH = 64,
+	parameter [AXI_DATA_WIDTH-1:0] SPI_BASE_ADDR = 64'h0000_0000_0000_1000 
 )
 (
 	input Clk_i,
-	input Rst_i,
-	input Rst80_i,
-	input [7:0] BaudRate_i [SPI_NUM-1:0],
+	input RstN_i,
+
+	input [AXI_DATA_WIDTH-1:0] WrData_i,
+    input [AXI_DATA_WIDTH-1:0] WrAddr_i,
+    input Val_i,
 
-	output	Clk80_o,
 	output	[SPI_NUM-1:0]	SpiClk_o,
 	output	SubSystSyncRst_o
 );
@@ -59,16 +62,19 @@ module ClkManager
 	wire [SPI_NUM-1:0] clkCh; 
 	wire [SPI_NUM-1:0] spiClk;
 
+	reg [AXI_DATA_WIDTH-1:0] spiClkReg [SPI_NUM-1:0];
+	reg [7:0] baudRate [SPI_NUM-1:0];
 //================================================================================
 //	ASSIGNMENTS
 //===============================================================================
+
 	genvar k;
 
 	generate 
 		for (k = 0; k < SPI_NUM; k = k + 1) begin : ClkGenAssignments
-			assign clkNum[k] = BaudRate_i[k][7:5];
-			assign clkDiv[k] = BaudRate_i[k][3:0];
-			assign clkCh[k] = BaudRate_i[k][4];
+			assign clkNum[k] = baudRate[k][7:5];
+			assign clkDiv[k] = baudRate[k][3:0];
+			assign clkCh[k] = baudRate[k][4];
 		end
 	endgenerate
 
@@ -84,6 +90,37 @@ module ClkManager
 //================================================================================
 //	CODING
 //================================================================================   
+
+always_ff @(posedge Clk_i) begin
+    if (!RstN_i) begin
+        for (int i = 0; i < SPI_NUM; i++) begin
+            spiClkReg[i] <= {AXI_DATA_WIDTH{1'b0}};
+        end
+    end
+    else begin
+        if (Val_i) begin
+            for (int i = 0; i < SPI_NUM; i++) begin
+                if (WrAddr_i == SPI_BASE_ADDR*i + 64'h1008) begin
+                    spiClkReg[i] <= WrData_i;
+                end
+            end
+        end
+    end
+end
+
+always @(*) begin
+    if (!RstN_i) begin
+        for (int i = 0; i < SPI_NUM; i++) begin
+            baudRate[i] = 0;
+        end
+    end
+    else begin
+        for (int i = 0; i < SPI_NUM; i++) begin
+            baudRate[i] = spiClkReg[i][7:0];
+        end
+    end
+end
+
 	genvar i;
 
 	generate

DataFifo/DataFifoWrapper.v

@@ -20,35 +20,37 @@
 //////////////////////////////////////////////////////////////////////////////////
 module DataFifoWrapper 
 #(
+	parameter	AXI_DATA_WIDTH	=	64,
 	parameter	CMD_REG_WIDTH	=	32,
 	parameter	ADDR_REG_WIDTH	=	12,
 	parameter	STAGES			=	3,
-	parameter	FIFO_NUM		=	7
+	parameter	FIFO_NUM		=	1,
+	parameter	[AXI_DATA_WIDTH-1:0] TX_FIFO_ADDR	=	64'h28,
+	parameter	[AXI_DATA_WIDTH-1:0] RX_FIFO_ADDR	=	64'h30
 )
 (
 	input	WrClk_i,
 	input	RdClk_i,
+
 	input	FifoRxRst_i,
 	input	FifoTxRst_i,
 	input	FifoTxRstWrPtr_i,
 	input	FifoRxRstRdPtr_i,
-	input	SmcAre_i,
-	input	SmcAwe_i,
-	input	[ADDR_REG_WIDTH-1:0]	Addr_i,
 
-	input	ToFifoVal_i,
-	input	[CMD_REG_WIDTH-1:0]	ToFifoData_i,
+	input [AXI_DATA_WIDTH-1:0] WrData_i,
+	input [AXI_DATA_WIDTH-1:0] WrAddr_i,
+	input [AXI_DATA_WIDTH-1:0] RdAddr_i,
+	input Val_i,
+
 	input	[CMD_REG_WIDTH-1:0]	ToFifoRxData_i,
 	input	ToFifoRxWriteVal_i,
-	
 	input	ToFifoTxReadVal_i,
 
-	output	ToSpiVal_o,
-	output	EmptyFlagTx_o,
 	output	[CMD_REG_WIDTH-1:0]	TxFifoCtrlReg_o,
 	output	[CMD_REG_WIDTH-1:0]	RxFifoCtrlReg_o,
-	output	[CMD_REG_WIDTH-1:0]	ToSpiData_o,
-	output	[CMD_REG_WIDTH-1:0]	DataFromRxFifo_o
+	output	EmptyFlagTx_o,
+	output	[CMD_REG_WIDTH-1:0]	DataFromRxFifo_o,
+	output	[CMD_REG_WIDTH-1:0]	ToSpiData_o
 );
 //================================================================================
 //	REG/WIRE
@@ -69,10 +71,10 @@ module DataFifoWrapper
 
 	wire emptyFlagTxForDsp;
 	
+	wire valR = (Val_i&(WrAddr_i==TX_FIFO_ADDR));
 //================================================================================
 //	ASSIGNMENTS
 //================================================================================
-	assign ToSpiVal_o = 1'b1;
 	assign DataFromRxFifo_o = dataFromRxFifo;
 	assign EmptyFlagTx_o = emptyFlagTx;
 
@@ -86,12 +88,12 @@ module DataFifoWrapper
 //================================================================================
 //	CODING
 //================================================================================
-	FifoCtrl FifoCtrl_inst 
+	FifoCtrl FifoCtrl
 	(
-		.ToFifoTxWriteVal_i		(ToFifoVal_i),
+		.ToFifoTxWriteVal_i		(valR),
 		.ToFifoTxReadVal_i		(ToFifoTxReadVal_i),
 		.ToFifoRxWriteVal_i		(ToFifoRxWriteVal_i),
-		.ToFifoRxReadVal_i		(SmcAre_i),
+		.ToFifoRxReadVal_i		(),
 		.FifoTxFull_i			(fullFlagTx),
 		.FifoTxRst_i			(FifoTxRst_i),
 		.FifoRxRst_i			(FifoRxRst_i),
@@ -105,7 +107,6 @@ module DataFifoWrapper
 		.FifoTxRdClock_i		(RdClk_i),
 		.FifoRxWrClock_i		(RdClk_i),
 		.FifoRxRdClock_i		(WrClk_i),
-		.Addr_i					(Addr_i),
 		.RxFifoUpDnCnt_o		(rxFifoUpDnCnt),
 		.TxFifoUpDnCnt_o		(txFifoUpDnCnt),
 		.FifoTxWriteEn_o		(txFifoWrEn),
@@ -119,7 +120,7 @@ module DataFifoWrapper
 		.wr_clk		(WrClk_i), 
 		.rd_clk		(RdClk_i), 
 		.rst		(FifoTxRst_i),
-		.din		(ToFifoData_i), 
+		.din		(WrData_i), 
 		.wr_en		(txFifoWrEn), 
 		.rd_en		(txFifoRdEn), 
 		.dout		(ToSpiData_o),

DataFifo/FifoCtrl.v

@@ -45,8 +45,6 @@ module FifoCtrl #(
 	input FifoRxWrClock_i,
 	input FifoRxRdClock_i,
 
-	input [63:0] Addr_i,
-
 	input FifoTxRst_i,
 	input FifoRxRst_i,
 
@@ -89,16 +87,6 @@ module FifoCtrl #(
 
 	wire rxFifoRstSync;
 
-	wire requestToFifo0	= (Addr_i == FIFO_1_READ_ADDR) ? 1'b1 : 1'b0;
-	wire requestToFifo1	= (Addr_i == FIFO_2_READ_ADDR) ? 1'b1 : 1'b0;
-	wire requestToFifo2	= (Addr_i == FIFO_3_READ_ADDR) ? 1'b1 : 1'b0;
-	wire requestToFifo3	= (Addr_i == FIFO_4_READ_ADDR) ? 1'b1 : 1'b0;
-	wire requestToFifo4	= (Addr_i == FIFO_5_READ_ADDR) ? 1'b1 : 1'b0;
-	wire requestToFifo5	= (Addr_i == FIFO_6_READ_ADDR) ? 1'b1 : 1'b0;
-	wire requestToFifo6	= (Addr_i == FIFO_7_READ_ADDR) ? 1'b1 : 1'b0;
-	
-	wire requestToFifo	= (requestToFifo0|requestToFifo1|requestToFifo2|requestToFifo3|requestToFifo4|requestToFifo5|requestToFifo6) ? 1'b1 : 1'b0;
-
 //================================================================================
 //	ASSIGNMENTS
 //================================================================================	

InputMux/InputMuxOld.sv

@@ -0,0 +1,74 @@
+module InputMux #(
+    parameter AXI_DATA_WIDTH = 64,
+    parameter SPI_NUM = 7,
+    parameter FIFO_TX1_ADDR = 64'h0000000000001028,
+    parameter FIFO_TX2_ADDR = 64'h0000000000002028,
+    parameter FIFO_TX3_ADDR = 64'h0000000000003028,
+    parameter FIFO_TX4_ADDR = 64'h0000000000004028,
+    parameter FIFO_TX5_ADDR = 64'h0000000000005028,
+    parameter FIFO_TX6_ADDR = 64'h0000000000006028,
+    parameter FIFO_TX7_ADDR = 64'h0000000000007028
+)(
+    input Clk_i,
+    input RstN_i,
+
+    input Val_i,
+    input [AXI_DATA_WIDTH-1:0] Data_i,
+    input [AXI_DATA_WIDTH-1:0] Addr_i,
+
+    output reg ToRegMapVal_o,
+    output reg [AXI_DATA_WIDTH-1:0] ToRegMapData_o,
+    output reg [AXI_DATA_WIDTH-1:0] ToRegMapAddr_o,
+
+    output reg  [SPI_NUM-1:0] ToFifoVal_o,
+    output reg [AXI_DATA_WIDTH-1:0] ToFifoData_o
+);
+//================================================================================
+//	                            LOCALPARAMS
+//================================================================================
+//================================================================================
+//	                             REG/WIRE
+//================================================================================
+reg [AXI_DATA_WIDTH-1 : 0] toFifoDataReg;
+//================================================================================
+//	                            CODING
+//================================================================================
+always @(posedge Clk_i) begin 
+    if (!RstN_i) begin 
+        ToRegMapVal_o <= 1'b0;
+        ToRegMapData_o <= {AXI_DATA_WIDTH{1'b0}};
+        ToRegMapAddr_o <= {AXI_DATA_WIDTH{1'b0}};
+
+        ToFifoVal_o <= {SPI_NUM{1'b0}};
+        toFifoDataReg <= {AXI_DATA_WIDTH{1'b0}};
+    end
+    else begin 
+        if (Val_i) begin
+            ToRegMapVal_o <= 1'b1;
+            ToRegMapData_o <= Data_i;
+            ToRegMapAddr_o <= Addr_i;
+            ToFifoVal_o <= {SPI_NUM{1'b0}};
+            toFifoDataReg <= {AXI_DATA_WIDTH{1'b0}};
+            for (int i = 0; i < SPI_NUM; i = i + 1) begin
+                if (Addr_i == FIFO_TX1_ADDR + i*1000) begin
+                    ToFifoVal_o[i] <= 1'b1;
+                    toFifoDataReg <= Data_i;
+                end
+            end
+        end
+        else begin
+            ToRegMapVal_o <= 1'b0;
+            ToRegMapData_o <= {AXI_DATA_WIDTH{1'b0}};
+            ToRegMapAddr_o <= {AXI_DATA_WIDTH{1'b0}};
+
+            ToFifoVal_o <= {SPI_NUM{1'b0}};
+            toFifoDataReg <= {AXI_DATA_WIDTH{1'b0}};
+        end
+    end
+end
+
+always @(posedge Clk_i) begin 
+    ToFifoData_o <= toFifoDataReg;
+end
+
+endmodule

PowRstMem/PowRstMemWrapper.sv

@@ -1,12 +1,17 @@
-module PowRstMemWrapper (
+module PowRstMemWrapper #(
+    parameter AXI_DATA_WIDTH = 64,
+    parameter RST_MEM_BASE_ADDR = 64'h1000
+)
+(
     input Clk_i,
     input Rst_i,
 
-    input WrReq_i,
-    input  [63:0] Data_i,
+    input [AXI_DATA_WIDTH-1:0] WrData_i,
+    input [AXI_DATA_WIDTH-1:0] WrAddr_i,
+    input Val_i,
 
     input RdReq_i,
-    output [63:0] Data_o,
+    output [AXI_DATA_WIDTH-1:0] Data_o,
     output reg DataVal_o
 );
 
@@ -16,12 +21,13 @@ wire [5:0] addrB;
 wire weA;
 wire reB;
 
+wire wrReq = (Val_i&(WrAddr_i==RST_MEM_BASE_ADDR));
 
 MemCtrl MemCtrl
 (
     .Clk_i(Clk_i),
     .Rst_i(Rst_i),
-    .WrReq_i(WrReq_i),
+    .WrReq_i(wrReq),
     .RdReq_i(RdReq_i),
 
     .AddrA_o(addrA),
@@ -31,14 +37,13 @@ MemCtrl MemCtrl
     .ReB_o(reB)
 );
 
-
 PowRstCmdMem PowRstMem 
 (
     .clka(Clk_i),    // input wire clka
     .ena(1'b1),      // input wire ena
     .wea(weA),      // input wire [0 : 0] wea
     .addra(addrA),  // input wire [5 : 0] addra
-    .dina(Data_i),    // input wire [31 : 0] dina
+    .dina(WrData_i),    // input wire [31 : 0] dina
     .clkb(Clk_i),    // input wire clkb
     .enb(reB),      // input wire enb
     .addrb(addrB),  // input wire [5 : 0] addrb
@@ -47,6 +52,8 @@ PowRstCmdMem PowRstMem
 
 always @(posedge Clk_i) begin
     if (Rst_i) begin
+        DataVal_o <= 0;
+    end else begin
         DataVal_o <= reB;
     end
 end

RegMap/RegMap.sv

@@ -1,6 +1,7 @@
 module RegMap #(
     parameter AXI_DATA_WIDTH = 64,
-    parameter SPI_NUM = 7
+    parameter [AXI_DATA_WIDTH-1:0] SPI_BASE_ADDR = 64'h1000,
+    parameter [AXI_DATA_WIDTH-1:0] SPI6_BASE_ADDR = 64'h6000
 )(
     input Clk_i,
     input RstN_i,
@@ -10,330 +11,78 @@ module RegMap #(
     input [AXI_DATA_WIDTH-1:0] RdAddr_i,
     input Val_i,
 
-    output reg [AXI_DATA_WIDTH-1:0] Spi0CtrlReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] Spi0ClkReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] Spi0CsDelayReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] Spi0CsCtrlReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] Spi0TxRxFifoCtrlReg_o,
-
-    output reg [AXI_DATA_WIDTH - 1 : 0] SpiCtrlReg_o [SPI_NUM-1 : 0], 
-    output reg [AXI_DATA_WIDTH - 1 : 0] SpiClkReg_o [SPI_NUM-1 : 0],
-    output reg [AXI_DATA_WIDTH - 1 : 0] SpiCsDelayReg_o [SPI_NUM-1 : 0],
-    output reg [AXI_DATA_WIDTH - 1 : 0] SpiCsCtrlReg_o [SPI_NUM-1 : 0],
-    output reg [AXI_DATA_WIDTH - 1 : 0] SpiTxRxFifoCtrlReg_o [SPI_NUM-1 : 0],
-
-    output reg [AXI_DATA_WIDTH-1:0] Spi1CtrlReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] Spi1ClkReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] Spi1CsDelayReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] Spi1CsCtrlReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] Spi1TxRxFifoCtrlReg_o,
-
-    output reg [AXI_DATA_WIDTH-1:0] Spi2CtrlReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] Spi2ClkReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] Spi2CsDelayReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] Spi2CsCtrlReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] Spi2TxRxFifoCtrlReg_o,
-
-    output reg [AXI_DATA_WIDTH-1:0] Spi3CtrlReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] Spi3ClkReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] Spi3CsDelayReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] Spi3CsCtrlReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] Spi3TxRxFifoCtrlReg_o,
-
-    output reg [AXI_DATA_WIDTH-1:0] Spi4CtrlReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] Spi4ClkReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] Spi4CsDelayReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] Spi4CsCtrlReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] Spi4TxRxFifoCtrlReg_o,
-
-    output reg [AXI_DATA_WIDTH-1:0] Spi5CtrlReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] Spi5ClkReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] Spi5CsDelayReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] Spi5CsCtrlReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] Spi5TxRxFifoCtrlReg_o,
-
-    output reg [AXI_DATA_WIDTH-1:0] Spi6CtrlReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] Spi6ClkReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] Spi6CsDelayReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] Spi6CsCtrlReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] Spi6TxRxFifoCtrlReg_o,
-
-    output reg [AXI_DATA_WIDTH-1:0] SpiTxRxEnReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] SpiTxRxSetReg_o,
-    output reg [AXI_DATA_WIDTH-1:0] SpiTxRxClearReg_o,
+    output reg [AXI_DATA_WIDTH - 1 : 0] SpiCtrlReg_o, 
+    output reg [AXI_DATA_WIDTH - 1 : 0] SpiClkReg_o,
+    output reg [AXI_DATA_WIDTH - 1 : 0] SpiCsDelayReg_o,
+    output reg [AXI_DATA_WIDTH - 1 : 0] SpiCsCtrlReg_o,
+    output reg [AXI_DATA_WIDTH - 1 : 0] SpiTxRxFifoCtrlReg_o,
 
     output reg [AXI_DATA_WIDTH - 1 : 0 ] AnsDataReg_o
 
 );
 
 //================================================================================
-//	LOCALPARAMS
+//  LOCALPARAMS
 //================================================================================
 /* Spi 0 */
-localparam  [AXI_DATA_WIDTH-1:0]  SPI0_BASE_ADDR = 64'h0000000000001000;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI0_CTRL_ADDR = SPI0_BASE_ADDR + 64'h0000;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI0_CLK_ADDR = SPI0_BASE_ADDR + 64'h0008;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI0_CS_DELAY_ADDR = SPI0_BASE_ADDR + 64'h0010;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI0_CS_CTRL_ADDR = SPI0_BASE_ADDR + 64'h0018;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI0_TX_RX_FIFO_CTRL_ADDR = SPI0_BASE_ADDR + 64'h0020;
-/* Spi 1 */
-localparam  [AXI_DATA_WIDTH-1:0]  SPI1_BASE_ADDR = 64'h0000000000002000;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI1_CTRL_ADDR = SPI1_BASE_ADDR + 64'h0000;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI1_CLK_ADDR = SPI1_BASE_ADDR + 64'h0008;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI1_CS_DELAY_ADDR = SPI1_BASE_ADDR + 64'h0010;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI1_CS_CTRL_ADDR = SPI1_BASE_ADDR + 64'h0018;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI1_TX_RX_FIFO_CTRL_ADDR = SPI1_BASE_ADDR + 64'h0020;
-/* Spi 2 */
-localparam  [AXI_DATA_WIDTH-1:0]  SPI2_BASE_ADDR = 64'h0000000000003000;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI2_CTRL_ADDR = SPI2_BASE_ADDR + 64'h0000;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI2_CLK_ADDR = SPI2_BASE_ADDR + 64'h0008;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI2_CS_DELAY_ADDR = SPI2_BASE_ADDR + 64'h0010;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI2_CS_CTRL_ADDR = SPI2_BASE_ADDR + 64'h0018;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI2_TX_RX_FIFO_CTRL_ADDR = SPI2_BASE_ADDR + 64'h0020;
-/* Spi 3 */
-localparam  [AXI_DATA_WIDTH-1:0]  SPI3_BASE_ADDR = 64'h0000000000004000;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI3_CTRL_ADDR = SPI3_BASE_ADDR + 64'h0000;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI3_CLK_ADDR = SPI3_BASE_ADDR + 64'h0008;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI3_CS_DELAY_ADDR = SPI3_BASE_ADDR + 64'h0010;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI3_CS_CTRL_ADDR = SPI3_BASE_ADDR + 64'h0018;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI3_TX_RX_FIFO_CTRL_ADDR = SPI3_BASE_ADDR + 64'h0020;
-/* Spi 4 */
-localparam  [AXI_DATA_WIDTH-1:0]  SPI4_BASE_ADDR = 64'h0000000000005000;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI4_CTRL_ADDR = SPI4_BASE_ADDR + 64'h0000;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI4_CLK_ADDR = SPI4_BASE_ADDR + 64'h0008;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI4_CS_DELAY_ADDR = SPI4_BASE_ADDR + 64'h0010;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI4_CS_CTRL_ADDR = SPI4_BASE_ADDR + 64'h0018;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI4_TX_RX_FIFO_CTRL_ADDR = SPI4_BASE_ADDR + 64'h0020;
-/* Spi 5 */
-localparam  [AXI_DATA_WIDTH-1:0]  SPI5_BASE_ADDR = 64'h0000000000006000;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI5_CTRL_ADDR = SPI5_BASE_ADDR + 64'h0000;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI5_CLK_ADDR = SPI5_BASE_ADDR + 64'h0008;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI5_CS_DELAY_ADDR = SPI5_BASE_ADDR + 64'h0010;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI5_CS_CTRL_ADDR = SPI5_BASE_ADDR + 64'h0018;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI5_TX_RX_FIFO_CTRL_ADDR = SPI5_BASE_ADDR + 64'h0020;
-/* Spi 6 */
-localparam  [AXI_DATA_WIDTH-1:0]  SPI6_BASE_ADDR = 64'h0000000000007000;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI6_CTRL_ADDR = SPI6_BASE_ADDR + 64'h0000;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI6_CLK_ADDR = SPI6_BASE_ADDR + 64'h0008;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI6_CS_DELAY_ADDR = SPI6_BASE_ADDR + 64'h0010;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI6_CS_CTRL_ADDR = SPI6_BASE_ADDR + 64'h0018;
-localparam  [AXI_DATA_WIDTH-1:0]  SPI6_TX_RX_FIFO_CTRL_ADDR = SPI6_BASE_ADDR + 64'h0020;
 
-/* Common */
-localparam [AXI_DATA_WIDTH-1:0] SPI_TX_RX_EN_ADDR = SPI6_BASE_ADDR + 64'h0100;
-localparam [AXI_DATA_WIDTH-1:0] SPI_TX_RX_SET_REG_ADDR = SPI6_BASE_ADDR + 64'h0108;
-localparam [AXI_DATA_WIDTH-1:0] SPI_TX_RX_CLEAR_REG_ADDR = SPI6_BASE_ADDR + 64'h0110;
-localparam [AXI_DATA_WIDTH-1:0] SPI_TX_RX_FLAGS_REG_ADDR = SPI6_BASE_ADDR + 64'h0118;
-localparam [AXI_DATA_WIDTH-1:0] GPIO_CTRL_ADDR = SPI6_BASE_ADDR + 64'h0120;
+localparam  [AXI_DATA_WIDTH-1:0]  SPI_CTRL_ADDR = SPI_BASE_ADDR + 64'h0000;
+localparam  [AXI_DATA_WIDTH-1:0]  SPI_CLK_ADDR = SPI_BASE_ADDR + 64'h0008;
+localparam  [AXI_DATA_WIDTH-1:0]  SPI_CS_DELAY_ADDR = SPI_BASE_ADDR + 64'h0010;
+localparam  [AXI_DATA_WIDTH-1:0]  SPI_CS_CTRL_ADDR = SPI_BASE_ADDR + 64'h0018;
+localparam  [AXI_DATA_WIDTH-1:0]  SPI_TX_RX_FIFO_CTRL_ADDR = SPI_BASE_ADDR + 64'h0020;
 
 //================================================================================
 //                                  CODING
 //================================================================================
 always_ff @(posedge Clk_i) begin
     if (!RstN_i) begin
-        for (int i = 0; i < SPI_NUM; i++) begin
-            SpiCtrlReg_o[i] <= {AXI_DATA_WIDTH{1'b0}};
-            SpiClkReg_o[i] <= {AXI_DATA_WIDTH{1'b0}};
-            SpiCsDelayReg_o[i] <= {AXI_DATA_WIDTH{1'b0}};
-            SpiCsCtrlReg_o[i] <= {AXI_DATA_WIDTH{1'b0}};
-            SpiTxRxFifoCtrlReg_o[i] <= {AXI_DATA_WIDTH{1'b0}};
-        end
-        SpiTxRxEnReg_o <= {AXI_DATA_WIDTH{1'b0}};
-        SpiTxRxSetReg_o <= {AXI_DATA_WIDTH{1'b0}};
-        SpiTxRxClearReg_o <= {AXI_DATA_WIDTH{1'b0}};
+        SpiCtrlReg_o <= {AXI_DATA_WIDTH{1'b0}};
+        SpiClkReg_o <= {AXI_DATA_WIDTH{1'b0}};
+        SpiCsDelayReg_o <= {AXI_DATA_WIDTH{1'b0}};
+        SpiCsCtrlReg_o <= {AXI_DATA_WIDTH{1'b0}};
+        SpiTxRxFifoCtrlReg_o <= {AXI_DATA_WIDTH{1'b0}};
     end
     else begin
         if (Val_i) begin
-            for (int i = 0; i < SPI_NUM; i++) begin
-                if (WrAddr_i == (SPI0_CTRL_ADDR + i*64'h1000)) begin
-                    SpiCtrlReg_o[i] <= WrData_i;
-                end
-                else if (WrAddr_i == (SPI0_CLK_ADDR + i*64'h1000)) begin
-                    SpiClkReg_o[i] <= WrData_i;
-                end
-                else if (WrAddr_i == (SPI0_CS_DELAY_ADDR + i*64'h1000)) begin
-                    SpiCsDelayReg_o[i] <= WrData_i;
-                end
-                else if (WrAddr_i == (SPI0_CS_CTRL_ADDR + i*64'h1000)) begin
-                    SpiCsCtrlReg_o[i] <= WrData_i;
-                end
-                else if (WrAddr_i == (SPI0_TX_RX_FIFO_CTRL_ADDR + i*64'h1000)) begin
-                    SpiTxRxFifoCtrlReg_o[i] <= WrData_i;
-                end
+            if (WrAddr_i == (SPI_CTRL_ADDR)) begin
+                SpiCtrlReg_o <= WrData_i;
             end
-            /* Other Registers */
-            if (WrAddr_i == SPI_TX_RX_EN_ADDR) begin
-                SpiTxRxEnReg_o <= WrData_i;
+            else if (WrAddr_i == (SPI_CLK_ADDR)) begin
+                SpiClkReg_o <= WrData_i;
             end
-            else if (WrAddr_i == SPI_TX_RX_SET_REG_ADDR) begin
-                SpiTxRxSetReg_o <= WrData_i;
+            else if (WrAddr_i == (SPI_CS_DELAY_ADDR)) begin
+                SpiCsDelayReg_o <= WrData_i;
             end
-            else if (WrAddr_i == SPI_TX_RX_CLEAR_REG_ADDR) begin
-                SpiTxRxClearReg_o <= WrData_i;
+            else if (WrAddr_i == (SPI_CS_CTRL_ADDR)) begin
+                SpiCsCtrlReg_o <= WrData_i;
+            end
+            else if (WrAddr_i == (SPI_TX_RX_FIFO_CTRL_ADDR)) begin
+                SpiTxRxFifoCtrlReg_o <= WrData_i;
             end
         end
     end
 end
 
-/* Read Registers */
-// always @(*) begin 
-//     if (!RstN_i) begin 
-//         AnsDataReg_o = {AXI_DATA_WIDTH{1'b0}};
-//     end
-//     else begin 
-//         case (RdAddr_i)  
-//             SPI0_CTRL_ADDR: begin
-//                 AnsDataReg_o = Spi0CtrlReg_o;
-//             end
-//             SPI0_CLK_ADDR: begin
-//                 AnsDataReg_o = Spi0ClkReg_o;
-//             end
-//             SPI0_CS_DELAY_ADDR: begin
-//                 AnsDataReg_o = Spi0CsDelayReg_o;
-//             end
-//             SPI0_CS_CTRL_ADDR: begin
-//                 AnsDataReg_o = Spi0CsCtrlReg_o;
-//             end
-//             SPI0_TX_RX_FIFO_CTRL_ADDR: begin
-//                 AnsDataReg_o = Spi0TxRxFifoCtrlReg_o;
-//             end
-//             SPI1_CTRL_ADDR: begin
-//                 AnsDataReg_o = Spi1CtrlReg_o;
-//             end
-//             SPI1_CLK_ADDR: begin
-//                 AnsDataReg_o = Spi1ClkReg_o;
-//             end
-//             SPI1_CS_DELAY_ADDR: begin
-//                 AnsDataReg_o = Spi1CsDelayReg_o;
-//             end
-//             SPI1_CS_CTRL_ADDR: begin
-//                 AnsDataReg_o = Spi1CsCtrlReg_o;
-//             end
-//             SPI1_TX_RX_FIFO_CTRL_ADDR: begin
-//                 AnsDataReg_o = Spi1TxRxFifoCtrlReg_o;
-//             end
-//             SPI2_CTRL_ADDR: begin
-//                 AnsDataReg_o = Spi2CtrlReg_o;
-//             end
-//             SPI2_CLK_ADDR: begin
-//                 AnsDataReg_o = Spi2ClkReg_o;
-//             end
-//             SPI2_CS_DELAY_ADDR: begin
-//                 AnsDataReg_o = Spi2CsDelayReg_o;
-//             end
-//             SPI2_CS_CTRL_ADDR: begin
-//                 AnsDataReg_o = Spi2CsCtrlReg_o;
-//             end
-//             SPI2_TX_RX_FIFO_CTRL_ADDR: begin
-//                 AnsDataReg_o = Spi2TxRxFifoCtrlReg_o;
-//             end
-//             SPI3_CTRL_ADDR: begin
-//                 AnsDataReg_o = Spi3CtrlReg_o;
-//             end
-//             SPI3_CLK_ADDR: begin
-//                 AnsDataReg_o = Spi3ClkReg_o;
-//             end
-//             SPI3_CS_DELAY_ADDR: begin
-//                 AnsDataReg_o = Spi3CsDelayReg_o;
-//             end
-//             SPI3_CS_CTRL_ADDR: begin
-//                 AnsDataReg_o = Spi3CsCtrlReg_o;
-//             end
-//             SPI3_TX_RX_FIFO_CTRL_ADDR: begin
-//                 AnsDataReg_o = Spi3TxRxFifoCtrlReg_o;
-//             end
-//             SPI4_CTRL_ADDR: begin
-//                 AnsDataReg_o = Spi4CtrlReg_o;
-//             end
-//             SPI4_CLK_ADDR: begin
-//                 AnsDataReg_o = Spi4ClkReg_o;
-//             end
-//             SPI4_CS_DELAY_ADDR: begin
-//                 AnsDataReg_o = Spi4CsDelayReg_o;
-//             end
-//             SPI4_CS_CTRL_ADDR: begin
-//                 AnsDataReg_o = Spi4CsCtrlReg_o;
-//             end
-//             SPI4_TX_RX_FIFO_CTRL_ADDR: begin
-//                 AnsDataReg_o = Spi4TxRxFifoCtrlReg_o;
-//             end
-//             SPI5_CTRL_ADDR: begin
-//                 AnsDataReg_o = Spi5CtrlReg_o;
-//             end
-//             SPI5_CLK_ADDR: begin
-//                 AnsDataReg_o = Spi5ClkReg_o;
-//             end
-//             SPI5_CS_DELAY_ADDR: begin
-//                 AnsDataReg_o = Spi5CsDelayReg_o;
-//             end
-//             SPI5_CS_CTRL_ADDR: begin
-//                 AnsDataReg_o = Spi5CsCtrlReg_o;
-//             end
-//             SPI5_TX_RX_FIFO_CTRL_ADDR: begin
-//                 AnsDataReg_o = Spi5TxRxFifoCtrlReg_o;
-//             end
-//             SPI6_CTRL_ADDR: begin
-//                 AnsDataReg_o = Spi6CtrlReg_o;
-//             end
-//             SPI6_CLK_ADDR: begin
-//                 AnsDataReg_o = Spi6ClkReg_o;
-//             end
-//             SPI6_CS_DELAY_ADDR: begin
-//                 AnsDataReg_o = Spi6CsDelayReg_o;
-//             end
-//             SPI6_CS_CTRL_ADDR: begin
-//                 AnsDataReg_o = Spi6CsCtrlReg_o;
-//             end
-//             SPI6_TX_RX_FIFO_CTRL_ADDR: begin
-//                 AnsDataReg_o = Spi6TxRxFifoCtrlReg_o;
-//             end
-//             SPI_TX_RX_EN_ADDR: begin
-//                 AnsDataReg_o = SpiTxRxEnReg_o;
-//             end
-//             SPI_TX_RX_SET_REG_ADDR: begin
-//                 AnsDataReg_o = SpiTxRxSetReg_o;
-//             end
-//             SPI_TX_RX_CLEAR_REG_ADDR: begin
-//                 AnsDataReg_o = SpiTxRxClearReg_o;
-//             end
-//             default: begin
-//                 AnsDataReg_o = {AXI_DATA_WIDTH{1'b0}};
-//             end
-//         endcase
-//     end
-// end
-
 always_comb begin 
     if (!RstN_i) begin 
         AnsDataReg_o = {AXI_DATA_WIDTH{1'b0}};
     end
     else begin 
-        for (int i = 0; i < SPI_NUM; i++) begin
-            if (RdAddr_i == (SPI0_CTRL_ADDR + i*64'h1000)) begin
-                AnsDataReg_o = SpiCtrlReg_o[i];
-            end
-            else if (RdAddr_i == (SPI0_CLK_ADDR + i*64'h1000)) begin
-                AnsDataReg_o = SpiClkReg_o[i];
-            end
-            else if (RdAddr_i == (SPI0_CS_DELAY_ADDR + i*64'h1000)) begin
-                AnsDataReg_o = SpiCsDelayReg_o[i];
-            end
-            else if (RdAddr_i == (SPI0_CS_CTRL_ADDR + i*64'h1000)) begin
-                AnsDataReg_o = SpiCsCtrlReg_o[i];
-            end
-            else if (RdAddr_i == (SPI0_TX_RX_FIFO_CTRL_ADDR + i*64'h1000)) begin
-                AnsDataReg_o = SpiTxRxFifoCtrlReg_o[i];
-            end
+        if (RdAddr_i == (SPI_CTRL_ADDR)) begin
+            AnsDataReg_o = SpiCtrlReg_o;
+        end
+        else if (RdAddr_i == (SPI_CLK_ADDR)) begin
+            AnsDataReg_o = SpiClkReg_o;
         end
-        /* Other Registers */
-        if (RdAddr_i == SPI_TX_RX_EN_ADDR) begin
-            AnsDataReg_o = SpiTxRxEnReg_o;
+        else if (RdAddr_i == (SPI_CS_DELAY_ADDR)) begin
+            AnsDataReg_o = SpiCsDelayReg_o;
         end
-        else if (RdAddr_i == SPI_TX_RX_SET_REG_ADDR) begin
-            AnsDataReg_o = SpiTxRxSetReg_o;
+        else if (RdAddr_i == (SPI_CS_CTRL_ADDR)) begin
+            AnsDataReg_o = SpiCsCtrlReg_o;
         end
-        else if (RdAddr_i == SPI_TX_RX_CLEAR_REG_ADDR) begin
-            AnsDataReg_o = SpiTxRxClearReg_o;
+        else if (RdAddr_i == (SPI_TX_RX_FIFO_CTRL_ADDR)) begin
+            AnsDataReg_o = SpiTxRxFifoCtrlReg_o;
         end
         else begin 
             AnsDataReg_o = {AXI_DATA_WIDTH{1'b0}};

SpiSettings/SpiSettings.sv

@@ -1,75 +1,70 @@
 module SpiSettings
 #(
     parameter AXI_DATA_WIDTH = 64,
-    parameter SPI_NUM = 7
+    parameter SPI_NUM = 1
 )(
 
-    input [AXI_DATA_WIDTH - 1 : 0 ]  SpiCtrlReg_i [SPI_NUM - 1 : 0] ,
-    input [AXI_DATA_WIDTH - 1 : 0 ] SpiCsDelayReg_i [SPI_NUM - 1 : 0] ,
-    input [AXI_DATA_WIDTH - 1 : 0 ] SpiClkReg_i [SPI_NUM - 1 : 0] ,
-    input [AXI_DATA_WIDTH - 1 : 0 ] SpiCsCtrlReg_i [SPI_NUM - 1 : 0] ,
-    input [AXI_DATA_WIDTH - 1 : 0 ] SpiTxRxFifoCtrlReg_i [SPI_NUM - 1 : 0] ,
+    input [AXI_DATA_WIDTH - 1 : 0 ]  SpiCtrlReg_i,
+    input [AXI_DATA_WIDTH - 1 : 0 ] SpiCsDelayReg_i,
+    input [AXI_DATA_WIDTH - 1 : 0 ] SpiClkReg_i,
+    input [AXI_DATA_WIDTH - 1 : 0 ] SpiCsCtrlReg_i,
+    input [AXI_DATA_WIDTH - 1 : 0 ] SpiTxRxFifoCtrlReg_i,
 
     input [AXI_DATA_WIDTH - 1 : 0 ] SpiTxRxEnReg_i,
 
-    output [1:0] WidthSel_o [SPI_NUM - 1 : 0] ,
-    output [SPI_NUM - 1 : 0]        SpiEn_o,
-    output [SPI_NUM - 1 : 0]        SpiMode_o,
-    output [SPI_NUM - 1 : 0]        ClockPol_o,
-    output [SPI_NUM - 1 : 0]        ClockPhase_o,
-    output [SPI_NUM - 1 : 0]        EndianSel_o,
-    output [SPI_NUM - 1 : 0]        SelSt_o,
-    output [SPI_NUM - 1 : 0]        Assel,
-    output [5:0] StopDelay_o [SPI_NUM - 1 : 0] ,
-    output [SPI_NUM - 1 : 0 ]       Lead_o,
-    output [SPI_NUM - 1 : 0 ]       Lag_o,
+    output [1:0] WidthSel_o,
+    output       SpiEn_o,
+    output       SpiMode_o,
+    output       ClockPol_o,
+    output       ClockPhase_o,
+    output       EndianSel_o,
+    output       SelSt_o,
+    output       Assel,
+    output [5:0] StopDelay_o,
+    output       Lead_o,
+    output       Lag_o,
 
-    output [7:0] BaudRate_o [SPI_NUM - 1 : 0] ,
-    output [SPI_NUM - 1 : 0 ]       SpiRst_o,
+    output [7:0] BaudRate_o,
+    output       SpiRst_o,
 
-    output [SPI_NUM - 1 : 0]        FifoRxRst_o,
-    output [SPI_NUM - 1 : 0]        FifoTxRst_o, 
+    output       FifoRxRst_o,
+    output       FifoTxRst_o, 
 
-    output [SPI_NUM - 1 : 0 ]       ChipSelFpga_o,
-    output [SPI_NUM - 1 : 0 ]       ChipSelFlash_o,
-    output [SPI_NUM - 1 : 0 ]       SpiDir_o,
+    output       ChipSelFpga_o,
+    output       ChipSelFlash_o,
+    output       SpiDir_o,
 
-    output [SPI_NUM - 1 : 0]        TxEn_o
+    output       TxEn_o
 
 );
 
 //================================================================================
 //  ASSIGNMENTS
 //================================================================================
-genvar i;
 
-generate 
-    for( i=0; i<SPI_NUM; i=i+1) begin: SPI_SETTINGS
-        assign SpiEn_o[i] = SpiCtrlReg_i[i][0];
-        assign ClockPhase_o[i] = SpiCtrlReg_i[i][1];
-        assign ClockPol_o[i] = SpiCtrlReg_i[i][2];
-        assign Assel[i] = SpiCtrlReg_i[i][3];
-        assign SelSt_o[i] = SpiCtrlReg_i[i][4];
-        assign WidthSel_o[i] = SpiCtrlReg_i[i][6:5];
-        assign SpiMode_o[i] = SpiCtrlReg_i[i][7];
-        assign EndianSel_o[i] = SpiCtrlReg_i[i][8];
+assign SpiEn_o = SpiCtrlReg_i[0];
+assign ClockPhase_o = SpiCtrlReg_i[1];
+assign ClockPol_o = SpiCtrlReg_i[2];
+assign Assel = SpiCtrlReg_i[3];
+assign SelSt_o = SpiCtrlReg_i[4];
+assign WidthSel_o = SpiCtrlReg_i[6:5];
+assign SpiMode_o = SpiCtrlReg_i[7];
+assign EndianSel_o = SpiCtrlReg_i[8];
 
-        assign Lag_o[i] = SpiCsDelayReg_i[i][0];
-        assign Lead_o[i] = SpiClkReg_i[i][1];
-        assign StopDelay_o[i] = SpiCsDelayReg_i[i][7:2];
+assign Lag_o = SpiCsDelayReg_i[0];
+assign Lead_o = SpiClkReg_i[1];
+assign StopDelay_o = SpiCsDelayReg_i[7:2];
 
-        assign BaudRate_o[i] = SpiClkReg_i[i][7:0];
+assign BaudRate_o = SpiClkReg_i[7:0];
 
-        assign FifoRxRst_o[i] = SpiTxRxFifoCtrlReg_i[i][0];
-        assign FifoTxRst_o[i] = SpiTxRxFifoCtrlReg_i[i][32];
+assign FifoRxRst_o = SpiTxRxFifoCtrlReg_i[0];
+assign FifoTxRst_o = SpiTxRxFifoCtrlReg_i[32];
 
-        assign ChipSelFpga_o[i] = SpiCsCtrlReg_i[i][0];
-        assign ChipSelFlash_o[i] = SpiCsCtrlReg_i[i][1];
+assign ChipSelFpga_o = SpiCsCtrlReg_i[0];
+assign ChipSelFlash_o = SpiCsCtrlReg_i[1];
 
-        assign SpiDir_o[i] = (SpiMode_o[i]) ? 1'b1 : 1'b0;
+assign SpiDir_o = (SpiMode_o) ? 1'b1 : 1'b0;
+assign TxEn_o = SpiTxRxEnReg_i;
 
-        assign TxEn_o[i] = SpiTxRxEnReg_i[i];
-    end
-endgenerate 
 
 endmodule

SpiSubSystem/SpiDataMuxer.v

@@ -1,7 +1,7 @@
 module SpiDataMuxer (
     input Clk_i,
     input Rst_i,
-    input Ctrl_i,
+    input PowRstEn_i,
 
     input [31:0] PowRstData_i,
     input [31:0] RegularData_i,
@@ -14,7 +14,7 @@ always @(posedge Clk_i) begin
     if (Rst_i) begin
         Data_o <= 0;
     end else begin
-        if (Ctrl_i) begin
+        if (PowRstEn_i) begin
             Data_o <= PowRstData_i;
         end else begin
             Data_o <= RegularData_i;

SpiSubSystem/SpiSubSystem.v

@@ -21,47 +21,30 @@
 
 module SpiSubSystem #(
 	parameter STAGES = 3,
+	parameter AXI_DATA_WIDTH = 64,
 	parameter CMD_REG_WIDTH = 32,
 	parameter ADDR_REG_WIDTH = 12,
 	parameter WIDTH  = 1,
-    parameter FIFO_NUM = 7,
     parameter ISTEMPRD = 1,
-    parameter ISPOWERRST = 1
+    parameter ISPOWERRST = 1,
+    parameter [AXI_DATA_WIDTH-1:0] SPI_BASE_ADDR = 64'h1000,
+    parameter [AXI_DATA_WIDTH-1:0] RST_MEM_BASE_ADDR = 64'h9000,
+    parameter [AXI_DATA_WIDTH-1:0] TMPRD_ADDR = 64'h9001
 ) 
 (
 	input Clk_i,
 	input SpiClk_i,
 	input Rst_i,
-	input TxEn_i,
-
-	input FifoRxRst_i,
-	input FifoTxRst_i,
-	input FifoRxRstRdPtr_i,
-	input FifoTxRstWrPtr_i,
-
-	input ToFifoVal_i,
-	input ToRstMemVal_i,
-	input [CMD_REG_WIDTH-1:0] ToFifoData_i,
-
-	input [1:0] WidthSel_i,
-	input PulsePol_i,
-	input ClockPhase_i,
-	input EndianSel_i,
-	input Lag_i,
-	input Lead_i,
-	input SelSt_i,
-	input [5:0] Stop_i,
-	input Assel_i,
 
-	input  [FIFO_NUM-1:0] ChipSelFpga_i,
-	input  [FIFO_NUM-1:0] ChipSelFlash_i,
+	input [CMD_REG_WIDTH-1:0] WrData_i,
+	input [CMD_REG_WIDTH-1:0] WrAddr_i,
+	input [CMD_REG_WIDTH-1:0] RdAddr_i,
+	input Val_i,
 
-	input SpiMode_i,
-	input SpiEn_i,
+	input PowRstEn_i,
+	input TxEn_i,
 
-	output [CMD_REG_WIDTH-1:0] TxFifoCtrlReg_o,
-	output [CMD_REG_WIDTH-1:0] RxFifoCtrlReg_o,
-	output [CMD_REG_WIDTH-1:0] DataFromRxFifo_o,
+	output [CMD_REG_WIDTH-1:0] RdData_o,
 
 	output Sck_o,
 	output Ss_o,
@@ -69,15 +52,13 @@ module SpiSubSystem #(
 	output Mosi0_o,
 	inout Mosi1_io,
 	output Mosi2_o,
-	output Mosi3_o,
-
-	input  Ctrl_i,
-	output [31:0] TempData_o
+	output Mosi3_o
 );
 
 //================================================================================
 //	REG/WIRE
 //================================================================================
+
 wire [CMD_REG_WIDTH-1:0] toSpiData;
 wire [CMD_REG_WIDTH-1:0] toSpiDataR;
 wire emptyFlagTx;
@@ -101,21 +82,142 @@ wire [31:0] tempData;
 reg [31:0] tempDataReg;
 wire [31:0] powRstData;
 wire mosi1_o;
+
+/* Spi settings arrays */
+wire [AXI_DATA_WIDTH - 1 : 0] spiCtrlArray;
+wire [AXI_DATA_WIDTH - 1 : 0] spiClkArray;
+wire [AXI_DATA_WIDTH - 1 : 0] spiCsDelayArray;
+wire [AXI_DATA_WIDTH - 1 : 0] spiCsCtrlArray;
+wire [AXI_DATA_WIDTH - 1 : 0] spiTxRxFifoCtrlArray;
+
+/* Common Regs */
+wire [AXI_DATA_WIDTH-1:0] spiTxRxEnReg;
+wire [AXI_DATA_WIDTH-1:0] dataFromRegMap;
+/* Synced Regs */
+wire [AXI_DATA_WIDTH-1:0] spiCtrlRR;
+wire [AXI_DATA_WIDTH-1:0] spiCsDelayRR;
+wire [AXI_DATA_WIDTH-1:0] spiCsCtrlRR;
+wire [AXI_DATA_WIDTH-1:0] spiTxRxFifoCtrlRR;
+
+/* SpiSettings */
+wire [1:0] widthSel;
+wire spiEn;
+wire spiMode;
+wire clockPol;
+wire clockPhase;
+wire endianSel;
+wire selSt;
+wire assel;
+wire [5:0] stopDelay;
+wire lead;
+wire lag;
+wire fifoTxRst;
+wire fifoRxRst;
+wire txEn;
+
+wire chipSelFpga;
+wire chipSelFlash;
+
+wire fifoRxRstRdPtr;
+wire fifoTxRstWrPtr;
+
+wire [CMD_REG_WIDTH-1:0] dataFromRxFifo;
+
 //================================================================================
 //  ASSIGNMENTS
 //================================================================================
-assign valToTxFifoRead  = (SpiMode_i) ? valToTxQ : valToTxR;
 
-assign Mosi1_io = (SpiMode_i) ? mosi1_o : 1'bz;
+assign valToTxFifoRead  = (spiMode) ? valToTxQ : valToTxR;
+
+assign Mosi1_io = (spiMode) ? mosi1_o : 1'bz;
 
 assign TempData_o = tempData;
+
+assign fifoRxRstRdPtr = spiTxRxFifoCtrlArray[32];
+assign fifoTxRstWrPtr = spiTxRxFifoCtrlArray[0];
+
 //================================================================================
 //	CODING
 //================================================================================
-InitRst InitRst_inst
+
+RegMap #(
+    .AXI_DATA_WIDTH (AXI_DATA_WIDTH),
+    .SPI_BASE_ADDR (SPI_BASE_ADDR)
+) RegMap (
+    .Clk_i(s_axi_aclk),
+    .RstN_i(s_axi_aresetn),
+
+    .WrData_i(WrData_i),
+    .WrAddr_i(WrAddr_i),
+    .RdAddr_i(RdAddr_i),
+    .Val_i(Val_i),
+
+    .SpiCtrlReg_o(spiCtrlArray),
+    .SpiClkReg_o(spiClkArray),
+    .SpiCsDelayReg_o(spiCsDelayArray),
+    .SpiCsCtrlReg_o(spiCsCtrlArray),
+    .SpiTxRxFifoCtrlReg_o(spiTxRxFifoCtrlArray),
+
+    .AnsDataReg_o(dataFromRegMap)
+);
+
+/* CDC Block */
+CDC #(
+    .WIDTH              (AXI_DATA_WIDTH),
+    .STAGES             (STAGES)
+) synchronizer
 (
-	.clk_i		(SpiClk_i),
-	.signal_o	(Rst_i)
+    .ClkFast_i          (s_axi_aclk),
+    .ClkSlow_i          (spiClkBus),
+
+    .SpiCtrlReg_i       (spiCtrlArray),
+    .SpiCsCtrlReg_i     (spiCsCtrlArray),
+    .SpiCsDelayReg_i    (spiCsDelayArray),
+    .SpiTxRxFifoCtrlReg_i (spiTxRxFifoCtrlArray),
+
+    .SpiCtrlReg_o       (spiCtrlRR),
+    .SpiCsCtrlReg_o     (spiCsCtrlRR),
+    .SpiCsDelayReg_o    (spiCsDelayRR),
+    .SpiTxRxFifoCtrlReg_o (spiTxRxFifoCtrlRR)
+
+);
+
+/* Spi Settings Block */
+SpiSettings #(
+    .AXI_DATA_WIDTH(AXI_DATA_WIDTH)
+) spiSettings (
+    .SpiCtrlReg_i(spiCtrlRR),
+    .SpiCsDelayReg_i(spiCsDelayRR),
+    .SpiClkReg_i(spiClkArray),
+    .SpiCsCtrlReg_i(spiCsCtrlRR),
+    .SpiTxRxFifoCtrlReg_i(spiTxRxFifoCtrlRR),
+
+    .SpiTxRxEnReg_i(spiTxRxEnReg),
+
+    .WidthSel_o(widthSel),
+    .SpiEn_o(spiEn),
+    .SpiMode_o(spiMode),
+    .ClockPol_o(clockPol),
+    .ClockPhase_o(clockPhase),
+    .EndianSel_o(endianSel),
+    .SelSt_o(selSt),
+    .Assel(assel),
+    .StopDelay_o(stopDelay),
+    .Lead_o(lead),
+    .Lag_o(lag),
+
+    .BaudRate_o(baudRate),
+    .SpiRst_o(SpiRst_o),
+
+    .FifoRxRst_o(fifoRxRst),
+    .FifoTxRst_o(fifoTxRst),
+
+    .ChipSelFpga_o(chipSelFpga),
+    .ChipSelFlash_o(chipSelFlash),
+    .SpiDir_o(SpiDir_o),
+
+    .TxEn_o(txEn)
+
 );
 
 Sync1bit #(
@@ -133,46 +235,45 @@ DataFifoWrapper #(
 	.CMD_REG_WIDTH		(CMD_REG_WIDTH),
 	.ADDR_REG_WIDTH		(ADDR_REG_WIDTH),
 	.STAGES				(STAGES),
-	.FIFO_NUM			(FIFO_NUM)
-) DataFifoWrapper
-(
+	.TX_FIFO_ADDR		(SPI_BASE_ADDR+64'h28),
+	.RX_FIFO_ADDR		(SPI_BASE_ADDR+64'h30)
+) DataFifoWrapper (
 	.WrClk_i			(Clk_i),
 	.RdClk_i			(SpiClk_i),
 
-	.FifoRxRst_i		(FifoRxRst_i),
-	.FifoTxRst_i		(FifoTxRst_i),
-	.FifoRxRstRdPtr_i	(FifoRxRstRdPtr_i),
-	.FifoTxRstWrPtr_i	(FifoTxRstWrPtr_i),
+	.FifoRxRst_i		(fifoRxRst),
+	.FifoTxRst_i		(fifoTxRst),
+	.FifoRxRstRdPtr_i	(),
+	.FifoTxRstWrPtr_i	(),
+
+	.WrData_i			(WrData_i),
+    .WrAddr_i			(WrAddr_i),
+    .RdAddr_i			(RdAddr_i),
+    .Val_i 				(Val_i),
 
-	.ToFifoVal_i		(ToFifoVal_i),
 	.ToFifoRxData_i		(dataToRxFifo),
 	.ToFifoRxWriteVal_i	(valToRxR),
 	.ToFifoTxReadVal_i	(valToTxFifoRead),
-	.ToFifoData_i		(ToFifoData_i),
 
 	.TxFifoCtrlReg_o	(TxFifoCtrlReg_o),
 	.RxFifoCtrlReg_o	(RxFifoCtrlReg_o),
 	.EmptyFlagTx_o		(emptyFlagTx),
-	.DataFromRxFifo_o	(DataFromRxFifo_o),
+	.DataFromRxFifo_o	(dataFromRxFifo),
 	.ToSpiData_o		(toSpiData)
 );
 
-//------------------------------------------------
-//Generating needed amount of calculating channels
 generate
 	if (ISTEMPRD) begin : TempRdSpi
-
-
 		SPIs TempRdSpi
 		(
 			.Clk_i			(SpiClk_i),
-			.Rst_i			(Rst_i | SpiMode_i),
+			.Rst_i			(Rst_i | spiMode),
 			.Sck_i			(sckR),
 			.Ss_i			(ssR),
 			.Mosi0_i		(Mosi1_io),
-			.WidthSel_i		(WidthSel_i),
-			.EndianSel_i	(EndianSel_i),
-			.SelSt_i		(SelSt_i),
+			.WidthSel_i		(widthSel),
+			.EndianSel_i	(endianSel),
+			.SelSt_i		(selSt),
 			.DataToRxFifo_o	(tempData),
 			.Val_o			(tempVal)
 		);
@@ -186,18 +287,27 @@ generate
 				end
 			end
 		end
+
+		assign RdData_o = (RdAddr_i == TMPRD_ADDR) ? tempDataReg : dataFromRxFifo;
+	end else begin
+		assign RdData_o = dataToRxFifo;
 	end
 endgenerate
 
 generate
 	if (ISPOWERRST) begin : PowRstMem
 
-		PowRstMemWrapper PowRstMemWrapper(
+		PowRstMemWrapper #(
+			.RST_MEM_BASE_ADDR(RST_MEM_BASE_ADDR)
+		)
+		PowRstMemWrapper
+		(
    			.Clk_i(Clk_i),
    			.Rst_i(Rst_i),
 	
-   			.WrReq_i(ToRstMemVal_i),
-   			.Data_i(ToFifoData_i),
+   			.WrData_i(WrData_i),
+    		.WrAddr_i(WrAddr_i),
+    		.Val_i(Val_i),
 	
    			.RdReq_i(),
    			.Data_o(powRstData),
@@ -205,30 +315,30 @@ generate
 		);
 
 		SpiDataMuxer SpiDataMuxer(
-    		.Clk_i		(Clk_i),
-    		.Rst_i		(Rst_i),
-    		.Ctrl_i		(Ctrl_i),
+    		.Clk_i			(Clk_i),
+    		.Rst_i			(Rst_i),
+    		.PowRstEn_i		(PowRstEn_i),
 		
-    		.PowRstData_i		(powRstData),
-    		.RegularData_i		(toSpiData),
+    		.PowRstData_i	(powRstData),
+    		.RegularData_i	(toSpiData),
 	
-    		.Data_o		(toSpiDataR)
+    		.Data_o			(toSpiDataR)
 		);
 
 		SPIm SPIm (
 			.Clk_i			(SpiClk_i),
 			.Start_i		(spiTxEnSync),
-			.Rst_i			(Rst_i | SpiMode_i | !SpiEn_i),
+			.Rst_i			(Rst_i | spiMode | !spiEn),
 			.EmptyFlag_i	(emptyFlagTx),
 			.SpiData_i		(toSpiDataR),
-			.WidthSel_i		(WidthSel_i),
-			.PulsePol_i		(PulsePol_i),
-			.ClockPhase_i	(ClockPhase_i),
-			.EndianSel_i	(EndianSel_i),
-			.Lag_i			(Lag_i),
-			.Lead_i			(Lead_i),
-			.Stop_i			(Stop_i),
-			.SelSt_i		(SelSt_i),
+			.WidthSel_i		(widthSel),
+			.PulsePol_i		(clockPol),
+			.ClockPhase_i	(clockPhase),
+			.EndianSel_i	(endianSel),
+			.Lag_i			(lag),
+			.Lead_i			(lead),
+			.Stop_i			(stopDelay),
+			.SelSt_i		(selSt),
 			.Sck_o			(sckR),
 			.Ss_o			(ssR),
 			.Mosi0_o		(mosi0R),
@@ -237,13 +347,13 @@ generate
 
 		SPIs SPIs (
 			.Clk_i			(SpiClk_i),
-			.Rst_i			(Rst_i | SpiMode_i),
+			.Rst_i			(Rst_i | spiMode),
 			.Sck_i			(sckR),
 			.Ss_i			(ssR),
 			.Mosi0_i		(Mosi1_io),
-			.WidthSel_i		(WidthSel_i),
-			.EndianSel_i	(EndianSel_i),
-			.SelSt_i		(SelSt_i),
+			.WidthSel_i		(widthSel),
+			.EndianSel_i	(endianSel),
+			.SelSt_i		(selSt),
 			.DataToRxFifo_o	(dataToRxFifo),
 			.Val_o			(valToRxR)
 		);
@@ -251,17 +361,17 @@ generate
 		QuadSPIm QuadSPIm (
 			.Clk_i			(SpiClk_i),
 			.Start_i		(spiTxEnSync),
-			.Rst_i			(Rst_i | !SpiMode_i | !SpiEn_i),
+			.Rst_i			(Rst_i | !spiMode | !spiEn),
 			.EmptyFlag_i	(emptyFlagTx),
 			.SpiData_i		(toSpiDataR),
-			.WidthSel_i		(WidthSel_i),
-			.PulsePol_i		(PulsePol_i),
-			.ClockPhase_i	(ClockPhase_i),
-			.EndianSel_i	(EndianSel_i),
-			.Lag_i			(Lag_i),
-			.Lead_i			(Lead_i),
-			.Stop_i			(Stop_i),
-			.SelSt_i		(SelSt_i),
+			.WidthSel_i		(widthSel),
+			.PulsePol_i		(clockPol),
+			.ClockPhase_i	(clockPhase),
+			.EndianSel_i	(endianSel),
+			.Lag_i			(lag),
+			.Lead_i			(lead),
+			.Stop_i			(stopDelay),
+			.SelSt_i		(selSt),
 			.Sck_o			(sckQ),
 			.Ss_o			(ssQ),
 			.Mosi0_o		(mosi0Q),
@@ -278,10 +388,10 @@ generate
 			.SckQ_i			(sckQ),
 			.Mosi0R_i		(mosi0R),
 			.Mosi0Q_i		(mosi0Q),
-			.ChipSelFpga_i	(ChipSelFpga_i),
-			.ChipSelFlash_i	(ChipSelFlash_i),
-			.Assel_i		(Assel_i),
-			.SpiMode_i		(SpiMode_i),
+			.ChipSelFpga_i	(chipSelFpga),
+			.ChipSelFlash_i	(chipSelFlash),
+			.Assel_i		(assel),
+			.SpiMode_i		(spiMode),
 			.Ss_o			(Ss_o),
 			.SsFlash_o		(SsFlash_o),
 			.Sck_o			(Sck_o),
@@ -291,17 +401,17 @@ generate
 		SPIm SPIm (
 			.Clk_i			(SpiClk_i),
 			.Start_i		(spiTxEnSync),
-			.Rst_i			(Rst_i | SpiMode_i | !SpiEn_i),
+			.Rst_i			(Rst_i | spiMode | !spiEn),
 			.EmptyFlag_i	(emptyFlagTx),
 			.SpiData_i		(toSpiData),
-			.WidthSel_i		(WidthSel_i),
-			.PulsePol_i		(PulsePol_i),
-			.ClockPhase_i	(ClockPhase_i),
-			.EndianSel_i	(EndianSel_i),
-			.Lag_i			(Lag_i),
-			.Lead_i			(Lead_i),
-			.Stop_i			(Stop_i),
-			.SelSt_i		(SelSt_i),
+			.WidthSel_i		(widthSel),
+			.PulsePol_i		(clockPol),
+			.ClockPhase_i	(clockPhase),
+			.EndianSel_i	(endianSel),
+			.Lag_i			(lag),
+			.Lead_i			(lead),
+			.Stop_i			(stopDelay),
+			.SelSt_i		(selSt),
 			.Sck_o			(sckR),
 			.Ss_o			(ssR),
 			.Mosi0_o		(mosi0R),
@@ -310,13 +420,13 @@ generate
 
 		SPIs SPIs (
 			.Clk_i			(SpiClk_i),
-			.Rst_i			(Rst_i | SpiMode_i),
+			.Rst_i			(Rst_i | spiMode),
 			.Sck_i			(sckR),
 			.Ss_i			(ssR),
 			.Mosi0_i		(Mosi1_io),
-			.WidthSel_i		(WidthSel_i),
-			.EndianSel_i	(EndianSel_i),
-			.SelSt_i		(SelSt_i),
+			.WidthSel_i		(widthSel),
+			.EndianSel_i	(endianSel),
+			.SelSt_i		(selSt),
 			.DataToRxFifo_o	(dataToRxFifo),
 			.Val_o			(valToRxR)
 		);
@@ -324,17 +434,17 @@ generate
 		QuadSPIm QuadSPIm (
 			.Clk_i			(SpiClk_i),
 			.Start_i		(spiTxEnSync),
-			.Rst_i			(Rst_i | !SpiMode_i | !SpiEn_i),
+			.Rst_i			(Rst_i | !spiMode | !spiEn),
 			.EmptyFlag_i	(emptyFlagTx),
 			.SpiData_i		(toSpiData),
-			.WidthSel_i		(WidthSel_i),
-			.PulsePol_i		(PulsePol_i),
-			.ClockPhase_i	(ClockPhase_i),
-			.EndianSel_i	(EndianSel_i),
-			.Lag_i			(Lag_i),
-			.Lead_i			(Lead_i),
-			.Stop_i			(Stop_i),
-			.SelSt_i		(SelSt_i),
+			.WidthSel_i		(widthSel),
+			.PulsePol_i		(clockPol),
+			.ClockPhase_i	(clockPhase),
+			.EndianSel_i	(endianSel),
+			.Lag_i			(lag),
+			.Lead_i			(lead),
+			.Stop_i			(stopDelay),
+			.SelSt_i		(selSt),
 			.Sck_o			(sckQ),
 			.Ss_o			(ssQ),
 			.Mosi0_o		(mosi0Q),
@@ -351,10 +461,10 @@ generate
 			.SckQ_i			(sckQ),
 			.Mosi0R_i		(mosi0R),
 			.Mosi0Q_i		(mosi0Q),
-			.ChipSelFpga_i	(ChipSelFpga_i),
-			.ChipSelFlash_i	(ChipSelFlash_i),
-			.Assel_i		(Assel_i),
-			.SpiMode_i		(SpiMode_i),
+			.ChipSelFpga_i	(chipSelFpga),
+			.ChipSelFlash_i	(chipSelFlash),
+			.Assel_i		(assel),
+			.SpiMode_i		(spiMode),
 			.Ss_o			(Ss_o),
 			.SsFlash_o		(SsFlash_o),
 			.Sck_o			(Sck_o),

Top/EpSubsystem.sv

@@ -1,33 +1,30 @@
 module EpSubSystem #(
     parameter AXI_DATA_WIDTH = 64,
-    parameter SPI_NUM = 1,
+    parameter SPI_NUM = 2,
     parameter AXI_ID_WIDTH = 4,
     parameter STAGES = 3,
     parameter [3:0] ISTEMPRD = 4'b0001,
     parameter [3:0] ISPOWERRST = 4'b0001,
 
-    parameter FIFO_TX1_ADDR = 64'h0000000000001028,
-    parameter FIFO_TX2_ADDR = 64'h0000000000002028,
-    parameter FIFO_TX3_ADDR = 64'h0000000000003028,
-    parameter FIFO_TX4_ADDR = 64'h0000000000004028,
-    parameter FIFO_TX5_ADDR = 64'h0000000000005028,
-    parameter FIFO_TX6_ADDR = 64'h0000000000006028,
-    parameter FIFO_TX7_ADDR = 64'h0000000000007028,
-
-    parameter FIFO_1_READ_ADDR = 64'h0000_0000_0000_1030,
-    parameter FIFO_2_READ_ADDR = 64'h0000_0000_0000_2030,
-    parameter FIFO_3_READ_ADDR = 64'h0000_0000_0000_3030,
-    parameter FIFO_4_READ_ADDR = 64'h0000_0000_0000_4030,
-    parameter FIFO_5_READ_ADDR = 64'h0000_0000_0000_5030,
-    parameter FIFO_6_READ_ADDR = 64'h0000_0000_0000_6030,
-    parameter FIFO_7_READ_ADDR = 64'h0000_0000_0000_7030
+    parameter [AXI_DATA_WIDTH-1:0] SPI_BASE_ADDR = 64'h0000_0000_0000_1000,
+    parameter [AXI_DATA_WIDTH-1:0] RST_MEM_BASE_ADDR = 64'h0000_0000_0000_9000,
+    parameter [AXI_DATA_WIDTH-1:0] FIFO_TX_ADDR_OFFSET = 64'h0000_0000_0000_0028,
+    parameter [AXI_DATA_WIDTH-1:0] FIFO_READ_ADDR_OFFSET = 64'h0000_0000_0000_0030,
+    parameter [AXI_DATA_WIDTH-1:0] FIFO_1_READ_ADDR = 64'h0000_0000_0000_1030,
+    parameter [AXI_DATA_WIDTH-1:0] FIFO_2_READ_ADDR = 64'h0000_0000_0000_2030,
+    parameter [AXI_DATA_WIDTH-1:0] FIFO_3_READ_ADDR = 64'h0000_0000_0000_3030,
+    parameter [AXI_DATA_WIDTH-1:0] FIFO_4_READ_ADDR = 64'h0000_0000_0000_4030,
+    parameter [AXI_DATA_WIDTH-1:0] FIFO_5_READ_ADDR = 64'h0000_0000_0000_5030,
+    parameter [AXI_DATA_WIDTH-1:0] FIFO_6_READ_ADDR = 64'h0000_0000_0000_6030,
+    parameter [AXI_DATA_WIDTH-1:0] FIFO_7_READ_ADDR = 64'h0000_0000_0000_7030
 ) 
 (
     AxiMMBus.master Bus,
 
     /* Ld */
-    input [SPI_NUM-1:0] Ld_i,
-
+    input  [SPI_NUM-1:0] ArbSpiStart_i,
+    input  [SPI_NUM-1:0] ArbSpiRst_i,
+    input  [SPI_NUM-1:0] ArbPowRstEn_i,
 
     output [SPI_NUM-1:0] Mosi0_o, 
     inout  [SPI_NUM-1:0] Mosi1_io,  //inout: when RSPI mode, input; when QSPI mode output; 
@@ -45,74 +42,14 @@ module EpSubSystem #(
 //================================================================================
 //                                  REG/WIRE
 //================================================================================
-/* SPI0 */
-wire [AXI_DATA_WIDTH-1:0] spi0Ctrl;
-wire [AXI_DATA_WIDTH-1:0] spi0Clk;
-wire [AXI_DATA_WIDTH-1:0] spi0CsDelay;
-wire [AXI_DATA_WIDTH-1:0] spi0CsCtrl;
-wire [AXI_DATA_WIDTH-1:0] spi0TxRxFifoCtrl;
-
-/* SPI1 */
-wire [AXI_DATA_WIDTH-1:0] spi1Ctrl;
-wire [AXI_DATA_WIDTH-1:0] spi1Clk;
-wire [AXI_DATA_WIDTH-1:0] spi1CsDelay;
-wire [AXI_DATA_WIDTH-1:0] spi1CsCtrl;
-wire [AXI_DATA_WIDTH-1:0] spi1TxRxFifoCtrl;
-
-/* SPI2 */
-wire [AXI_DATA_WIDTH-1:0] spi2Ctrl;
-wire [AXI_DATA_WIDTH-1:0] spi2Clk;
-wire [AXI_DATA_WIDTH-1:0] spi2CsDelay;
-wire [AXI_DATA_WIDTH-1:0] spi2CsCtrl;
-wire [AXI_DATA_WIDTH-1:0] spi2TxRxFifoCtrl;
-
-/* SPI3 */
-wire [AXI_DATA_WIDTH-1:0] spi3Ctrl;
-wire [AXI_DATA_WIDTH-1:0] spi3Clk;
-wire [AXI_DATA_WIDTH-1:0] spi3CsDelay;
-wire [AXI_DATA_WIDTH-1:0] spi3CsCtrl;
-wire [AXI_DATA_WIDTH-1:0] spi3TxRxFifoCtrl;
-
-/* SPI4 */
-wire [AXI_DATA_WIDTH-1:0] spi4Ctrl;
-wire [AXI_DATA_WIDTH-1:0] spi4Clk;
-wire [AXI_DATA_WIDTH-1:0] spi4CsDelay;
-wire [AXI_DATA_WIDTH-1:0] spi4CsCtrl;
-wire [AXI_DATA_WIDTH-1:0] spi4TxRxFifoCtrl;
-
-/* SPI5 */
-wire [AXI_DATA_WIDTH-1:0] spi5Ctrl;
-wire [AXI_DATA_WIDTH-1:0] spi5Clk;
-wire [AXI_DATA_WIDTH-1:0] spi5CsDelay;
-wire [AXI_DATA_WIDTH-1:0] spi5CsCtrl;
-wire [AXI_DATA_WIDTH-1:0] spi5TxRxFifoCtrl;
-
-/* SPI6 */
-wire [AXI_DATA_WIDTH-1:0] spi6Ctrl;
-wire [AXI_DATA_WIDTH-1:0] spi6Clk;
-wire [AXI_DATA_WIDTH-1:0] spi6CsDelay;
-wire [AXI_DATA_WIDTH-1:0] spi6CsCtrl;
-wire [AXI_DATA_WIDTH-1:0] spi6TxRxFifoCtrl;
-
-/* Spi settings arrays */
-wire [AXI_DATA_WIDTH - 1 : 0] spiCtrlArray [SPI_NUM-1:0];
-wire [AXI_DATA_WIDTH - 1 : 0] spiClkArray [SPI_NUM-1:0];
-wire [AXI_DATA_WIDTH - 1 : 0] spiCsDelayArray [SPI_NUM-1:0];
-wire [AXI_DATA_WIDTH - 1 : 0] spiCsCtrlArray [SPI_NUM-1:0];
-wire [AXI_DATA_WIDTH - 1 : 0] spiTxRxFifoCtrlArray [SPI_NUM-1:0];
 
 /* Common Regs */
 wire [AXI_DATA_WIDTH-1:0] spiTxRxEnReg;
 wire [AXI_DATA_WIDTH-1:0] dataFromRegMap;
-/* Synced Regs */
-wire [AXI_DATA_WIDTH-1:0] spiCtrlRR [SPI_NUM-1:0];
-wire [AXI_DATA_WIDTH-1:0] spiCsDelayRR [SPI_NUM-1:0];
-wire [AXI_DATA_WIDTH-1:0] spiCsCtrlRR [SPI_NUM-1:0];
-wire [AXI_DATA_WIDTH-1:0] spiTxRxFifoCtrlRR [SPI_NUM-1:0];
 
 /* AXI-Slave */
 wire [AXI_DATA_WIDTH-1:0] rdDataToAxiSlave;
-wire [AXI_DATA_WIDTH-1:0] rdAddr;
+wire [AXI_DATA_WIDTH-1:0] rdAddrFromAxiSlave;
 wire [AXI_DATA_WIDTH-1:0] wrDataFromAxiSlave;
 wire [AXI_DATA_WIDTH-1:0] wrAddrFromAxiSlave;
 wire valFromAxiSlave;
@@ -132,28 +69,6 @@ wire [AXI_DATA_WIDTH-1:0] toRegMapAddr;
 wire [7:0] baudRate [SPI_NUM-1:0];
 wire [SPI_NUM-1:0] spiClkBus;
 
-/* SpiSettings */
-wire [1:0] widthSel [SPI_NUM-1:0];
-wire [SPI_NUM-1:0] spiEn;
-wire [SPI_NUM-1:0] spiMode;
-wire [SPI_NUM-1:0] clockPol;
-wire [SPI_NUM-1:0] clockPhase;
-wire [SPI_NUM-1:0] endianSel;
-wire [SPI_NUM-1:0] selSt;
-wire [SPI_NUM-1:0] assel;
-wire [5:0] stopDelay [SPI_NUM-1:0];
-wire [SPI_NUM-1:0] lead;
-wire [SPI_NUM-1:0] lag;
-wire [SPI_NUM-1:0] fifoTxRst;
-wire [SPI_NUM-1:0] fifoRxRst;
-wire [SPI_NUM-1:0] txEn;
-
-wire [SPI_NUM-1:0] chipSelFpga;
-wire [SPI_NUM-1:0] chipSelFlash;
-
-wire [SPI_NUM-1:0] fifoRxRstRdPtr;
-wire [SPI_NUM-1:0] fifoTxRstWrPtr;
-
 /* CDC LD */
 wire [SPI_NUM-1:0] ldReg;
 
@@ -163,14 +78,7 @@ wire [AXI_DATA_WIDTH - 1 : 0]  dataFromRxFifo [SPI_NUM-1:0];
 //================================================================================
 //                          ASSIGNMENTS
 //================================================================================
-genvar j;
 
-generate
-    for (j = 0; j < SPI_NUM; j = j +1) begin : Assignments 
-        assign fifoRxRstRdPtr[j] = spiTxRxFifoCtrlArray[j][32];
-        assign fifoTxRstWrPtr[j] = spiTxRxFifoCtrlArray[j][0];
-    end
-endgenerate
 
 //================================================================================
 //                          CODING
@@ -187,62 +95,10 @@ AxiSlave #(
     .Val_o (valFromAxiSlave),
     .ValToRdFifo_o(valToRdFifo),
     .Data_o (wrDataFromAxiSlave),
-    .RdAddr_o (rdAddr),
+    .RdAddr_o (rdAddrFromAxiSlave),
     .Addr_o (wrAddrFromAxiSlave)
 );
 
-/* Input Mux */
-InputMux #(
-    .AXI_DATA_WIDTH (AXI_DATA_WIDTH),
-    .SPI_NUM        (SPI_NUM),
-    .FIFO_TX1_ADDR  (FIFO_TX1_ADDR),
-    .FIFO_TX2_ADDR  (FIFO_TX2_ADDR),
-    .FIFO_TX3_ADDR  (FIFO_TX3_ADDR),
-    .FIFO_TX4_ADDR  (FIFO_TX4_ADDR),
-    .FIFO_TX5_ADDR  (FIFO_TX5_ADDR),
-    .FIFO_TX6_ADDR  (FIFO_TX6_ADDR),
-    .FIFO_TX7_ADDR  (FIFO_TX7_ADDR)
-) InputMux (
-    .Clk_i(s_axi_aclk),
-    .RstN_i(s_axi_aresetn),
-    .Val_i(valFromAxiSlave),
-    .Addr_i(wrAddrFromAxiSlave),
-    .Data_i(wrDataFromAxiSlave),
-
-    .ToRegMapAddr_o(toRegMapAddr),
-
-    .Val_o(dataBusVal),
-
-    .Data_o(dataBus)
-);
-
-/* Register Map */
-RegMap #(
-    .AXI_DATA_WIDTH (AXI_DATA_WIDTH),
-    .SPI_NUM        (SPI_NUM)
-) RegMap (
-    .Clk_i(s_axi_aclk),
-    .RstN_i(s_axi_aresetn),
-    .WrData_i(dataBus),
-    .WrAddr_i(toRegMapAddr),
-    .RdAddr_i(rdAddr),
-    .Val_i(dataBusVal[SPI_NUM]),
-
-    
-
-    .SpiCtrlReg_o(spiCtrlArray),
-    .SpiClkReg_o(spiClkArray),
-    .SpiCsDelayReg_o(spiCsDelayArray),
-    .SpiCsCtrlReg_o(spiCsCtrlArray),
-    .SpiTxRxFifoCtrlReg_o(spiTxRxFifoCtrlArray),
-
-    .SpiTxRxEnReg_o(spiTxRxEnReg),
-
-    .AnsDataReg_o(dataFromRegMap)
-
-);
-
-/* Clock Manager */
 ClkManager #(
     .SPI_NUM (SPI_NUM),
     .STAGES  (STAGES)
@@ -250,76 +106,17 @@ ClkManager #(
 ) ClkManager
 (
     .Clk_i(s_axi_aclk),
-    .Rst_i(~s_axi_aresetn),
-    .BaudRate_i (baudRate),
-    .SpiClk_o(spiClkBus),
-    .SubSystSyncRst_o(spiSubSysRst)
-
-);
-
-/* CDC Block */
-CDC #(
-    .WIDTH              (AXI_DATA_WIDTH),
-    .STAGES             (STAGES),
-    .SPI_NUM            (SPI_NUM)
-) synchronizer
-(
-    .ClkFast_i          (s_axi_aclk),
-    .ClkSlow_i          (spiClkBus),
-
-    .SpiCtrlReg_i       (spiCtrlArray),
-    .SpiCsCtrlReg_i     (spiCsCtrlArray),
-    .SpiCsDelayReg_i    (spiCsDelayArray),
-    .SpiTxRxFifoCtrlReg_i (spiTxRxFifoCtrlArray),
+    .RstN_i(~s_axi_aresetn),
 
-    .SpiCtrlReg_o       (spiCtrlRR),
-    .SpiCsCtrlReg_o     (spiCsCtrlRR),
-    .SpiCsDelayReg_o    (spiCsDelayRR),
-    .SpiTxRxFifoCtrlReg_o (spiTxRxFifoCtrlRR)
-
-);
+    .WrData_i(wrDataFromAxiSlave),
+    .WrAddr_i(wrAddrFromAxiSlave),
+    .Val_i(valFromAxiSlave),
 
-/* Spi Settings Block */
-SpiSettings #(
-    .AXI_DATA_WIDTH(AXI_DATA_WIDTH),
-    .SPI_NUM(SPI_NUM)
-) spiSettings (
-    .SpiCtrlReg_i(spiCtrlRR),
-    .SpiCsDelayReg_i(spiCsDelayRR),
-    .SpiClkReg_i(spiClkArray),
-    .SpiCsCtrlReg_i(spiCsCtrlRR),
-    .SpiTxRxFifoCtrlReg_i(spiTxRxFifoCtrlRR),
-
-    .SpiTxRxEnReg_i(spiTxRxEnReg),
-
-    .WidthSel_o(widthSel),
-    .SpiEn_o(spiEn),
-    .SpiMode_o(spiMode),
-    .ClockPol_o(clockPol),
-    .ClockPhase_o(clockPhase),
-    .EndianSel_o(endianSel),
-    .SelSt_o(selSt),
-    .Assel(assel),
-    .StopDelay_o(stopDelay),
-    .Lead_o(lead),
-    .Lag_o(lag),
-
-    .BaudRate_o(baudRate),
-    .SpiRst_o(SpiRst_o),
-
-    .FifoRxRst_o(fifoRxRst),
-    .FifoTxRst_o(fifoTxRst),
-
-    .ChipSelFpga_o(chipSelFpga),
-    .ChipSelFlash_o(chipSelFlash),
-    .SpiDir_o(SpiDir_o),
-
-    .TxEn_o(txEn)
+    .SpiClk_o(spiClkBus),
+    .SubSystSyncRst_o(spiSubSysRst)
 
 );
 
-/* Generate block */
-
 genvar i;
 
 generate
@@ -327,46 +124,28 @@ generate
 
         SpiSubSystem #(
             .STAGES             (STAGES),
+            .AXI_DATA_WIDTH     (AXI_DATA_WIDTH),
             .CMD_REG_WIDTH      (AXI_DATA_WIDTH),
             .ADDR_REG_WIDTH     (AXI_DATA_WIDTH),
             .WIDTH              (1),
-            .FIFO_NUM           (SPI_NUM),
             .ISTEMPRD           (ISTEMPRD[i]),
-            .ISPOWERRST         (ISPOWERRST[i])
+            .ISPOWERRST         (ISPOWERRST[i]),
+            .SPI_BASE_ADDR      (SPI_BASE_ADDR*i+64'h1000),
+            .RST_MEM_BASE_ADDR  (RST_MEM_BASE_ADDR*i)
         ) SpiSubSystem (
             .Clk_i(s_axi_aclk),
             .SpiClk_i(spiClkBus[i]),
-            .Rst_i(spiSubSysRst),
-            .TxEn_i(txEn[i]),
-
-            .FifoRxRst_i(fifoRxRst[i]),
-            .FifoTxRst_i(fifoTxRst[i]),
-            .FifoRxRstRdPtr_i(fifoRxRstRdPtr[i]),
-            .FifoTxRstWrPtr_i(fifoTxRstWrPtr[i]),
-
-            .ToFifoVal_i(dataBusVal[i]),
-            .ToRstMemVal_i(dataBusVal[i]),
-            .ToFifoData_i(dataBus),
-
-            .WidthSel_i(widthSel[i]),
-            .PulsePol_i(clockPol[i]),
-            .ClockPhase_i(clockPhase[i]),
-            .EndianSel_i(endianSel[i]),
-            .Lag_i(lag[i]),
-            .Lead_i(lead[i]),
-            .SelSt_i(selSt[i]),
-            .Stop_i(stopDelay[i]),
-            .Assel_i(assel[i]),
-
-            .ChipSelFpga_i(chipSelFpga[i]),
-            .ChipSelFlash_i(chipSelFlash[i]),
-
-            .SpiMode_i(spiMode[i]),
-            .SpiEn_i(spiEn[i]),
-
-            .TxFifoCtrlReg_o(),
-            .RxFifoCtrlReg_o(),
-            .DataFromRxFifo_o(dataFromRxFifo[i]),
+            .Rst_i(spiSubSysRst|ArbSpiRst_i[i]),
+
+            .WrData_i(wrDataFromAxiSlave),
+            .WrAddr_i(wrAddrFromAxiSlave),
+            .RdAddr_i(rdAddrFromAxiSlave),
+            .Val_i(valFromAxiSlave),
+
+            .PowRstEn_i(ArbPowRstEn_i[i]),
+            .TxEn_i(ArbSpiStart_i[i]),
+
+            .RdData_o(dataFromRxFifo[i]),
 
             .Sck_o(Sck_o[i]),
             .Ss_o(Ss_o[i]),
@@ -374,33 +153,16 @@ generate
             .Mosi0_o(Mosi0_o[i]),
             .Mosi1_io(Mosi1_io[i]),
             .Mosi2_o(Mosi2_o[i]),
-            .Mosi3_o(Mosi3_o[i]),
-
-            .Ctrl_i(),
-            .TempData_o()
-        );
-
-        xpm_cdc_single #(
-                .DEST_SYNC_FF       (3),
-                .INIT_SYNC_FF       (0),
-                .SIM_ASSERT_CHK     (0),
-                .SRC_INPUT_REG      (1)
-            )
-            xpm_cdc_single_inst(
-                .dest_out   (ldReg[i]),
-
-                .dest_clk   (s_axi_aclk),
-                .src_clk    (spiClkBus[i]),
-                .src_in     (Ld_i[i])
-            );
-            
+            .Mosi3_o(Mosi3_o[i])
+        );      
     end
 endgenerate
 
 /* Output Mux */
-OutputMux #(
-    .AXI_DATA_WIDTH (AXI_DATA_WIDTH),
-    .SPI_NUM        (SPI_NUM),
+OutputMux 
+#(
+    .AXI_DATA_WIDTH   (AXI_DATA_WIDTH),
+    .SPI_NUM          (SPI_NUM),
     .FIFO_1_READ_ADDR (FIFO_1_READ_ADDR),
     .FIFO_2_READ_ADDR (FIFO_2_READ_ADDR),
     .FIFO_3_READ_ADDR (FIFO_3_READ_ADDR),
@@ -408,13 +170,14 @@ OutputMux #(
     .FIFO_5_READ_ADDR (FIFO_5_READ_ADDR),
     .FIFO_6_READ_ADDR (FIFO_6_READ_ADDR),
     .FIFO_7_READ_ADDR (FIFO_7_READ_ADDR)
-) OutputMux (
+) 
+OutputMux (
     .Clk_i(s_axi_aclk),
     .RstN_i(s_axi_aresetn),
 
     .DataFromRxFifo_i(dataFromRxFifo),
     .DataFromRegMap_i(dataFromRegMap),
-    .Addr_i(rdAddr),
+    .Addr_i(rdAddrFromAxiSlave),
 
     .AnsData_o(rdDataToAxiSlave)
 );