//////////////////////////////////////////////////////////////////////////////////
// Company:			TAIR
// Engineer:		
// 
// Create Date:		10/30/2023 11:24:31 AM
// Design Name:
// Module Name:		CDC
// Project Name:	S5443_V3_FPGA3
// Target Devices:	BOARD: BY5443v3. FPGA: xc7s25csga225-2
// Tool Versions:
// Description: 	
// 
// Dependencies: 	This module synchronizes commands from RegMap to the 
//					respective clock domain.
// 
// Revision:
// Revision 1.0 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
module CDC #(
	parameter WIDTH = 32,
	parameter STAGES = 3,
	parameter SPI_NUM = 7
)
(
	input ClkFast_i,
	input [SPI_NUM-1:0] ClkSlow_i,

	/* Arrays of inputs */
	input [WIDTH-1:0] SpiCtrlReg_i [SPI_NUM-1:0],
	input [WIDTH-1:0] SpiCsCtrlReg_i [SPI_NUM-1:0],
	input [WIDTH-1:0] SpiCsDelayReg_i [SPI_NUM-1:0],
	input [WIDTH-1:0] SpiTxRxFifoCtrlReg_i [SPI_NUM-1:0],

	/* Arrays of outputs */
	output [WIDTH-1:0] SpiCtrlReg_o [SPI_NUM-1:0],
	output [WIDTH-1:0] SpiCsCtrlReg_o [SPI_NUM-1:0],
	output [WIDTH-1:0] SpiCsDelayReg_o [SPI_NUM-1:0],
	output [WIDTH-1:0] SpiTxRxFifoCtrlReg_o [SPI_NUM-1:0]
	
);

//================================================================================
//  REG/WIRE
//================================================================================
/* Arrays of launch registers */
reg [WIDTH-1:0] spiCtrlReg [SPI_NUM-1:0];
reg [WIDTH-1:0] spiCsCtrlReg [SPI_NUM-1:0];
reg [WIDTH-1:0] spiCsDelayReg [SPI_NUM-1:0];
reg [WIDTH-1:0] spiTxRxFifoCtrlReg [SPI_NUM-1:0];

/* Array of capture regs */
(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spiCtrlReg_c [SPI_NUM-1:0];
(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spiCsCtrlReg_c [SPI_NUM-1:0];
(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spiCsDelayReg_c [SPI_NUM-1:0];
(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spiTxRxFifoCtrlReg_c [SPI_NUM-1:0];

//================================================================================
//	ASSIGNMENTS
//================================================================================
genvar i ;
generate 
	for (i = 0; i < SPI_NUM; i = i + 1) begin : CDC_ASSIGN_OUT
		assign SpiCtrlReg_o[i] = spiCtrlReg_c[i][STAGES*WIDTH-1:(STAGES-1)*WIDTH];
		assign SpiCsCtrlReg_o[i] = spiCsCtrlReg_c[i][STAGES*WIDTH-1:(STAGES-1)*WIDTH];
		assign SpiCsDelayReg_o[i] = spiCsDelayReg_c[i][STAGES*WIDTH-1:(STAGES-1)*WIDTH];
		assign SpiTxRxFifoCtrlReg_o[i] = spiTxRxFifoCtrlReg_c[i][STAGES*WIDTH-1:(STAGES-1)*WIDTH];
	end
endgenerate

//================================================================================
//	LOCALPARAMS
//================================================================================

//================================================================================
//	CODING
//================================================================================
always_ff @(posedge ClkFast_i) begin
	spiCtrlReg <= SpiCtrlReg_i;
	spiCsCtrlReg <= SpiCsCtrlReg_i;
	spiCsDelayReg <= SpiCsDelayReg_i;
	spiTxRxFifoCtrlReg <= SpiTxRxFifoCtrlReg_i;
end

generate 
	for (i = 0; i < SPI_NUM; i = i + 1) begin : CDC_GEN
		always_ff @(posedge ClkSlow_i[i]) begin : CDC_CAPTURE
			spiCtrlReg_c[i] <= {spiCtrlReg_c[i][(STAGES-1)*WIDTH-1:0], spiCtrlReg[i]};
			spiCsCtrlReg_c[i] <= {spiCsCtrlReg_c[i][(STAGES-1)*WIDTH-1:0], spiCsCtrlReg[i]};
			spiCsDelayReg_c[i] <= {spiCsDelayReg_c[i][(STAGES-1)*WIDTH-1:0], spiCsDelayReg[i]};
			spiTxRxFifoCtrlReg_c[i] <= {spiTxRxFifoCtrlReg_c[i][(STAGES-1)*WIDTH-1:0], spiTxRxFifoCtrlReg[i]};
		end
	end
endgenerate

endmodule