module MemCtrl (
    input Clk_i,
    input Rst_i,

    input WrReq_i,
    input RdReq_i,

    output reg [5:0] AddrA_o,
    output reg WeA_o,

    output reg [5:0] AddrB_o,
    output reg ReB_o
);

reg [2:0] currState;

localparam IDLE = 2'h0;
localparam WRITE = 2'h1;
localparam READ = 2'h2;

always @(posedge Clk_i) begin
    if (Rst_i) begin
        currState <= IDLE;
    end else begin
        case (currState)
            IDLE: begin
                    if (WrReq_i) begin
                        currState <= WRITE;
                        AddrA_o <= AddrA_o+1;
                        WeA_o <= 1'b1;
                    end else if (RdReq_i)begin
                        currState <= READ;
                        AddrB_o <= AddrB_o+1;
                        ReB_o <= 1'b1;
                    end else begin
                        currState <= IDLE;
                        AddrA_o <= 0;
                        AddrB_o <= 0;
                        WeA_o <= 1'b0;
                        ReB_o <= 1'b0;
                    end
                  end

            WRITE:begin
                    if (WrReq_i) begin
                        currState <= WRITE;
                        AddrA_o <= AddrA_o+1;
                        WeA_o <= 1'b1;
                    end else begin
                        currState <= IDLE;
                        AddrA_o <= 0;
                        WeA_o <= 1'b0;
                    end
                  end

             READ:begin
                    if (RdReq_i) begin
                        currState <= READ;
                        AddrB_o <= AddrB_o+1;
                        ReB_o <= 1'b1;
                    end else begin
                        currState <= IDLE;
                        AddrB_o <= 0;
                        ReB_o <= 1'b0;
                    end
                  end
        endcase
    end
end

endmodule