module RegMap #(
    parameter AXI_DATA_WIDTH = 64,
    parameter SPI_NUM = 7
)(
    input Clk_i,
    input RstN_i,

    input [AXI_DATA_WIDTH-1:0] WrData_i,
    input [AXI_DATA_WIDTH-1:0] WrAddr_i,
    input [AXI_DATA_WIDTH-1:0] RdAddr_i,
    input Val_i,

    output reg [AXI_DATA_WIDTH-1:0] Spi0CtrlReg_o,
    output reg [AXI_DATA_WIDTH-1:0] Spi0ClkReg_o,
    output reg [AXI_DATA_WIDTH-1:0] Spi0CsDelayReg_o,
    output reg [AXI_DATA_WIDTH-1:0] Spi0CsCtrlReg_o,
    output reg [AXI_DATA_WIDTH-1:0] Spi0TxRxFifoCtrlReg_o,

    output reg [AXI_DATA_WIDTH - 1 : 0] SpiCtrlReg_o [SPI_NUM-1 : 0], 
    output reg [AXI_DATA_WIDTH - 1 : 0] SpiClkReg_o [SPI_NUM-1 : 0],
    output reg [AXI_DATA_WIDTH - 1 : 0] SpiCsDelayReg_o [SPI_NUM-1 : 0],
    output reg [AXI_DATA_WIDTH - 1 : 0] SpiCsCtrlReg_o [SPI_NUM-1 : 0],
    output reg [AXI_DATA_WIDTH - 1 : 0] SpiTxRxFifoCtrlReg_o [SPI_NUM-1 : 0],

    output reg [AXI_DATA_WIDTH-1:0] Spi1CtrlReg_o,
    output reg [AXI_DATA_WIDTH-1:0] Spi1ClkReg_o,
    output reg [AXI_DATA_WIDTH-1:0] Spi1CsDelayReg_o,
    output reg [AXI_DATA_WIDTH-1:0] Spi1CsCtrlReg_o,
    output reg [AXI_DATA_WIDTH-1:0] Spi1TxRxFifoCtrlReg_o,

    output reg [AXI_DATA_WIDTH-1:0] Spi2CtrlReg_o,
    output reg [AXI_DATA_WIDTH-1:0] Spi2ClkReg_o,
    output reg [AXI_DATA_WIDTH-1:0] Spi2CsDelayReg_o,
    output reg [AXI_DATA_WIDTH-1:0] Spi2CsCtrlReg_o,
    output reg [AXI_DATA_WIDTH-1:0] Spi2TxRxFifoCtrlReg_o,

    output reg [AXI_DATA_WIDTH-1:0] Spi3CtrlReg_o,
    output reg [AXI_DATA_WIDTH-1:0] Spi3ClkReg_o,
    output reg [AXI_DATA_WIDTH-1:0] Spi3CsDelayReg_o,
    output reg [AXI_DATA_WIDTH-1:0] Spi3CsCtrlReg_o,
    output reg [AXI_DATA_WIDTH-1:0] Spi3TxRxFifoCtrlReg_o,

    output reg [AXI_DATA_WIDTH-1:0] Spi4CtrlReg_o,
    output reg [AXI_DATA_WIDTH-1:0] Spi4ClkReg_o,
    output reg [AXI_DATA_WIDTH-1:0] Spi4CsDelayReg_o,
    output reg [AXI_DATA_WIDTH-1:0] Spi4CsCtrlReg_o,
    output reg [AXI_DATA_WIDTH-1:0] Spi4TxRxFifoCtrlReg_o,

    output reg [AXI_DATA_WIDTH-1:0] Spi5CtrlReg_o,
    output reg [AXI_DATA_WIDTH-1:0] Spi5ClkReg_o,
    output reg [AXI_DATA_WIDTH-1:0] Spi5CsDelayReg_o,
    output reg [AXI_DATA_WIDTH-1:0] Spi5CsCtrlReg_o,
    output reg [AXI_DATA_WIDTH-1:0] Spi5TxRxFifoCtrlReg_o,

    output reg [AXI_DATA_WIDTH-1:0] Spi6CtrlReg_o,
    output reg [AXI_DATA_WIDTH-1:0] Spi6ClkReg_o,
    output reg [AXI_DATA_WIDTH-1:0] Spi6CsDelayReg_o,
    output reg [AXI_DATA_WIDTH-1:0] Spi6CsCtrlReg_o,
    output reg [AXI_DATA_WIDTH-1:0] Spi6TxRxFifoCtrlReg_o,

    output reg [AXI_DATA_WIDTH-1:0] SpiTxRxEnReg_o,
    output reg [AXI_DATA_WIDTH-1:0] SpiTxRxSetReg_o,
    output reg [AXI_DATA_WIDTH-1:0] SpiTxRxClearReg_o,

    output reg [AXI_DATA_WIDTH - 1 : 0 ] AnsDataReg_o

);

//================================================================================
//	LOCALPARAMS
//================================================================================
/* Spi 0 */
localparam  [AXI_DATA_WIDTH-1:0]  SPI0_BASE_ADDR = 64'h0000000000001000;
localparam  [AXI_DATA_WIDTH-1:0]  SPI0_CTRL_ADDR = SPI0_BASE_ADDR + 64'h0000;
localparam  [AXI_DATA_WIDTH-1:0]  SPI0_CLK_ADDR = SPI0_BASE_ADDR + 64'h0008;
localparam  [AXI_DATA_WIDTH-1:0]  SPI0_CS_DELAY_ADDR = SPI0_BASE_ADDR + 64'h0010;
localparam  [AXI_DATA_WIDTH-1:0]  SPI0_CS_CTRL_ADDR = SPI0_BASE_ADDR + 64'h0018;
localparam  [AXI_DATA_WIDTH-1:0]  SPI0_TX_RX_FIFO_CTRL_ADDR = SPI0_BASE_ADDR + 64'h0020;
/* Spi 1 */
localparam  [AXI_DATA_WIDTH-1:0]  SPI1_BASE_ADDR = 64'h0000000000002000;
localparam  [AXI_DATA_WIDTH-1:0]  SPI1_CTRL_ADDR = SPI1_BASE_ADDR + 64'h0000;
localparam  [AXI_DATA_WIDTH-1:0]  SPI1_CLK_ADDR = SPI1_BASE_ADDR + 64'h0008;
localparam  [AXI_DATA_WIDTH-1:0]  SPI1_CS_DELAY_ADDR = SPI1_BASE_ADDR + 64'h0010;
localparam  [AXI_DATA_WIDTH-1:0]  SPI1_CS_CTRL_ADDR = SPI1_BASE_ADDR + 64'h0018;
localparam  [AXI_DATA_WIDTH-1:0]  SPI1_TX_RX_FIFO_CTRL_ADDR = SPI1_BASE_ADDR + 64'h0020;
/* Spi 2 */
localparam  [AXI_DATA_WIDTH-1:0]  SPI2_BASE_ADDR = 64'h0000000000003000;
localparam  [AXI_DATA_WIDTH-1:0]  SPI2_CTRL_ADDR = SPI2_BASE_ADDR + 64'h0000;
localparam  [AXI_DATA_WIDTH-1:0]  SPI2_CLK_ADDR = SPI2_BASE_ADDR + 64'h0008;
localparam  [AXI_DATA_WIDTH-1:0]  SPI2_CS_DELAY_ADDR = SPI2_BASE_ADDR + 64'h0010;
localparam  [AXI_DATA_WIDTH-1:0]  SPI2_CS_CTRL_ADDR = SPI2_BASE_ADDR + 64'h0018;
localparam  [AXI_DATA_WIDTH-1:0]  SPI2_TX_RX_FIFO_CTRL_ADDR = SPI2_BASE_ADDR + 64'h0020;
/* Spi 3 */
localparam  [AXI_DATA_WIDTH-1:0]  SPI3_BASE_ADDR = 64'h0000000000004000;
localparam  [AXI_DATA_WIDTH-1:0]  SPI3_CTRL_ADDR = SPI3_BASE_ADDR + 64'h0000;
localparam  [AXI_DATA_WIDTH-1:0]  SPI3_CLK_ADDR = SPI3_BASE_ADDR + 64'h0008;
localparam  [AXI_DATA_WIDTH-1:0]  SPI3_CS_DELAY_ADDR = SPI3_BASE_ADDR + 64'h0010;
localparam  [AXI_DATA_WIDTH-1:0]  SPI3_CS_CTRL_ADDR = SPI3_BASE_ADDR + 64'h0018;
localparam  [AXI_DATA_WIDTH-1:0]  SPI3_TX_RX_FIFO_CTRL_ADDR = SPI3_BASE_ADDR + 64'h0020;
/* Spi 4 */
localparam  [AXI_DATA_WIDTH-1:0]  SPI4_BASE_ADDR = 64'h0000000000005000;
localparam  [AXI_DATA_WIDTH-1:0]  SPI4_CTRL_ADDR = SPI4_BASE_ADDR + 64'h0000;
localparam  [AXI_DATA_WIDTH-1:0]  SPI4_CLK_ADDR = SPI4_BASE_ADDR + 64'h0008;
localparam  [AXI_DATA_WIDTH-1:0]  SPI4_CS_DELAY_ADDR = SPI4_BASE_ADDR + 64'h0010;
localparam  [AXI_DATA_WIDTH-1:0]  SPI4_CS_CTRL_ADDR = SPI4_BASE_ADDR + 64'h0018;
localparam  [AXI_DATA_WIDTH-1:0]  SPI4_TX_RX_FIFO_CTRL_ADDR = SPI4_BASE_ADDR + 64'h0020;
/* Spi 5 */
localparam  [AXI_DATA_WIDTH-1:0]  SPI5_BASE_ADDR = 64'h0000000000006000;
localparam  [AXI_DATA_WIDTH-1:0]  SPI5_CTRL_ADDR = SPI5_BASE_ADDR + 64'h0000;
localparam  [AXI_DATA_WIDTH-1:0]  SPI5_CLK_ADDR = SPI5_BASE_ADDR + 64'h0008;
localparam  [AXI_DATA_WIDTH-1:0]  SPI5_CS_DELAY_ADDR = SPI5_BASE_ADDR + 64'h0010;
localparam  [AXI_DATA_WIDTH-1:0]  SPI5_CS_CTRL_ADDR = SPI5_BASE_ADDR + 64'h0018;
localparam  [AXI_DATA_WIDTH-1:0]  SPI5_TX_RX_FIFO_CTRL_ADDR = SPI5_BASE_ADDR + 64'h0020;
/* Spi 6 */
localparam  [AXI_DATA_WIDTH-1:0]  SPI6_BASE_ADDR = 64'h0000000000007000;
localparam  [AXI_DATA_WIDTH-1:0]  SPI6_CTRL_ADDR = SPI6_BASE_ADDR + 64'h0000;
localparam  [AXI_DATA_WIDTH-1:0]  SPI6_CLK_ADDR = SPI6_BASE_ADDR + 64'h0008;
localparam  [AXI_DATA_WIDTH-1:0]  SPI6_CS_DELAY_ADDR = SPI6_BASE_ADDR + 64'h0010;
localparam  [AXI_DATA_WIDTH-1:0]  SPI6_CS_CTRL_ADDR = SPI6_BASE_ADDR + 64'h0018;
localparam  [AXI_DATA_WIDTH-1:0]  SPI6_TX_RX_FIFO_CTRL_ADDR = SPI6_BASE_ADDR + 64'h0020;

/* Common */
localparam [AXI_DATA_WIDTH-1:0] SPI_TX_RX_EN_ADDR = SPI6_BASE_ADDR + 64'h0100;
localparam [AXI_DATA_WIDTH-1:0] SPI_TX_RX_SET_REG_ADDR = SPI6_BASE_ADDR + 64'h0108;
localparam [AXI_DATA_WIDTH-1:0] SPI_TX_RX_CLEAR_REG_ADDR = SPI6_BASE_ADDR + 64'h0110;
localparam [AXI_DATA_WIDTH-1:0] SPI_TX_RX_FLAGS_REG_ADDR = SPI6_BASE_ADDR + 64'h0118;
localparam [AXI_DATA_WIDTH-1:0] GPIO_CTRL_ADDR = SPI6_BASE_ADDR + 64'h0120;

//================================================================================
//                                  CODING
//================================================================================
always_ff @(posedge Clk_i) begin
    if (!RstN_i) begin
        for (int i = 0; i < SPI_NUM; i++) begin
            SpiCtrlReg_o[i] <= {AXI_DATA_WIDTH{1'b0}};
            SpiClkReg_o[i] <= {AXI_DATA_WIDTH{1'b0}};
            SpiCsDelayReg_o[i] <= {AXI_DATA_WIDTH{1'b0}};
            SpiCsCtrlReg_o[i] <= {AXI_DATA_WIDTH{1'b0}};
            SpiTxRxFifoCtrlReg_o[i] <= {AXI_DATA_WIDTH{1'b0}};
        end
        SpiTxRxEnReg_o <= {AXI_DATA_WIDTH{1'b0}};
        SpiTxRxSetReg_o <= {AXI_DATA_WIDTH{1'b0}};
        SpiTxRxClearReg_o <= {AXI_DATA_WIDTH{1'b0}};
    end
    else begin
        if (Val_i) begin
            for (int i = 0; i < SPI_NUM; i++) begin
                if (WrAddr_i == (SPI0_CTRL_ADDR + i*64'h1000)) begin
                    SpiCtrlReg_o[i] <= WrData_i;
                end
                else if (WrAddr_i == (SPI0_CLK_ADDR + i*64'h1000)) begin
                    SpiClkReg_o[i] <= WrData_i;
                end
                else if (WrAddr_i == (SPI0_CS_DELAY_ADDR + i*64'h1000)) begin
                    SpiCsDelayReg_o[i] <= WrData_i;
                end
                else if (WrAddr_i == (SPI0_CS_CTRL_ADDR + i*64'h1000)) begin
                    SpiCsCtrlReg_o[i] <= WrData_i;
                end
                else if (WrAddr_i == (SPI0_TX_RX_FIFO_CTRL_ADDR + i*64'h1000)) begin
                    SpiTxRxFifoCtrlReg_o[i] <= WrData_i;
                end
            end
            /* Other Registers */
            if (WrAddr_i == SPI_TX_RX_EN_ADDR) begin
                SpiTxRxEnReg_o <= WrData_i;
            end
            else if (WrAddr_i == SPI_TX_RX_SET_REG_ADDR) begin
                SpiTxRxSetReg_o <= WrData_i;
            end
            else if (WrAddr_i == SPI_TX_RX_CLEAR_REG_ADDR) begin
                SpiTxRxClearReg_o <= WrData_i;
            end
        end
    end
end

/* Read Registers */
// always @(*) begin 
//     if (!RstN_i) begin 
//         AnsDataReg_o = {AXI_DATA_WIDTH{1'b0}};
//     end
//     else begin 
//         case (RdAddr_i)  
//             SPI0_CTRL_ADDR: begin
//                 AnsDataReg_o = Spi0CtrlReg_o;
//             end
//             SPI0_CLK_ADDR: begin
//                 AnsDataReg_o = Spi0ClkReg_o;
//             end
//             SPI0_CS_DELAY_ADDR: begin
//                 AnsDataReg_o = Spi0CsDelayReg_o;
//             end
//             SPI0_CS_CTRL_ADDR: begin
//                 AnsDataReg_o = Spi0CsCtrlReg_o;
//             end
//             SPI0_TX_RX_FIFO_CTRL_ADDR: begin
//                 AnsDataReg_o = Spi0TxRxFifoCtrlReg_o;
//             end
//             SPI1_CTRL_ADDR: begin
//                 AnsDataReg_o = Spi1CtrlReg_o;
//             end
//             SPI1_CLK_ADDR: begin
//                 AnsDataReg_o = Spi1ClkReg_o;
//             end
//             SPI1_CS_DELAY_ADDR: begin
//                 AnsDataReg_o = Spi1CsDelayReg_o;
//             end
//             SPI1_CS_CTRL_ADDR: begin
//                 AnsDataReg_o = Spi1CsCtrlReg_o;
//             end
//             SPI1_TX_RX_FIFO_CTRL_ADDR: begin
//                 AnsDataReg_o = Spi1TxRxFifoCtrlReg_o;
//             end
//             SPI2_CTRL_ADDR: begin
//                 AnsDataReg_o = Spi2CtrlReg_o;
//             end
//             SPI2_CLK_ADDR: begin
//                 AnsDataReg_o = Spi2ClkReg_o;
//             end
//             SPI2_CS_DELAY_ADDR: begin
//                 AnsDataReg_o = Spi2CsDelayReg_o;
//             end
//             SPI2_CS_CTRL_ADDR: begin
//                 AnsDataReg_o = Spi2CsCtrlReg_o;
//             end
//             SPI2_TX_RX_FIFO_CTRL_ADDR: begin
//                 AnsDataReg_o = Spi2TxRxFifoCtrlReg_o;
//             end
//             SPI3_CTRL_ADDR: begin
//                 AnsDataReg_o = Spi3CtrlReg_o;
//             end
//             SPI3_CLK_ADDR: begin
//                 AnsDataReg_o = Spi3ClkReg_o;
//             end
//             SPI3_CS_DELAY_ADDR: begin
//                 AnsDataReg_o = Spi3CsDelayReg_o;
//             end
//             SPI3_CS_CTRL_ADDR: begin
//                 AnsDataReg_o = Spi3CsCtrlReg_o;
//             end
//             SPI3_TX_RX_FIFO_CTRL_ADDR: begin
//                 AnsDataReg_o = Spi3TxRxFifoCtrlReg_o;
//             end
//             SPI4_CTRL_ADDR: begin
//                 AnsDataReg_o = Spi4CtrlReg_o;
//             end
//             SPI4_CLK_ADDR: begin
//                 AnsDataReg_o = Spi4ClkReg_o;
//             end
//             SPI4_CS_DELAY_ADDR: begin
//                 AnsDataReg_o = Spi4CsDelayReg_o;
//             end
//             SPI4_CS_CTRL_ADDR: begin
//                 AnsDataReg_o = Spi4CsCtrlReg_o;
//             end
//             SPI4_TX_RX_FIFO_CTRL_ADDR: begin
//                 AnsDataReg_o = Spi4TxRxFifoCtrlReg_o;
//             end
//             SPI5_CTRL_ADDR: begin
//                 AnsDataReg_o = Spi5CtrlReg_o;
//             end
//             SPI5_CLK_ADDR: begin
//                 AnsDataReg_o = Spi5ClkReg_o;
//             end
//             SPI5_CS_DELAY_ADDR: begin
//                 AnsDataReg_o = Spi5CsDelayReg_o;
//             end
//             SPI5_CS_CTRL_ADDR: begin
//                 AnsDataReg_o = Spi5CsCtrlReg_o;
//             end
//             SPI5_TX_RX_FIFO_CTRL_ADDR: begin
//                 AnsDataReg_o = Spi5TxRxFifoCtrlReg_o;
//             end
//             SPI6_CTRL_ADDR: begin
//                 AnsDataReg_o = Spi6CtrlReg_o;
//             end
//             SPI6_CLK_ADDR: begin
//                 AnsDataReg_o = Spi6ClkReg_o;
//             end
//             SPI6_CS_DELAY_ADDR: begin
//                 AnsDataReg_o = Spi6CsDelayReg_o;
//             end
//             SPI6_CS_CTRL_ADDR: begin
//                 AnsDataReg_o = Spi6CsCtrlReg_o;
//             end
//             SPI6_TX_RX_FIFO_CTRL_ADDR: begin
//                 AnsDataReg_o = Spi6TxRxFifoCtrlReg_o;
//             end
//             SPI_TX_RX_EN_ADDR: begin
//                 AnsDataReg_o = SpiTxRxEnReg_o;
//             end
//             SPI_TX_RX_SET_REG_ADDR: begin
//                 AnsDataReg_o = SpiTxRxSetReg_o;
//             end
//             SPI_TX_RX_CLEAR_REG_ADDR: begin
//                 AnsDataReg_o = SpiTxRxClearReg_o;
//             end
//             default: begin
//                 AnsDataReg_o = {AXI_DATA_WIDTH{1'b0}};
//             end
//         endcase
//     end
// end

always_comb begin 
    if (!RstN_i) begin 
        AnsDataReg_o = {AXI_DATA_WIDTH{1'b0}};
    end
    else begin 
        for (int i = 0; i < SPI_NUM; i++) begin
            if (RdAddr_i == (SPI0_CTRL_ADDR + i*64'h1000)) begin
                AnsDataReg_o = SpiCtrlReg_o[i];
            end
            else if (RdAddr_i == (SPI0_CLK_ADDR + i*64'h1000)) begin
                AnsDataReg_o = SpiClkReg_o[i];
            end
            else if (RdAddr_i == (SPI0_CS_DELAY_ADDR + i*64'h1000)) begin
                AnsDataReg_o = SpiCsDelayReg_o[i];
            end
            else if (RdAddr_i == (SPI0_CS_CTRL_ADDR + i*64'h1000)) begin
                AnsDataReg_o = SpiCsCtrlReg_o[i];
            end
            else if (RdAddr_i == (SPI0_TX_RX_FIFO_CTRL_ADDR + i*64'h1000)) begin
                AnsDataReg_o = SpiTxRxFifoCtrlReg_o[i];
            end
        end
        /* Other Registers */
        if (RdAddr_i == SPI_TX_RX_EN_ADDR) begin
            AnsDataReg_o = SpiTxRxEnReg_o;
        end
        else if (RdAddr_i == SPI_TX_RX_SET_REG_ADDR) begin
            AnsDataReg_o = SpiTxRxSetReg_o;
        end
        else if (RdAddr_i == SPI_TX_RX_CLEAR_REG_ADDR) begin
            AnsDataReg_o = SpiTxRxClearReg_o;
        end
        else begin 
            AnsDataReg_o = {AXI_DATA_WIDTH{1'b0}};
        end
    end
end

endmodule