module SpiSettings
#(
    parameter AXI_DATA_WIDTH = 64,
    parameter SPI_NUM = 7
)(

    input [AXI_DATA_WIDTH - 1 : 0 ]  SpiCtrlReg_i [SPI_NUM - 1 : 0] ,
    input [AXI_DATA_WIDTH - 1 : 0 ] SpiCsDelayReg_i [SPI_NUM - 1 : 0] ,
    input [AXI_DATA_WIDTH - 1 : 0 ] SpiClkReg_i [SPI_NUM - 1 : 0] ,
    input [AXI_DATA_WIDTH - 1 : 0 ] SpiCsCtrlReg_i [SPI_NUM - 1 : 0] ,
    input [AXI_DATA_WIDTH - 1 : 0 ] SpiTxRxFifoCtrlReg_i [SPI_NUM - 1 : 0] ,

    input [AXI_DATA_WIDTH - 1 : 0 ] SpiTxRxEnReg_i,

    output [1:0] WidthSel_o [SPI_NUM - 1 : 0] ,
    output [SPI_NUM - 1 : 0]        SpiEn_o,
    output [SPI_NUM - 1 : 0]        SpiMode_o,
    output [SPI_NUM - 1 : 0]        ClockPol_o,
    output [SPI_NUM - 1 : 0]        ClockPhase_o,
    output [SPI_NUM - 1 : 0]        EndianSel_o,
    output [SPI_NUM - 1 : 0]        SelSt_o,
    output [SPI_NUM - 1 : 0]        Assel,
    output [5:0] StopDelay_o [SPI_NUM - 1 : 0] ,
    output [SPI_NUM - 1 : 0 ]       Lead_o,
    output [SPI_NUM - 1 : 0 ]       Lag_o,

    output [7:0] BaudRate_o [SPI_NUM - 1 : 0] ,
    output [SPI_NUM - 1 : 0 ]       SpiRst_o,

    output [SPI_NUM - 1 : 0]        FifoRxRst_o,
    output [SPI_NUM - 1 : 0]        FifoTxRst_o, 

    output [SPI_NUM - 1 : 0 ]       ChipSelFpga_o,
    output [SPI_NUM - 1 : 0 ]       ChipSelFlash_o,
    output [SPI_NUM - 1 : 0 ]       SpiDir_o,

    output [SPI_NUM - 1 : 0]        TxEn_o

);

//================================================================================
//  ASSIGNMENTS
//================================================================================
genvar i;

generate 
    for( i=0; i<SPI_NUM; i=i+1) begin: SPI_SETTINGS
        assign SpiEn_o[i] = SpiCtrlReg_i[i][0];
        assign ClockPhase_o[i] = SpiCtrlReg_i[i][1];
        assign ClockPol_o[i] = SpiCtrlReg_i[i][2];
        assign Assel[i] = SpiCtrlReg_i[i][3];
        assign SelSt_o[i] = SpiCtrlReg_i[i][4];
        assign WidthSel_o[i] = SpiCtrlReg_i[i][6:5];
        assign SpiMode_o[i] = SpiCtrlReg_i[i][7];
        assign EndianSel_o[i] = SpiCtrlReg_i[i][8];

        assign Lag_o[i] = SpiCsDelayReg_i[i][0];
        assign Lead_o[i] = SpiClkReg_i[i][1];
        assign StopDelay_o[i] = SpiCsDelayReg_i[i][7:2];

        assign BaudRate_o[i] = SpiClkReg_i[i][7:0];

        assign FifoRxRst_o[i] = SpiTxRxFifoCtrlReg_i[i][0];
        assign FifoTxRst_o[i] = SpiTxRxFifoCtrlReg_i[i][32];

        assign ChipSelFpga_o[i] = SpiCsCtrlReg_i[i][0];
        assign ChipSelFlash_o[i] = SpiCsCtrlReg_i[i][1];

        assign SpiDir_o[i] = (SpiMode_o[i]) ? 1'b1 : 1'b0;

        assign TxEn_o[i] = SpiTxRxEnReg_i[i];
    end
endgenerate 

endmodule