//////////////////////////////////////////////////////////////////////////////////
// Company:			TAIR
// Engineer:		
// 
// Create Date:		10/30/2023 11:24:31 AM
// Design Name:
// Module Name:		CDC
// Project Name:	S5443_V3_FPGA3
// Target Devices:	BOARD: BY5443v3. FPGA: xc7s25csga225-2
// Tool Versions:
// Description: 	
// 
// Dependencies: 	This module synchronizes commands from RegMap to the 
//					respective clock domain.
// 
// Revision:
// Revision 1.0 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
module CDC #(
	parameter WIDTH = 32,
	parameter STAGES = 3
)
(
	input ClkFast_i,
	input ClkSlow_i,

	/* Arrays of inputs */
	input [WIDTH-1:0] SpiCtrlReg_i,
	input [WIDTH-1:0] SpiCsCtrlReg_i,
	input [WIDTH-1:0] SpiCsDelayReg_i,
	input [WIDTH-1:0] SpiTxRxFifoCtrlReg_i,

	/* Arrays of outputs */
	output [WIDTH-1:0] SpiCtrlReg_o,
	output [WIDTH-1:0] SpiCsCtrlReg_o,
	output [WIDTH-1:0] SpiCsDelayReg_o,
	output [WIDTH-1:0] SpiTxRxFifoCtrlReg_o
	
);

//================================================================================
//  REG/WIRE
//================================================================================
/* Arrays of launch registers */
reg [WIDTH-1:0] spiCtrlReg;
reg [WIDTH-1:0] spiCsCtrlReg;
reg [WIDTH-1:0] spiCsDelayReg;
reg [WIDTH-1:0] spiTxRxFifoCtrlReg;

/* Array of capture regs */
(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spiCtrlReg_c;
(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spiCsCtrlReg_c;
(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spiCsDelayReg_c;
(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spiTxRxFifoCtrlReg_c;

//================================================================================
//	ASSIGNMENTS
//================================================================================

assign SpiCtrlReg_o = spiCtrlReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign SpiCsCtrlReg_o = spiCsCtrlReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign SpiCsDelayReg_o = spiCsDelayReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign SpiTxRxFifoCtrlReg_o = spiTxRxFifoCtrlReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];

//================================================================================
//	LOCALPARAMS
//================================================================================

//================================================================================
//	CODING
//================================================================================
always_ff @(posedge ClkFast_i) begin
	spiCtrlReg <= SpiCtrlReg_i;
	spiCsCtrlReg <= SpiCsCtrlReg_i;
	spiCsDelayReg <= SpiCsDelayReg_i;
	spiTxRxFifoCtrlReg <= SpiTxRxFifoCtrlReg_i;
end


always_ff @(posedge ClkSlow_i) begin : CDC_CAPTURE
	spiCtrlReg_c <= {spiCtrlReg_c[(STAGES-1)*WIDTH-1:0], spiCtrlReg};
	spiCsCtrlReg_c <= {spiCsCtrlReg_c[(STAGES-1)*WIDTH-1:0], spiCsCtrlReg};
	spiCsDelayReg_c <= {spiCsDelayReg_c[(STAGES-1)*WIDTH-1:0], spiCsDelayReg};
	spiTxRxFifoCtrlReg_c <= {spiTxRxFifoCtrlReg_c[(STAGES-1)*WIDTH-1:0], spiTxRxFifoCtrlReg};
end

endmodule