module SpiSettings
#(
    parameter AXI_DATA_WIDTH = 64,
    parameter SPI_NUM = 1
)(

    input [AXI_DATA_WIDTH - 1 : 0 ]  SpiCtrlReg_i,
    input [AXI_DATA_WIDTH - 1 : 0 ] SpiCsDelayReg_i,
    input [AXI_DATA_WIDTH - 1 : 0 ] SpiClkReg_i,
    input [AXI_DATA_WIDTH - 1 : 0 ] SpiCsCtrlReg_i,
    input [AXI_DATA_WIDTH - 1 : 0 ] SpiTxRxFifoCtrlReg_i,

    input [AXI_DATA_WIDTH - 1 : 0 ] SpiTxRxEnReg_i,

    output [1:0] WidthSel_o,
    output       SpiEn_o,
    output       SpiMode_o,
    output       ClockPol_o,
    output       ClockPhase_o,
    output       EndianSel_o,
    output       SelSt_o,
    output       Assel,
    output [5:0] StopDelay_o,
    output       Lead_o,
    output       Lag_o,

    output [7:0] BaudRate_o,
    output       SpiRst_o,

    output       FifoRxRst_o,
    output       FifoTxRst_o, 

    output       ChipSelFpga_o,
    output       ChipSelFlash_o,
    output       SpiDir_o,

    output       TxEn_o

);

//================================================================================
//  ASSIGNMENTS
//================================================================================

assign SpiEn_o = SpiCtrlReg_i[0];
assign ClockPhase_o = SpiCtrlReg_i[1];
assign ClockPol_o = SpiCtrlReg_i[2];
assign Assel = SpiCtrlReg_i[3];
assign SelSt_o = SpiCtrlReg_i[4];
assign WidthSel_o = SpiCtrlReg_i[6:5];
assign SpiMode_o = SpiCtrlReg_i[7];
assign EndianSel_o = SpiCtrlReg_i[8];

assign Lag_o = SpiCsDelayReg_i[0];
assign Lead_o = SpiClkReg_i[1];
assign StopDelay_o = SpiCsDelayReg_i[7:2];

assign BaudRate_o = SpiClkReg_i[7:0];

assign FifoRxRst_o = SpiTxRxFifoCtrlReg_i[0];
assign FifoTxRst_o = SpiTxRxFifoCtrlReg_i[32];

assign ChipSelFpga_o = SpiCsCtrlReg_i[0];
assign ChipSelFlash_o = SpiCsCtrlReg_i[1];

assign SpiDir_o = (SpiMode_o) ? 1'b1 : 1'b0;
assign TxEn_o = SpiTxRxEnReg_i;


endmodule