module AxiSlaveWrapper #(
    parameter AXI_DATA_WIDTH = 64,
    parameter AXI_ID_WIDTH = 4
)
(
    /* Global Signals */
    (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF S_AXI:S_AXI_CTRL, ASSOCIATED_RESET s_axi_aresetn_i, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0,INSERT_VIP 0" *)
    (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
    input wire                          s_axi_aclk,
    (* X_INTERFACE_INFO = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
    (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
    input wire                          s_axi_aresetn,

    //***********************************************
    //	           SLAVE INTERFACE WRITE
    //***********************************************
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
    input wire [AXI_ID_WIDTH - 1 : 0]       s_axi_awid,   // Write Address ID
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
    input wire [AXI_DATA_WIDTH-1:0]      s_axi_awaddr, // Write Address
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
    input wire [7:0]                     s_axi_awlen, // Burst Length. Exact number of transfers in a burst.
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
    input wire [2:0]                     s_axi_awsize, // Burst Size. Number of bytes in each transfer.
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
    input wire [1:0]                     s_axi_awburst, // Burst Type. Type of burst operation and size determine how the address is incremented.
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
    input wire                           s_axi_awlock, // Write Address Lock
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
    input wire [3:0]                     s_axi_awcache, // Write Address Cache
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
    input wire [2:0]                     s_axi_awprot, // Write Address Protection
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
    input wire                           s_axi_awvalid, // Write Address Valid
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
    output wire                          s_axi_awready, // Write Address Ready
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
    input wire [AXI_DATA_WIDTH-1:0]      s_axi_wdata,// Write Data
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
    input wire [AXI_DATA_WIDTH/8-1:0]    s_axi_wstrb, // Write Strobe. This signal indicates which byte lanes hold valid data.
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
    input wire                           s_axi_wlast, // Write Last. This signal indicates the last transfer in a burst.
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
    input wire                           s_axi_wvalid, // Write Valid. This signal indicates that the write data on the bus is valid.
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
    output wire                          s_axi_wready,
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
    output wire [AXI_ID_WIDTH - 1 : 0]    s_axi_bid,
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
    output wire [1:0]                    s_axi_bresp,
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
    output wire                          s_axi_bvalid,
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
    input wire                           s_axi_bready, // Write Response Ready. This signal indicates that the master is ready to accept a write response.
    //***********************************************
    //	           SLAVE INTERFACE READ
    //***********************************************
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
    input wire [AXI_ID_WIDTH - 1 : 0]    s_axi_arid, // Read Address ID
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
    input wire [AXI_DATA_WIDTH-1:0]      s_axi_araddr, // Read Address. This signal is the address of the first transfer in a burst.
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
    input wire [7:0]                     s_axi_arlen, // Burst Length. Exact number of transfers in a burst.
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
    input wire [2:0]                     s_axi_arsize,
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
    input wire [1:0]                     s_axi_arburst,
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
    input wire                           s_axi_arlock,
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
    input wire [3:0]                     s_axi_arcache,
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
    input wire [2:0]                     s_axi_arprot,
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
    input wire                           s_axi_arvalid,
    /* Output AXI4 FULL Signals */
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
    output wire                          s_axi_arready,
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
    output wire [AXI_ID_WIDTH - 1 : 0]    s_axi_rid,

    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
    output wire [AXI_DATA_WIDTH-1:0]     s_axi_rdata,
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
    output wire [1:0]                    s_axi_rresp,
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
    output wire                          s_axi_rlast,
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
    output wire                          s_axi_rvalid,
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
    input  wire                          s_axi_rready,


    /* User Signals */
    input wire  [AXI_DATA_WIDTH-1:0] RdData_i,
    output wire  Val_o,
    output wire  ValToRdFifo_o,
    output wire [AXI_DATA_WIDTH-1:0] Data_o,
    output wire [AXI_DATA_WIDTH-1:0] RdAddr_o,
    output wire [AXI_DATA_WIDTH-1:0] Addr_o

);



AxiSlave #(
    .AXI_DATA_WIDTH(AXI_DATA_WIDTH)
) axi_slave (
    .s_axi_aclk_i(s_axi_aclk),
    .s_axi_aresetn_i(s_axi_aresetn),
    .s_axi_awaddr_i(s_axi_awaddr),
    .s_axi_awlen_i(s_axi_awlen),
    .s_axi_awsize_i(s_axi_awsize),
    .s_axi_awburst_i(s_axi_awburst),
    .s_axi_awvalid_i(s_axi_awvalid),
    .s_axi_wdata_i(s_axi_wdata),
    .s_axi_wstrb_i(s_axi_wstrb),
    .s_axi_wlast_i(s_axi_wlast),
    .s_axi_wvalid_i(s_axi_wvalid),
    .s_axi_bready_i(s_axi_bready),
    .s_axi_araddr_i(s_axi_araddr),
    .s_axi_arlen_i(s_axi_arlen),
    .s_axi_arsize_i(s_axi_arsize),
    .s_axi_arburst_i(s_axi_arburst),
    .s_axi_arvalid_i(s_axi_arvalid),
    .s_axi_rready_i(s_axi_rready),
    .s_axi_awready_o(s_axi_awready),
    .s_axi_wready_o(s_axi_wready),
    .s_axi_bresp_o(s_axi_bresp),
    .s_axi_bvalid_o(s_axi_bvalid),
    .s_axi_arready_o(s_axi_arready),
    .s_axi_rdata_o(s_axi_rdata),
    .s_axi_rlast_o(s_axi_rlast),
    .s_axi_rresp_o(s_axi_rresp),
    .s_axi_rvalid_o(s_axi_rvalid),


    .RdData_i(RdData_i),
    .Val_o (Val_o),
    .ValToRdFifo_o(ValToRdFifo_o),
    .Data_o (Data_o),
    .RdAddr_o (RdAddr_o),
    .Addr_o (Addr_o)
);




endmodule