//////////////////////////////////////////////////////////////////////////////////
// Company:			TAIR
// Engineer:		
// 
// Create Date:		10/30/2023 11:24:31 AM
// Design Name:
// Module Name:		SpiSubSystem
// Project Name:	S5443_V3_FPGA3
// Target Devices:	BOARD: BY5443v3. FPGA: xc7s25csga225-2
// Tool Versions:
// Description: 	This is a wrapper module that contains FIFO controller and 
//					FIFO modules 
// 
// Dependencies: 
// 
// Revision:
// Revision 1.0 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
module DataFifoWrapper 
#(
	parameter	AXI_DATA_WIDTH	=	64,
	parameter	CMD_REG_WIDTH	=	32,
	parameter	ADDR_REG_WIDTH	=	12,
	parameter	STAGES			=	3,
	parameter	FIFO_NUM		=	1,
	parameter	[AXI_DATA_WIDTH-1:0] TX_FIFO_ADDR	=	64'h28,
	parameter	[AXI_DATA_WIDTH-1:0] RX_FIFO_ADDR	=	64'h30
)
(
	input	WrClk_i,
	input	RdClk_i,

	input	FifoRxRst_i,
	input	FifoTxRst_i,
	input	FifoTxRstWrPtr_i,
	input	FifoRxRstRdPtr_i,

	input [AXI_DATA_WIDTH-1:0] WrData_i,
	input [AXI_DATA_WIDTH-1:0] WrAddr_i,
	input [AXI_DATA_WIDTH-1:0] RdAddr_i,
	input Val_i,

	input	[CMD_REG_WIDTH-1:0]	ToFifoRxData_i,
	input	ToFifoRxWriteVal_i,
	input	ToFifoTxReadVal_i,

	output	[CMD_REG_WIDTH-1:0]	TxFifoCtrlReg_o,
	output	[CMD_REG_WIDTH-1:0]	RxFifoCtrlReg_o,
	output	EmptyFlagTx_o,
	output	[CMD_REG_WIDTH-1:0]	DataFromRxFifo_o,
	output	[CMD_REG_WIDTH-1:0]	ToSpiData_o
);
//================================================================================
//	REG/WIRE
//================================================================================
	wire [CMD_REG_WIDTH-1:0]	dataFromRxFifo;
	wire fullFlagRx;
	wire emptyFlagRx;
	wire fullFlagTx;
	wire emptyFlagTx;

	wire txFifoWrEn;
	wire txFifoRdEn;
	wire rxFifoWrEn;
	wire rxFifoRdEn;

	wire [7:0] rxFifoUpDnCnt;
	wire [7:0] txFifoUpDnCnt;

	wire emptyFlagTxForDsp;
	
	wire valR = (Val_i&(WrAddr_i==TX_FIFO_ADDR));
//================================================================================
//	ASSIGNMENTS
//================================================================================
	assign DataFromRxFifo_o = dataFromRxFifo;
	assign EmptyFlagTx_o = emptyFlagTx;

	assign TxFifoCtrlReg_o = {16'h0, txFifoUpDnCnt, 5'h0, emptyFlagTxForDsp, fullFlagTx, FifoTxRst_i};
	assign RxFifoCtrlReg_o = {16'h0, rxFifoUpDnCnt, 5'h0, emptyFlagRx, fullFlagRx, FifoRxRst_i};

//================================================================================
//	LOCALPARAMS
//================================================================================

//================================================================================
//	CODING
//================================================================================
	FifoCtrl FifoCtrl
	(
		.ToFifoTxWriteVal_i		(valR),
		.ToFifoTxReadVal_i		(ToFifoTxReadVal_i),
		.ToFifoRxWriteVal_i		(ToFifoRxWriteVal_i),
		.ToFifoRxReadVal_i		(),
		.FifoTxFull_i			(fullFlagTx),
		.FifoTxRst_i			(FifoTxRst_i),
		.FifoRxRst_i			(FifoRxRst_i),
		.FifoTxRstWrPtr_i		(FifoTxRstWrPtr_i),
		.FifoRxRstRdPtr_i		(FifoRxRstRdPtr_i),
		.FifoTxEmpty_i			(emptyFlagTx),
		.FifoRxFull_i			(fullFlagRx),
		.EmptyFlagTxForDsp_o	(emptyFlagTxForDsp),
		.FifoRxEmpty_i			(emptyFlagRx),
		.FifoTxWrClock_i		(WrClk_i),
		.FifoTxRdClock_i		(RdClk_i),
		.FifoRxWrClock_i		(RdClk_i),
		.FifoRxRdClock_i		(WrClk_i),
		.RxFifoUpDnCnt_o		(rxFifoUpDnCnt),
		.TxFifoUpDnCnt_o		(txFifoUpDnCnt),
		.FifoTxWriteEn_o		(txFifoWrEn),
		.FifoTxReadEn_o			(txFifoRdEn),
		.FifoRxWriteEn_o		(rxFifoWrEn),
		.FifoRxReadEn_o			(rxFifoRdEn)
	);
	
	FifoTx	DataFifoTx
	( 
		.wr_clk		(WrClk_i), 
		.rd_clk		(RdClk_i), 
		.rst		(FifoTxRst_i),
		.din		(WrData_i), 
		.wr_en		(txFifoWrEn), 
		.rd_en		(txFifoRdEn), 
		.dout		(ToSpiData_o),
		.full		(fullFlagTx), 
		.empty		(emptyFlagTx)
	);
	
	FifoRx	DataFifoRx
	( 
		.wr_clk		(RdClk_i), 
		.rd_clk		(WrClk_i),
		.rst		(FifoRxRst_i), 
		.din		(ToFifoRxData_i), 
		.wr_en		(rxFifoWrEn), 
		.rd_en		(rxFifoRdEn), 
		.dout		(dataFromRxFifo), 
		.full		(fullFlagRx), 
		.empty		(emptyFlagRx)
	);
	
endmodule