module InputMux #(
    parameter AXI_DATA_WIDTH = 64,
    parameter SPI_NUM = 3,
    parameter FIFO_TX1_ADDR = 64'h0000000000001028,
    parameter FIFO_TX2_ADDR = 64'h0000000000002028,
    parameter FIFO_TX3_ADDR = 64'h0000000000003028,
    parameter FIFO_TX4_ADDR = 64'h0000000000004028,
    parameter FIFO_TX5_ADDR = 64'h0000000000005028,
    parameter FIFO_TX6_ADDR = 64'h0000000000006028,
    parameter FIFO_TX7_ADDR = 64'h0000000000007028
)(
    input Clk_i,
    input RstN_i,

    input Val_i,
    input [AXI_DATA_WIDTH-1:0] Data_i,
    input [AXI_DATA_WIDTH-1:0] Addr_i,

    output reg [AXI_DATA_WIDTH-1:0] ToRegMapAddr_o,

    output reg  [SPI_NUM:0] Val_o,

    output reg [AXI_DATA_WIDTH-1:0] Data_o
);
//================================================================================
//	                            LOCALPARAMS
//================================================================================
//================================================================================
//	                             REG/WIRE
//================================================================================

//================================================================================
//	                            CODING
//================================================================================
always @(posedge Clk_i) begin 
    if (!RstN_i) begin 
        Data_o <= {AXI_DATA_WIDTH{1'b0}};
        Val_o <= {AXI_DATA_WIDTH{1'b0}};
    end
    else begin 
        if (Val_i) begin
            Data_o <= Data_i;
            ToRegMapAddr_o <= Addr_i;
            case(Addr_i)
                FIFO_TX1_ADDR:  begin
                                    Val_o[0] <= Val_i;
                                end
                FIFO_TX2_ADDR:  begin
                                    Val_o[1] <= Val_i;
                                end
                FIFO_TX3_ADDR:  begin
                                    Val_o[2] <= Val_i;
                                end
                FIFO_TX4_ADDR:  begin
                                    Val_o[3] <= Val_i;
                                end
                FIFO_TX5_ADDR:  begin
                                    Val_o[4] <= Val_i;
                                end
                FIFO_TX6_ADDR:  begin
                                    Val_o[5] <= Val_i;
                                end
                FIFO_TX7_ADDR:  begin
                                    Val_o[6] <= Val_i;
                                end
                default:    begin 
                                Val_o[SPI_NUM] <= Val_i;
                            end
            endcase
        end
        else begin
            Val_o <= {SPI_NUM{1'b0}};
        end
    end
end

endmodule