module InputMux #(
    parameter AXI_DATA_WIDTH = 64,
    parameter SPI_NUM = 7,
    parameter FIFO_TX1_ADDR = 64'h0000000000001028,
    parameter FIFO_TX2_ADDR = 64'h0000000000002028,
    parameter FIFO_TX3_ADDR = 64'h0000000000003028,
    parameter FIFO_TX4_ADDR = 64'h0000000000004028,
    parameter FIFO_TX5_ADDR = 64'h0000000000005028,
    parameter FIFO_TX6_ADDR = 64'h0000000000006028,
    parameter FIFO_TX7_ADDR = 64'h0000000000007028
)(
    input Clk_i,
    input RstN_i,

    input Val_i,
    input [AXI_DATA_WIDTH-1:0] Data_i,
    input [AXI_DATA_WIDTH-1:0] Addr_i,

    output reg ToRegMapVal_o,
    output reg [AXI_DATA_WIDTH-1:0] ToRegMapData_o,
    output reg [AXI_DATA_WIDTH-1:0] ToRegMapAddr_o,

    output reg  [SPI_NUM-1:0] ToFifoVal_o,
    output reg [AXI_DATA_WIDTH-1:0] ToFifoData_o
);
//================================================================================
//	                            LOCALPARAMS
//================================================================================
//================================================================================
//	                             REG/WIRE
//================================================================================
reg [AXI_DATA_WIDTH-1 : 0] toFifoDataReg;
//================================================================================
//	                            CODING
//================================================================================
always @(posedge Clk_i) begin 
    if (!RstN_i) begin 
        ToRegMapVal_o <= 1'b0;
        ToRegMapData_o <= {AXI_DATA_WIDTH{1'b0}};
        ToRegMapAddr_o <= {AXI_DATA_WIDTH{1'b0}};

        ToFifoVal_o <= {SPI_NUM{1'b0}};
        toFifoDataReg <= {AXI_DATA_WIDTH{1'b0}};
    end
    else begin 
        if (Val_i) begin
            ToRegMapVal_o <= 1'b1;
            ToRegMapData_o <= Data_i;
            ToRegMapAddr_o <= Addr_i;
            ToFifoVal_o <= {SPI_NUM{1'b0}};
            toFifoDataReg <= {AXI_DATA_WIDTH{1'b0}};
            for (int i = 0; i < SPI_NUM; i = i + 1) begin
                if (Addr_i == FIFO_TX1_ADDR + i*1000) begin
                    ToFifoVal_o[i] <= 1'b1;
                    toFifoDataReg <= Data_i;
                end
            end
        end
        else begin
            ToRegMapVal_o <= 1'b0;
            ToRegMapData_o <= {AXI_DATA_WIDTH{1'b0}};
            ToRegMapAddr_o <= {AXI_DATA_WIDTH{1'b0}};

            ToFifoVal_o <= {SPI_NUM{1'b0}};
            toFifoDataReg <= {AXI_DATA_WIDTH{1'b0}};
        end
    end
end

always @(posedge Clk_i) begin 
    ToFifoData_o <= toFifoDataReg;
end

endmodule