module InputMuxTb #(
    parameter AXI_DATA_WIDTH = 64,
    parameter SPI_NUM = 7,
    parameter FIFO_TX1_ADDR = 64'h0000000000001028,
    parameter FIFO_TX2_ADDR = 64'h0000000000002028,
    parameter FIFO_TX3_ADDR = 64'h0000000000003028,
    parameter FIFO_TX4_ADDR = 64'h0000000000004028,
    parameter FIFO_TX5_ADDR = 64'h0000000000005028,
    parameter FIFO_TX6_ADDR = 64'h0000000000006028,
    parameter FIFO_TX7_ADDR = 64'h0000000000007028,
    parameter REGMAP_ADDR = 64'h0000000000001024,
    parameter REGMAP_ADDR1 = 64'h0000000000002008,
    parameter REGMAP_ADDR2 = 64'h0000000000003022
)
();
//================================================================================
//	                            LOCALPARAMS
//================================================================================
//================================================================================
//	                             REG/WIRE
//================================================================================
reg Clk_i;
reg RstN_i;
reg Val_i;
reg [AXI_DATA_WIDTH-1:0] Data_i;
reg [AXI_DATA_WIDTH-1:0] Addr_i;

reg [31:0] tbCnt;
//================================================================================
//	                            CODING
//================================================================================

always #(10/2) Clk_i = ~Clk_i;

initial begin
    Clk_i = 1'b1;
    RstN_i = 1'b0;
    Val_i = 1'b0;
    Data_i = 64'h0;
    Addr_i = 0;

    #100
    RstN_i = 1'b1;
end

always @(posedge Clk_i) begin
    if (!RstN_i) begin
        tbCnt <= 0;
    end else begin
        tbCnt <= tbCnt+1;
    end
end

always @(posedge Clk_i) begin
    if (!RstN_i) begin
        Data_i <= 0;
        Addr_i <= 0;
        Val_i  <= 0;
    end else begin
        case(tbCnt) 
            30: begin
                    Data_i <= 64'h1;
                    Addr_i <= FIFO_TX1_ADDR;
                    Val_i  <= 1;
                end
            35: begin
                    Data_i <= 64'h1;
                    Addr_i <= FIFO_TX2_ADDR;
                    Val_i  <= 1;
                end
            40: begin
                    Data_i <= 64'h1;
                    Addr_i <= FIFO_TX3_ADDR;
                    Val_i  <= 1;
                end
            45: begin
                    Data_i <= 64'h1;
                    Addr_i <= REGMAP_ADDR;
                    Val_i  <= 1;
                end
            50: begin
                    Data_i <= 64'h1;
                    Addr_i <= REGMAP_ADDR;
                    Val_i  <= 1;
                end
            55: begin
                    Data_i <= 64'h1;
                    Addr_i <= REGMAP_ADDR1;
                    Val_i  <= 1;
                end
            60: begin
                    Data_i <= 64'h1;
                    Addr_i <= REGMAP_ADDR2;
                    Val_i  <= 1;
                end
            default:    begin
                            Val_i <= 0;
                        end
        endcase
    end
end

InputMux InputMux
(
    .Clk_i      (Clk_i),
    .RstN_i     (RstN_i),

    .Val_i      (Val_i),
    .Data_i     (Data_i),
    .Addr_i     (Addr_i),

    .ToRegMapAddr_o (),

    .Val_o  (),

    .Data_o ()
);

endmodule