module PowRstMemWrapper #(
    parameter AXI_DATA_WIDTH = 64,
    parameter RST_MEM_BASE_ADDR = 64'h1000
)
(
    input Clk_i,
    input Rst_i,

    input [AXI_DATA_WIDTH-1:0] WrData_i,
    input [AXI_DATA_WIDTH-1:0] WrAddr_i,
    input Val_i,

    input RdReq_i,
    output [AXI_DATA_WIDTH-1:0] Data_o,
    output reg DataVal_o
);

wire [5:0] addrA;
wire [5:0] addrB;

wire weA;
wire reB;

wire wrReq = (Val_i&(WrAddr_i==RST_MEM_BASE_ADDR));

MemCtrl MemCtrl
(
    .Clk_i(Clk_i),
    .Rst_i(Rst_i),
    .WrReq_i(wrReq),
    .RdReq_i(RdReq_i),

    .AddrA_o(addrA),
    .WeA_o(weA),

    .AddrB_o(addrB),
    .ReB_o(reB)
);

PowRstCmdMem PowRstMem 
(
    .clka(Clk_i),    // input wire clka
    .ena(1'b1),      // input wire ena
    .wea(weA),      // input wire [0 : 0] wea
    .addra(addrA),  // input wire [5 : 0] addra
    .dina(WrData_i),    // input wire [31 : 0] dina
    .clkb(Clk_i),    // input wire clkb
    .enb(reB),      // input wire enb
    .addrb(addrB),  // input wire [5 : 0] addrb
    .doutb(Data_o)  // output wire [31 : 0] doutb
);

always @(posedge Clk_i) begin
    if (Rst_i) begin
        DataVal_o <= 0;
    end else begin
        DataVal_o <= reB;
    end
end

endmodule