module EpSubSystem #(
    parameter AXI_DATA_WIDTH = 64,
    parameter SPI_NUM = 2,
    parameter AXI_ID_WIDTH = 4,
    parameter STAGES = 3,
    parameter [3:0] ISTEMPRD = 4'b0001,
    parameter [3:0] ISPOWERRST = 4'b0001,

    parameter [AXI_DATA_WIDTH-1:0] SPI_BASE_ADDR = 64'h0000_0000_0000_1000,
    parameter [AXI_DATA_WIDTH-1:0] RST_MEM_BASE_ADDR = 64'h0000_0000_0000_9000,
    parameter [AXI_DATA_WIDTH-1:0] FIFO_TX_ADDR_OFFSET = 64'h0000_0000_0000_0028,
    parameter [AXI_DATA_WIDTH-1:0] FIFO_READ_ADDR_OFFSET = 64'h0000_0000_0000_0030,
    parameter [AXI_DATA_WIDTH-1:0] FIFO_1_READ_ADDR = 64'h0000_0000_0000_1030,
    parameter [AXI_DATA_WIDTH-1:0] FIFO_2_READ_ADDR = 64'h0000_0000_0000_2030,
    parameter [AXI_DATA_WIDTH-1:0] FIFO_3_READ_ADDR = 64'h0000_0000_0000_3030,
    parameter [AXI_DATA_WIDTH-1:0] FIFO_4_READ_ADDR = 64'h0000_0000_0000_4030,
    parameter [AXI_DATA_WIDTH-1:0] FIFO_5_READ_ADDR = 64'h0000_0000_0000_5030,
    parameter [AXI_DATA_WIDTH-1:0] FIFO_6_READ_ADDR = 64'h0000_0000_0000_6030,
    parameter [AXI_DATA_WIDTH-1:0] FIFO_7_READ_ADDR = 64'h0000_0000_0000_7030
) 
(
    AxiMMBus.master Bus,

    /* Ld */
    input  [SPI_NUM-1:0] ArbSpiStart_i,
    input  [SPI_NUM-1:0] ArbSpiRst_i,
    input  [SPI_NUM-1:0] ArbPowRstEn_i,

    output [SPI_NUM-1:0] Mosi0_o, 
    inout  [SPI_NUM-1:0] Mosi1_io,  //inout: when RSPI mode, input; when QSPI mode output; 
    output [SPI_NUM-1:0] Mosi2_o,
    output [SPI_NUM-1:0] Mosi3_o,
    output [SPI_NUM-1:0] Ss_o,
    output [SPI_NUM-1:0] SsFlash_o,
    output [SPI_NUM-1:0] Sck_o,
    output [SPI_NUM-1:0] SpiRst_o,
    output [SPI_NUM-1:0] SpiDir_o,

    output LD_o
);

//================================================================================
//                                  REG/WIRE
//================================================================================

/* Common Regs */
wire [AXI_DATA_WIDTH-1:0] spiTxRxEnReg;
wire [AXI_DATA_WIDTH-1:0] dataFromRegMap;

/* AXI-Slave */
wire [AXI_DATA_WIDTH-1:0] rdDataToAxiSlave;
wire [AXI_DATA_WIDTH-1:0] rdAddrFromAxiSlave;
wire [AXI_DATA_WIDTH-1:0] wrDataFromAxiSlave;
wire [AXI_DATA_WIDTH-1:0] wrAddrFromAxiSlave;
wire valFromAxiSlave;
wire valToRdFifo;

/* Input Mux */
wire [AXI_DATA_WIDTH-1:0] toFifoData;
wire [SPI_NUM-1:0] toFifoVal;
wire [AXI_DATA_WIDTH-1:0] toRegMapData;
wire [AXI_DATA_WIDTH-1:0] dataBus;
wire [SPI_NUM:0] dataBusVal;

wire toRegMapVal;
wire [AXI_DATA_WIDTH-1:0] toRegMapAddr;

/* Clock Manager */
wire [7:0] baudRate [SPI_NUM-1:0];
wire [SPI_NUM-1:0] spiClkBus;

/* CDC LD */
wire [SPI_NUM-1:0] ldReg;

/* Output Mux */
wire [AXI_DATA_WIDTH - 1 : 0]  dataFromRxFifo [SPI_NUM-1:0]; 

//================================================================================
//                          ASSIGNMENTS
//================================================================================


//================================================================================
//                          CODING
//================================================================================

AxiMMBus #(.AXI_DATA_WIDTH(AXI_DATA_WIDTH)) AxiBus();

AxiSlave #(
    .AXI_DATA_WIDTH(AXI_DATA_WIDTH)
) axi_slave (
    .Bus(Bus),

    .RdData_i(rdDataToAxiSlave),
    .Val_o (valFromAxiSlave),
    .ValToRdFifo_o(valToRdFifo),
    .Data_o (wrDataFromAxiSlave),
    .RdAddr_o (rdAddrFromAxiSlave),
    .Addr_o (wrAddrFromAxiSlave)
);

ClkManager #(
    .SPI_NUM (SPI_NUM),
    .STAGES  (STAGES)

) ClkManager
(
    .Clk_i(s_axi_aclk),
    .RstN_i(~s_axi_aresetn),

    .WrData_i(wrDataFromAxiSlave),
    .WrAddr_i(wrAddrFromAxiSlave),
    .Val_i(valFromAxiSlave),

    .SpiClk_o(spiClkBus),
    .SubSystSyncRst_o(spiSubSysRst)

);

genvar i;

generate
    for (i = 0; i < SPI_NUM; i = i + 1) begin : SpiSubSystem

        SpiSubSystem #(
            .STAGES             (STAGES),
            .AXI_DATA_WIDTH     (AXI_DATA_WIDTH),
            .CMD_REG_WIDTH      (AXI_DATA_WIDTH),
            .ADDR_REG_WIDTH     (AXI_DATA_WIDTH),
            .WIDTH              (1),
            .ISTEMPRD           (ISTEMPRD[i]),
            .ISPOWERRST         (ISPOWERRST[i]),
            .SPI_BASE_ADDR      (SPI_BASE_ADDR*i+64'h1000),
            .RST_MEM_BASE_ADDR  (RST_MEM_BASE_ADDR*i)
        ) SpiSubSystem (
            .Clk_i(s_axi_aclk),
            .SpiClk_i(spiClkBus[i]),
            .Rst_i(spiSubSysRst|ArbSpiRst_i[i]),

            .WrData_i(wrDataFromAxiSlave),
            .WrAddr_i(wrAddrFromAxiSlave),
            .RdAddr_i(rdAddrFromAxiSlave),
            .Val_i(valFromAxiSlave),

            .PowRstEn_i(ArbPowRstEn_i[i]),
            .TxEn_i(ArbSpiStart_i[i]),

            .RdData_o(dataFromRxFifo[i]),

            .Sck_o(Sck_o[i]),
            .Ss_o(Ss_o[i]),
            .SsFlash_o(SsFlash_o[i]),
            .Mosi0_o(Mosi0_o[i]),
            .Mosi1_io(Mosi1_io[i]),
            .Mosi2_o(Mosi2_o[i]),
            .Mosi3_o(Mosi3_o[i])
        );      
    end
endgenerate

/* Output Mux */
OutputMux 
#(
    .AXI_DATA_WIDTH   (AXI_DATA_WIDTH),
    .SPI_NUM          (SPI_NUM),
    .FIFO_1_READ_ADDR (FIFO_1_READ_ADDR),
    .FIFO_2_READ_ADDR (FIFO_2_READ_ADDR),
    .FIFO_3_READ_ADDR (FIFO_3_READ_ADDR),
    .FIFO_4_READ_ADDR (FIFO_4_READ_ADDR),
    .FIFO_5_READ_ADDR (FIFO_5_READ_ADDR),
    .FIFO_6_READ_ADDR (FIFO_6_READ_ADDR),
    .FIFO_7_READ_ADDR (FIFO_7_READ_ADDR)
) 
OutputMux (
    .Clk_i(s_axi_aclk),
    .RstN_i(s_axi_aresetn),

    .DataFromRxFifo_i(dataFromRxFifo),
    .DataFromRegMap_i(dataFromRegMap),
    .Addr_i(rdAddrFromAxiSlave),

    .AnsData_o(rdDataToAxiSlave)
);


        




endmodule