EpSubsystem/DataFifo/FifoCtrl.v

//////////////////////////////////////////////////////////////////////////////////
// Company:         TAIR
// Engineer:        
// 
// Create Date:     10/30/2023 11:24:31 AM
// Design Name:
// Module Name:     FifoCtrl
// Project Name:    S5443_V3_FPGA3
// Target Devices:  BOARD: BY5443v3. FPGA: xc7s25csga225-2
// Tool Versions:
// Description:     This module generate controll signals for FIFO's 
// 
// Dependencies: 
// 
// Revision:
// Revision 1.0 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module FifoCtrl #(
	parameter STAGES = 3,
	parameter AXI_WIDTH = 64,
	parameter FIFO_1_READ_ADDR = 64'h0000_0000_0000_1030,
    parameter FIFO_2_READ_ADDR = 64'h0000_0000_0000_2030,
    parameter FIFO_3_READ_ADDR = 64'h0000_0000_0000_3030,
    parameter FIFO_4_READ_ADDR = 64'h0000_0000_0000_4030,
    parameter FIFO_5_READ_ADDR = 64'h0000_0000_0000_5030,
    parameter FIFO_6_READ_ADDR = 64'h0000_0000_0000_6030,
    parameter FIFO_7_READ_ADDR = 64'h0000_0000_0000_7030
)
(
	input ToFifoTxWriteVal_i,
	input ToFifoTxReadVal_i,
	input ToFifoRxWriteVal_i,
	input ToFifoRxReadVal_i,

	input FifoTxFull_i,
	input FifoTxEmpty_i,
	input FifoRxFull_i,
	input FifoRxEmpty_i,

	input FifoTxWrClock_i,
	input FifoTxRdClock_i,
	input FifoRxWrClock_i,
	input FifoRxRdClock_i,

	input [63:0] Addr_i,

	input FifoTxRst_i,
	input FifoRxRst_i,

	input FifoTxRstWrPtr_i,
	input FifoRxRstRdPtr_i,

	output [7:0] RxFifoUpDnCnt_o,
	output [7:0] TxFifoUpDnCnt_o,

	output EmptyFlagTxForDsp_o,

	output FifoTxWriteEn_o,
	output FifoTxReadEn_o,
	output FifoRxWriteEn_o,
	output FifoRxReadEn_o
);

//================================================================================
//  REG/WIRE
//================================================================================
	reg fifoTxWriteEn;
	reg fifoTxReadEn;
	reg fifoRxWriteEn;
	reg fifoRxReadEn;
	
	reg [7:0] txFifoWrPtr;
	reg [7:0] txFifoRdPtr;
	reg [7:0] rxFifoWrPtr;
	reg [7:0] rxFifoRdPtr;
	
	reg [7:0] rxFifoUpDnCnt;
	reg [7:0] txFifoUpDnCnt;
	
	reg [1:0] readEnCnt;
	reg emptyFlagTxForDsp;    
		
	wire [7:0] rxFifoWrPtrSync;
	wire [7:0] txFifoWrPtrSync;
	wire [7:0] txFifoRdPtrSync;

	wire rxFifoRstSync;

	wire requestToFifo0	= (Addr_i == FIFO_1_READ_ADDR) ? 1'b1 : 1'b0;
	wire requestToFifo1	= (Addr_i == FIFO_2_READ_ADDR) ? 1'b1 : 1'b0;
	wire requestToFifo2	= (Addr_i == FIFO_3_READ_ADDR) ? 1'b1 : 1'b0;
	wire requestToFifo3	= (Addr_i == FIFO_4_READ_ADDR) ? 1'b1 : 1'b0;
	wire requestToFifo4	= (Addr_i == FIFO_5_READ_ADDR) ? 1'b1 : 1'b0;
	wire requestToFifo5	= (Addr_i == FIFO_6_READ_ADDR) ? 1'b1 : 1'b0;
	wire requestToFifo6	= (Addr_i == FIFO_7_READ_ADDR) ? 1'b1 : 1'b0;
	
	wire requestToFifo	= (requestToFifo0|requestToFifo1|requestToFifo2|requestToFifo3|requestToFifo4|requestToFifo5|requestToFifo6) ? 1'b1 : 1'b0;

//================================================================================
//	ASSIGNMENTS
//================================================================================	
	assign FifoTxWriteEn_o = fifoTxWriteEn;
	assign FifoTxReadEn_o = fifoTxReadEn;
	assign FifoRxWriteEn_o = fifoRxWriteEn;
	assign FifoRxReadEn_o = fifoRxReadEn;
	
	assign RxFifoUpDnCnt_o = rxFifoUpDnCnt;
	assign TxFifoUpDnCnt_o = txFifoUpDnCnt;
	
	assign EmptyFlagTxForDsp_o = emptyFlagTxForDsp;
	
//================================================================================
//	LOCALPARAMS
//================================================================================

//================================================================================
//	CODING
//================================================================================
	RxFifoPtrSync #(
		.WIDTH	(8),
		.STAGES	(STAGES)
	)
	rxFifoPtrSync (
		.ClkFast_i		(FifoRxWrClock_i),
		.ClkSlow_i		(FifoRxRdClock_i),
		.RxFifoWrPtr_i	(rxFifoWrPtr),
		.RxFifoWrPtr_o	(rxFifoWrPtrSync)
	);

	TxFifoPtrSync #(
		.WIDTH	(8),
		.STAGES	(STAGES)
	)
	txFifoPtrSync (
		.ClkFast_i(FifoTxRdClock_i),
		.ClkSlow_i(FifoTxWrClock_i),
		.TxFifoWrPtr_i(txFifoRdPtr),
		.TxFifoWrPtr_o(txFifoRdPtrSync)
	);
	
	always @(posedge FifoTxWrClock_i) begin 
		if (ToFifoTxWriteVal_i && !FifoTxFull_i) begin 
			fifoTxWriteEn <= 1'b1;
		end
		else begin 
			fifoTxWriteEn <= 1'b0;
		end
	end
	
	always @(posedge FifoTxRdClock_i) begin 
		if (ToFifoTxReadVal_i && !FifoTxEmpty_i) begin 
			fifoTxReadEn <= 1'b1;
		end
		else begin 
			fifoTxReadEn <= 1'b0;
		end
	end
	
	always @(posedge FifoRxWrClock_i) begin 
		if (ToFifoRxWriteVal_i && !FifoRxFull_i) begin 
			fifoRxWriteEn <= 1'b1;
		end
		else begin 
			fifoRxWriteEn <= 1'b0;
		end
	end
	
	always @(*) begin 
		if (ToFifoRxReadVal_i && !FifoRxEmpty_i) begin 
			fifoRxReadEn = 1'b1;
		end
		else begin 
			fifoRxReadEn = 1'b0;
		end
	end
	
	always @(posedge FifoTxWrClock_i) begin 
		if (FifoTxRstWrPtr_i) begin 
			txFifoWrPtr <= 8'h0;
		end
		else begin 
			if (fifoTxWriteEn  ) begin 
				txFifoWrPtr <= txFifoWrPtr + 1'b1;
			end
		end
	end
	
	always @(posedge FifoTxRdClock_i) begin 
		if (FifoTxRst_i) begin 
			txFifoRdPtr <= 8'h0;
		end
		else begin 
			if (fifoTxReadEn) begin 
				txFifoRdPtr <= txFifoRdPtr + 1'b1;
			end
		end
	end
	
	always @(posedge FifoRxWrClock_i) begin 
		if (FifoRxRst_i) begin 
			rxFifoWrPtr <= 8'h0;
		end
		else begin
			if (fifoRxWriteEn) begin 
				rxFifoWrPtr <= rxFifoWrPtr + 1'b1;
			end
		end
	end
	
	always @(posedge FifoRxRdClock_i) begin 
		if (FifoRxRstRdPtr_i) begin 
			rxFifoRdPtr <= 8'h0;
		end
		else begin 
			if (fifoRxReadEn) begin 
				rxFifoRdPtr <= rxFifoRdPtr + 1'b1;
			end
		end
	end
	
	always @(posedge FifoRxRdClock_i) begin 
		if (FifoRxRstRdPtr_i) begin 
			rxFifoUpDnCnt <= 8'h0;
		end
		else begin 
			rxFifoUpDnCnt <= rxFifoWrPtrSync - rxFifoRdPtr;
		end
	end
	
	always @(posedge FifoTxWrClock_i) begin 
		if (FifoTxRst_i) begin 
			txFifoUpDnCnt <= 8'h0;
		end
		else begin 
			txFifoUpDnCnt <= txFifoWrPtr - txFifoRdPtrSync;
		end
	end

	always @(*) begin
		if (txFifoUpDnCnt == 8'h0) begin
			emptyFlagTxForDsp <= 1'b1;
		end
		else begin
			emptyFlagTxForDsp <= 1'b0;
		end
	end
	
endmodule