EpSubsystem/Interface/AxiMMBus.sv

/* AXI FULL SLAVE */
interface AxiMMBus #(parameter AXI_DATA_WIDTH = 64);
    /* Global Signals */
    logic                                  s_axi_aclk_i;
    logic                                  s_axi_aresetn_i;

    /* Input AXI4 FULL Signals */
    logic [AXI_DATA_WIDTH-1:0]             s_axi_awaddr_i; // Write Address
    logic [7:0]                            s_axi_awlen_i; // Burst Length. Exact number of transfers in a burst.
    logic [2:0]                            s_axi_awsize_i; // Burst Size. Number of bytes in each transfer.

    /* Burst type. FIXED: 00, INCR: 01, WRAP: 10, Reserved: 11 */
    /* INCR - Incrementing burst. The address increments by the data width for each transfer. */
    /* WRAP - Wrapping burst. The address increments by the data width for each transfer, but the address does not increment to the next address when the burst wraps. */
    /* FIXED - Fixed burst. The address does not increment for the burst. */
    logic [1:0]                            s_axi_awburst_i; // Burst Type. Type of burst operation and size determine how the address is incremented.
    logic                                  s_axi_awvalid_i; // Write Address Valid
    logic [AXI_DATA_WIDTH-1:0]             s_axi_wdata_i;// Write Data
    logic [AXI_DATA_WIDTH/8-1:0]           s_axi_wstrb_i; // Write Strobe. This signal indicates which byte lanes hold valid data.
    logic                                  s_axi_wlast_i; // Write Last. This signal indicates the last transfer in a burst.
    logic                                  s_axi_wvalid_i; // Write Valid. This signal indicates that the write data on the bus is valid.
    logic                                  s_axi_bready_i; // Write Response Ready. This signal indicates that the master is ready to accept a write response.
    logic [AXI_DATA_WIDTH-1:0]             s_axi_araddr_i; // Read Address. This signal is the address of the first transfer in a burst.
    logic [7:0]                            s_axi_arlen_i; // Burst Length. Exact number of transfers in a burst.
    logic [2:0]                            s_axi_arsize_i;
    logic [1:0]                            s_axi_arburst_i;
    logic                                  s_axi_arvalid_i;
    logic                                  s_axi_rready_i;

    /* Output AXI4 FULL Signals */
    logic                                 s_axi_awready_o;
    logic                                 s_axi_wready_o;
    logic [1:0]                           s_axi_bresp_o;
    logic                                 s_axi_bvalid_o;
    logic                                 s_axi_arready_o;
    logic [AXI_DATA_WIDTH-1:0]             s_axi_rdata_o;
    logic                                 s_axi_rlast_o;
    logic [1:0]                           s_axi_rresp_o;
    logic                                 s_axi_rvalid_o;
       
    modport master (
        input   s_axi_aclk_i,
        input   s_axi_aresetn_i,
    
        /* Input AXI4 FULL Signals */
        output   s_axi_awaddr_i, // Write Address
        output   s_axi_awlen_i, // Burst Length. Exact number of transfers in a burst.
        output   s_axi_awsize_i, // Burst Size. Number of bytes in each transfer.
    

        output   s_axi_awburst_i, // Burst Type. Type of burst operation and size determine how the address is incremented.
        output   s_axi_awvalid_i, // Write Address Valid
        output   s_axi_wdata_i,// Write Data
        output   s_axi_wstrb_i, // Write Strobe. This signal indicates which byte lanes hold valid data.
        output   s_axi_wlast_i, // Write Last. This signal indicates the last transfer in a burst.
        output   s_axi_wvalid_i, // Write Valid. This signal indicates that the write data on the bus is valid.
        output   s_axi_bready_i, // Write Response Ready. This signal indicates that the master is ready to accept a write response.
        output   s_axi_araddr_i, // Read Address. This signal is the address of the first transfer in a burst.
        output   s_axi_arlen_i, // Burst Length. Exact number of transfers in a burst.
        output   s_axi_arsize_i,
        output   s_axi_arburst_i,
        output   s_axi_arvalid_i,
        output   s_axi_rready_i,
    
                
        input  s_axi_awready_o,
        input  s_axi_wready_o,
        input  s_axi_bresp_o,
        input  s_axi_bvalid_o,
        input  s_axi_arready_o,
        input  s_axi_rdata_o,
        input  s_axi_rlast_o,
        input  s_axi_rresp_o,
        input  s_axi_rvalid_o
    );    
    modport slave (
        input   s_axi_aclk_i,
        input   s_axi_aresetn_i,
    
        /* Input AXI4 FULL Signals */
        input   s_axi_awaddr_i, // Write Address
        input   s_axi_awlen_i, // Burst Length. Exact number of transfers in a burst.
        input   s_axi_awsize_i, // Burst Size. Number of bytes in each transfer.
    

        input   s_axi_awburst_i, // Burst Type. Type of burst operation and size determine how the address is incremented.
        input   s_axi_awvalid_i, // Write Address Valid
        input   s_axi_wdata_i,// Write Data
        input   s_axi_wstrb_i, // Write Strobe. This signal indicates which byte lanes hold valid data.
        input   s_axi_wlast_i, // Write Last. This signal indicates the last transfer in a burst.
        input   s_axi_wvalid_i, // Write Valid. This signal indicates that the write data on the bus is valid.
        input   s_axi_bready_i, // Write Response Ready. This signal indicates that the master is ready to accept a write response.
        input   s_axi_araddr_i, // Read Address. This signal is the address of the first transfer in a burst.
        input   s_axi_arlen_i, // Burst Length. Exact number of transfers in a burst.
        input   s_axi_arsize_i,
        input   s_axi_arburst_i,
        input   s_axi_arvalid_i,
        input   s_axi_rready_i,
    
                
        output  s_axi_awready_o,
        output  s_axi_wready_o,
        output  s_axi_bresp_o,
        output  s_axi_bvalid_o,
        output  s_axi_arready_o,
        output  s_axi_rdata_o,
        output  s_axi_rlast_o,
        output  s_axi_rresp_o,
        output  s_axi_rvalid_o
    ); 
endinterface