OutputMuxTb.v 1.3 KB

12345678910111213141516171819202122232425262728293031323334353637383940
  1. module OutputMux #(
  2. parameter AXI_DATA_WIDTH = 64,
  3. parameter SPI_NUM = 7,
  4. parameter FIFO_1_READ_ADDR = 64'h0000_0000_0000_1030,
  5. parameter FIFO_2_READ_ADDR = 64'h0000_0000_0000_2030,
  6. parameter FIFO_3_READ_ADDR = 64'h0000_0000_0000_3030,
  7. parameter FIFO_4_READ_ADDR = 64'h0000_0000_0000_4030,
  8. parameter FIFO_5_READ_ADDR = 64'h0000_0000_0000_5030,
  9. parameter FIFO_6_READ_ADDR = 64'h0000_0000_0000_6030,
  10. parameter FIFO_7_READ_ADDR = 64'h0000_0000_0000_7030
  11. )(
  12. input Clk_i,
  13. input RstN_i,
  14. input [AXI_DATA_WIDTH - 1 : 0] DataFromRxFifo_i [SPI_NUM - 1 : 0],
  15. input [AXI_DATA_WIDTH - 1 : 0] DataFromRegMap_i,
  16. input [AXI_DATA_WIDTH-1:0] Addr_i,
  17. output reg [AXI_DATA_WIDTH-1:0] AnsData_o
  18. );
  19. //================================================================================
  20. // CODING
  21. //================================================================================
  22. /* Multiplexing the data from the RxFifo and the RegMap */
  23. always_comb
  24. if (!RstN_i) begin
  25. AnsData_o = 0;
  26. end
  27. else begin
  28. AnsData_o = DataFromRegMap_i;
  29. for (int i = 0; i < SPI_NUM; i++) begin
  30. if (Addr_i == FIFO_1_READ_ADDR + i*1000) begin
  31. AnsData_o = DataFromRxFifo_i[i];
  32. end
  33. end
  34. end
  35. endmodule