EpSubsystem/SpiSubSystem/SpiSubSystem.v

//////////////////////////////////////////////////////////////////////////////////
// Company:			TAIR
// Engineer:		
// 
// Create Date:		10/30/2023 11:24:31 AM
// Design Name:
// Module Name:		SpiSubSystem
// Project Name:	S5443_V3_FPGA3
// Target Devices:	BOARD: BY5443v3. FPGA: xc7s25csga225-2
// Tool Versions:
// Description: 	This is wrapper that encapsulates FIFO's, Spi modules and 
//					modules that multiplex Spi output lines 
// 
// Dependencies: 
// 
// Revision:
// Revision 1.0 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module SpiSubSystem #(
	parameter STAGES = 3,
	parameter CMD_REG_WIDTH = 32,
	parameter ADDR_REG_WIDTH = 12,
	parameter WIDTH  = 1,
    parameter FIFO_NUM = 7,
    parameter ISTEMPRD = 1,
    parameter ISPOWERRST = 1
) 
(
	input Clk_i,
	input SpiClk_i,
	input Rst_i,
	input TxEn_i,

	input FifoRxRst_i,
	input FifoTxRst_i,
	input FifoRxRstRdPtr_i,
	input FifoTxRstWrPtr_i,

	input ToFifoVal_i,
	input ToRstMemVal_i,
	input [CMD_REG_WIDTH-1:0] ToFifoData_i,

	input [1:0] WidthSel_i,
	input PulsePol_i,
	input ClockPhase_i,
	input EndianSel_i,
	input Lag_i,
	input Lead_i,
	input SelSt_i,
	input [5:0] Stop_i,
	input Assel_i,

	input  [FIFO_NUM-1:0] ChipSelFpga_i,
	input  [FIFO_NUM-1:0] ChipSelFlash_i,

	input SpiMode_i,
	input SpiEn_i,

	output [CMD_REG_WIDTH-1:0] TxFifoCtrlReg_o,
	output [CMD_REG_WIDTH-1:0] RxFifoCtrlReg_o,
	output [CMD_REG_WIDTH-1:0] DataFromRxFifo_o,

	output Sck_o,
	output Ss_o,
	output SsFlash_o,
	output Mosi0_o,
	inout Mosi1_io,
	output Mosi2_o,
	output Mosi3_o,

	input  Ctrl_i,
	output [31:0] TempData_o
);

//================================================================================
//	REG/WIRE
//================================================================================
wire [CMD_REG_WIDTH-1:0] toSpiData;
wire [CMD_REG_WIDTH-1:0] toSpiDataR;
wire emptyFlagTx;

wire sckR;
wire ssR;
wire mosi0R;
wire valToTxR;
wire valToRxR;

wire sckQ;
wire ssQ;
wire mosi0Q;
wire valToTxQ;

wire valToTxFifoRead;
wire valToRxFifoWrite;
wire [CMD_REG_WIDTH-1:0] dataToRxFifo;

wire [31:0] tempData;
reg [31:0] tempDataReg;
wire [31:0] powRstData;
wire mosi1_o;
//================================================================================
//  ASSIGNMENTS
//================================================================================
assign valToTxFifoRead  = (SpiMode_i) ? valToTxQ : valToTxR;

assign Mosi1_io = (SpiMode_i) ? mosi1_o : 1'bz;

assign TempData_o = tempData;
//================================================================================
//	CODING
//================================================================================
InitRst InitRst_inst
(
	.clk_i		(SpiClk_i),
	.signal_o	(Rst_i)
);

Sync1bit #(
	.WIDTH		(1),
	.STAGES		(STAGES)
) Sync1bit_inst 
(
	.ClkFast_i	(Clk_i),
	.ClkSlow_i	(SpiClk_i),
	.TxEn_i		(TxEn_i),
	.TxEn_o		(spiTxEnSync)
);

DataFifoWrapper #(
	.CMD_REG_WIDTH		(CMD_REG_WIDTH),
	.ADDR_REG_WIDTH		(ADDR_REG_WIDTH),
	.STAGES				(STAGES),
	.FIFO_NUM			(FIFO_NUM)
) DataFifoWrapper
(
	.WrClk_i			(Clk_i),
	.RdClk_i			(SpiClk_i),

	.FifoRxRst_i		(FifoRxRst_i),
	.FifoTxRst_i		(FifoTxRst_i),
	.FifoRxRstRdPtr_i	(FifoRxRstRdPtr_i),
	.FifoTxRstWrPtr_i	(FifoTxRstWrPtr_i),

	.ToFifoVal_i		(ToFifoVal_i),
	.ToFifoRxData_i		(dataToRxFifo),
	.ToFifoRxWriteVal_i	(valToRxR),
	.ToFifoTxReadVal_i	(valToTxFifoRead),
	.ToFifoData_i		(ToFifoData_i),

	.TxFifoCtrlReg_o	(TxFifoCtrlReg_o),
	.RxFifoCtrlReg_o	(RxFifoCtrlReg_o),
	.EmptyFlagTx_o		(emptyFlagTx),
	.DataFromRxFifo_o	(DataFromRxFifo_o),
	.ToSpiData_o		(toSpiData)
);

//------------------------------------------------
//Generating needed amount of calculating channels
generate
	if (ISTEMPRD) begin : TempRdSpi


		SPIs TempRdSpi
		(
			.Clk_i			(SpiClk_i),
			.Rst_i			(Rst_i | SpiMode_i),
			.Sck_i			(sckR),
			.Ss_i			(ssR),
			.Mosi0_i		(Mosi1_io),
			.WidthSel_i		(WidthSel_i),
			.EndianSel_i	(EndianSel_i),
			.SelSt_i		(SelSt_i),
			.DataToRxFifo_o	(tempData),
			.Val_o			(tempVal)
		);

		always @(posedge Clk_i) begin
			if (Rst_i) begin
				tempDataReg <= 32'd0;
			end else begin
				if (tempVal) begin
					tempDataReg <= tempData;
				end
			end
		end
	end
endgenerate

generate
	if (ISPOWERRST) begin : PowRstMem

		PowRstMemWrapper PowRstMemWrapper(
   			.Clk_i(Clk_i),
   			.Rst_i(Rst_i),
	
   			.WrReq_i(ToRstMemVal_i),
   			.Data_i(ToFifoData_i),
	
   			.RdReq_i(),
   			.Data_o(powRstData),
   			.DataVal_o()
		);

		SpiDataMuxer SpiDataMuxer(
    		.Clk_i		(Clk_i),
    		.Rst_i		(Rst_i),
    		.Ctrl_i		(Ctrl_i),
		
    		.PowRstData_i		(powRstData),
    		.RegularData_i		(toSpiData),
	
    		.Data_o		(toSpiDataR)
		);

		SPIm SPIm (
			.Clk_i			(SpiClk_i),
			.Start_i		(spiTxEnSync),
			.Rst_i			(Rst_i | SpiMode_i | !SpiEn_i),
			.EmptyFlag_i	(emptyFlagTx),
			.SpiData_i		(toSpiDataR),
			.WidthSel_i		(WidthSel_i),
			.PulsePol_i		(PulsePol_i),
			.ClockPhase_i	(ClockPhase_i),
			.EndianSel_i	(EndianSel_i),
			.Lag_i			(Lag_i),
			.Lead_i			(Lead_i),
			.Stop_i			(Stop_i),
			.SelSt_i		(SelSt_i),
			.Sck_o			(sckR),
			.Ss_o			(ssR),
			.Mosi0_o		(mosi0R),
			.Val_o			(valToTxR)
		);

		SPIs SPIs (
			.Clk_i			(SpiClk_i),
			.Rst_i			(Rst_i | SpiMode_i),
			.Sck_i			(sckR),
			.Ss_i			(ssR),
			.Mosi0_i		(Mosi1_io),
			.WidthSel_i		(WidthSel_i),
			.EndianSel_i	(EndianSel_i),
			.SelSt_i		(SelSt_i),
			.DataToRxFifo_o	(dataToRxFifo),
			.Val_o			(valToRxR)
		);

		QuadSPIm QuadSPIm (
			.Clk_i			(SpiClk_i),
			.Start_i		(spiTxEnSync),
			.Rst_i			(Rst_i | !SpiMode_i | !SpiEn_i),
			.EmptyFlag_i	(emptyFlagTx),
			.SpiData_i		(toSpiDataR),
			.WidthSel_i		(WidthSel_i),
			.PulsePol_i		(PulsePol_i),
			.ClockPhase_i	(ClockPhase_i),
			.EndianSel_i	(EndianSel_i),
			.Lag_i			(Lag_i),
			.Lead_i			(Lead_i),
			.Stop_i			(Stop_i),
			.SelSt_i		(SelSt_i),
			.Sck_o			(sckQ),
			.Ss_o			(ssQ),
			.Mosi0_o		(mosi0Q),
			.Mosi1_o		(mosi1_o),
			.Mosi2_o		(Mosi2_o),
			.Mosi3_o		(Mosi3_o),
			.Val_o			(valToTxQ)
		);

		SpiLinesMuxer SpiLinesMuxer (
			.SsR_i			(ssR),
			.SsQ_i			(ssQ),
			.SckR_i			(sckR),
			.SckQ_i			(sckQ),
			.Mosi0R_i		(mosi0R),
			.Mosi0Q_i		(mosi0Q),
			.ChipSelFpga_i	(ChipSelFpga_i),
			.ChipSelFlash_i	(ChipSelFlash_i),
			.Assel_i		(Assel_i),
			.SpiMode_i		(SpiMode_i),
			.Ss_o			(Ss_o),
			.SsFlash_o		(SsFlash_o),
			.Sck_o			(Sck_o),
			.Mosi0_o		(Mosi0_o)
		);
	end else begin
		SPIm SPIm (
			.Clk_i			(SpiClk_i),
			.Start_i		(spiTxEnSync),
			.Rst_i			(Rst_i | SpiMode_i | !SpiEn_i),
			.EmptyFlag_i	(emptyFlagTx),
			.SpiData_i		(toSpiData),
			.WidthSel_i		(WidthSel_i),
			.PulsePol_i		(PulsePol_i),
			.ClockPhase_i	(ClockPhase_i),
			.EndianSel_i	(EndianSel_i),
			.Lag_i			(Lag_i),
			.Lead_i			(Lead_i),
			.Stop_i			(Stop_i),
			.SelSt_i		(SelSt_i),
			.Sck_o			(sckR),
			.Ss_o			(ssR),
			.Mosi0_o		(mosi0R),
			.Val_o			(valToTxR)
		);

		SPIs SPIs (
			.Clk_i			(SpiClk_i),
			.Rst_i			(Rst_i | SpiMode_i),
			.Sck_i			(sckR),
			.Ss_i			(ssR),
			.Mosi0_i		(Mosi1_io),
			.WidthSel_i		(WidthSel_i),
			.EndianSel_i	(EndianSel_i),
			.SelSt_i		(SelSt_i),
			.DataToRxFifo_o	(dataToRxFifo),
			.Val_o			(valToRxR)
		);

		QuadSPIm QuadSPIm (
			.Clk_i			(SpiClk_i),
			.Start_i		(spiTxEnSync),
			.Rst_i			(Rst_i | !SpiMode_i | !SpiEn_i),
			.EmptyFlag_i	(emptyFlagTx),
			.SpiData_i		(toSpiData),
			.WidthSel_i		(WidthSel_i),
			.PulsePol_i		(PulsePol_i),
			.ClockPhase_i	(ClockPhase_i),
			.EndianSel_i	(EndianSel_i),
			.Lag_i			(Lag_i),
			.Lead_i			(Lead_i),
			.Stop_i			(Stop_i),
			.SelSt_i		(SelSt_i),
			.Sck_o			(sckQ),
			.Ss_o			(ssQ),
			.Mosi0_o		(mosi0Q),
			.Mosi1_o		(mosi1_o),
			.Mosi2_o		(Mosi2_o),
			.Mosi3_o		(Mosi3_o),
			.Val_o			(valToTxQ)
		);

		SpiLinesMuxer SpiLinesMuxer (
			.SsR_i			(ssR),
			.SsQ_i			(ssQ),
			.SckR_i			(sckR),
			.SckQ_i			(sckQ),
			.Mosi0R_i		(mosi0R),
			.Mosi0Q_i		(mosi0Q),
			.ChipSelFpga_i	(ChipSelFpga_i),
			.ChipSelFlash_i	(ChipSelFlash_i),
			.Assel_i		(Assel_i),
			.SpiMode_i		(SpiMode_i),
			.Ss_o			(Ss_o),
			.SsFlash_o		(SsFlash_o),
			.Sck_o			(Sck_o),
			.Mosi0_o		(Mosi0_o)
		);
	end
endgenerate

endmodule