EpSubsystem/RegMap/RegMap.sv

module RegMap #(
    parameter AXI_DATA_WIDTH = 64,
    parameter [AXI_DATA_WIDTH-1:0] SPI_BASE_ADDR = 64'h1000,
    parameter [AXI_DATA_WIDTH-1:0] SPI6_BASE_ADDR = 64'h6000
)(
    input Clk_i,
    input RstN_i,

    input [AXI_DATA_WIDTH-1:0] WrData_i,
    input [AXI_DATA_WIDTH-1:0] WrAddr_i,
    input [AXI_DATA_WIDTH-1:0] RdAddr_i,
    input Val_i,

    output reg [AXI_DATA_WIDTH - 1 : 0] SpiCtrlReg_o, 
    output reg [AXI_DATA_WIDTH - 1 : 0] SpiClkReg_o,
    output reg [AXI_DATA_WIDTH - 1 : 0] SpiCsDelayReg_o,
    output reg [AXI_DATA_WIDTH - 1 : 0] SpiCsCtrlReg_o,
    output reg [AXI_DATA_WIDTH - 1 : 0] SpiTxRxFifoCtrlReg_o,

    output reg [AXI_DATA_WIDTH - 1 : 0 ] AnsDataReg_o

);

//================================================================================
//  LOCALPARAMS
//================================================================================
/* Spi 0 */

localparam  [AXI_DATA_WIDTH-1:0]  SPI_CTRL_ADDR = SPI_BASE_ADDR + 64'h0000;
localparam  [AXI_DATA_WIDTH-1:0]  SPI_CLK_ADDR = SPI_BASE_ADDR + 64'h0008;
localparam  [AXI_DATA_WIDTH-1:0]  SPI_CS_DELAY_ADDR = SPI_BASE_ADDR + 64'h0010;
localparam  [AXI_DATA_WIDTH-1:0]  SPI_CS_CTRL_ADDR = SPI_BASE_ADDR + 64'h0018;
localparam  [AXI_DATA_WIDTH-1:0]  SPI_TX_RX_FIFO_CTRL_ADDR = SPI_BASE_ADDR + 64'h0020;

//================================================================================
//                                  CODING
//================================================================================
always_ff @(posedge Clk_i) begin
    if (!RstN_i) begin
        SpiCtrlReg_o <= {AXI_DATA_WIDTH{1'b0}};
        SpiClkReg_o <= {AXI_DATA_WIDTH{1'b0}};
        SpiCsDelayReg_o <= {AXI_DATA_WIDTH{1'b0}};
        SpiCsCtrlReg_o <= {AXI_DATA_WIDTH{1'b0}};
        SpiTxRxFifoCtrlReg_o <= {AXI_DATA_WIDTH{1'b0}};
    end
    else begin
        if (Val_i) begin
            if (WrAddr_i == (SPI_CTRL_ADDR)) begin
                SpiCtrlReg_o <= WrData_i;
            end
            else if (WrAddr_i == (SPI_CLK_ADDR)) begin
                SpiClkReg_o <= WrData_i;
            end
            else if (WrAddr_i == (SPI_CS_DELAY_ADDR)) begin
                SpiCsDelayReg_o <= WrData_i;
            end
            else if (WrAddr_i == (SPI_CS_CTRL_ADDR)) begin
                SpiCsCtrlReg_o <= WrData_i;
            end
            else if (WrAddr_i == (SPI_TX_RX_FIFO_CTRL_ADDR)) begin
                SpiTxRxFifoCtrlReg_o <= WrData_i;
            end
        end
    end
end

always_comb begin 
    if (!RstN_i) begin 
        AnsDataReg_o = {AXI_DATA_WIDTH{1'b0}};
    end
    else begin 
        if (RdAddr_i == (SPI_CTRL_ADDR)) begin
            AnsDataReg_o = SpiCtrlReg_o;
        end
        else if (RdAddr_i == (SPI_CLK_ADDR)) begin
            AnsDataReg_o = SpiClkReg_o;
        end
        else if (RdAddr_i == (SPI_CS_DELAY_ADDR)) begin
            AnsDataReg_o = SpiCsDelayReg_o;
        end
        else if (RdAddr_i == (SPI_CS_CTRL_ADDR)) begin
            AnsDataReg_o = SpiCsCtrlReg_o;
        end
        else if (RdAddr_i == (SPI_TX_RX_FIFO_CTRL_ADDR)) begin
            AnsDataReg_o = SpiTxRxFifoCtrlReg_o;
        end
        else begin 
            AnsDataReg_o = {AXI_DATA_WIDTH{1'b0}};
        end
    end
end

endmodule