#ifndef NFM_BASE_MEMORY_H
#define NFM_BASE_MEMORY_H
    #include <stdint.h>
    #include <stddef.h>
    #include "app/nfm/nfm_base_ECalUnit.h"

    #define MEMORY_OFFSET_BLOCK_COMMON              (0)      // sEcalHeaderCRC_t    

    #define MEMORY_OFFSET_BLOCK_DATAHEADER_SC4000   (0x80)   // sEcalDataHeaderCRC_t
    #define MEMORY_OFFSET_BLOCK_DATAHEADER_SC6000   (0x80)   // sEcalDataHeaderCRC_t    
    #define MEMORY_OFFSET_BLOCK_DATAHEADER_SC8000   (0x80)   // sEcalDataHeaderCRC_t
    #define MEMORY_OFFSET_BLOCK_DATAHEADER_SC25XX   (0x80)   // sEcalDataHeaderCRC_t
    #define MEMORY_OFFSET_BLOCK_DATAHEADER_SC2543   (0x80)   // sEcalDataHeaderCRC_t
    #define MEMORY_OFFSET_BLOCK_DATAHEADER_SC84XX   (0x80)   // sEcalDataHeaderCRC_t
    #define MEMORY_OFFSET_BLOCK_DATAHEADER_SC45XX   (0x80)   // sEcalDataHeaderCRC_t    
    
    #define MEMORY_OFFSET_BLOCK_THERMHEADER_SC4000  (?THERM_COMP_ADDR_SC8000) // 08.02.2021 (������, ��������, ������ �������� ������, �� NFMBASE_FLASH_MAKEREALADDRESS)
    #define MEMORY_OFFSET_BLOCK_THERMHEADER_SC6000  (?THERM_COMP_ADDR_SC8000) // 08.02.2021 (������, ��������, ������ �������� ������, �� NFMBASE_FLASH_MAKEREALADDRESS)
    #define MEMORY_OFFSET_BLOCK_THERMHEADER_SC8000  (?THERM_COMP_ADDR_SC8000) // 08.02.2021 (������, ��������, ������ �������� ������, �� NFMBASE_FLASH_MAKEREALADDRESS)
    #define MEMORY_OFFSET_BLOCK_THERMHEADER_SC25XX  (?THERM_COMP_ADDR_SC8000) // 08.02.2021 (������, ��������, ������ �������� ������, �� NFMBASE_FLASH_MAKEREALADDRESS)
    #define MEMORY_OFFSET_BLOCK_THERMHEADER_SC2543  (THERM_COMP_ADDR_SC2543)  // ������������ ����� 0
    #define MEMORY_OFFSET_BLOCK_THERMHEADER_SC84XX  (?THERM_COMP_ADDR_SC8400) // 08.02.2021 (������, ��������, ������ �������� ������, �� NFMBASE_FLASH_MAKEREALADDRESS)
    #define MEMORY_OFFSET_BLOCK_THERMHEADER_SC45XX  (?THERM_COMP_ADDR_SC8400) // 08.02.2021 (������, ��������, ������ �������� ������, �� NFMBASE_FLASH_MAKEREALADDRESS)
    //-----------------------------------------  
    #define  MEMORY_OFFSET_BLOCK_USER1DATA_SC4000   ?1048576                 // 08.02.2021 (������, ��������, ������ �������� ������, �� NFMBASE_FLASH_MAKEREALADDRESS)
    #define  MEMORY_OFFSET_BLOCK_USER1DATA_SC6000   ?1048576                 // 08.02.2021 (������, ��������, ������ �������� ������, �� NFMBASE_FLASH_MAKEREALADDRESS)
    #define  MEMORY_OFFSET_BLOCK_USER1DATA_SC8000   ?1048576                 // 08.02.2021 (������, ��������, ������ �������� ������, �� NFMBASE_FLASH_MAKEREALADDRESS)
    #define  MEMORY_OFFSET_BLOCK_USER1DATA_SC25XX   ?1048576                 // 08.02.2021 (������, ��������, ������ �������� ������, �� NFMBASE_FLASH_MAKEREALADDRESS)
    #define  MEMORY_OFFSET_BLOCK_USER1DATA_SC2543   0                        // ������������ ����� 1
    #define  MEMORY_OFFSET_BLOCK_USER1DATA_SC84XX   ?2097152                 // 08.02.2021 (������, ��������, ������ �������� ������, �� NFMBASE_FLASH_MAKEREALADDRESS)
    #define  MEMORY_OFFSET_BLOCK_USER1DATA_SC45XX   ?2097152                 // 08.02.2021 (������, ��������, ������ �������� ������, �� NFMBASE_FLASH_MAKEREALADDRESS)
    //-----------------------------------------
    #define  MEMORY_OFFSET_BLOCK_USER2DATA_SC4000   ?1223338                 // 08.02.2021 (������, ��������, ������ �������� ������, �� NFMBASE_FLASH_MAKEREALADDRESS)
    #define  MEMORY_OFFSET_BLOCK_USER2DATA_SC6000   ?1223338                 // 08.02.2021 (������, ��������, ������ �������� ������, �� NFMBASE_FLASH_MAKEREALADDRESS)
    #define  MEMORY_OFFSET_BLOCK_USER2DATA_SC8000   ?1223338                 // 08.02.2021 (������, ��������, ������ �������� ������, �� NFMBASE_FLASH_MAKEREALADDRESS)
    #define  MEMORY_OFFSET_BLOCK_USER2DATA_SC25XX   ?1223338                 // 08.02.2021 (������, ��������, ������ �������� ������, �� NFMBASE_FLASH_MAKEREALADDRESS)
    #define  MEMORY_OFFSET_BLOCK_USER2DATA_SC2543   349524                   // ������������ ����� 1
    #define  MEMORY_OFFSET_BLOCK_USER2DATA_SC84XX   ?2708812                 // 08.02.2021 (������, ��������, ������ �������� ������, �� NFMBASE_FLASH_MAKEREALADDRESS)
    #define  MEMORY_OFFSET_BLOCK_USER2DATA_SC45XX   ?2708812                 // 08.02.2021 (������, ��������, ������ �������� ������, �� NFMBASE_FLASH_MAKEREALADDRESS)
    //-----------------------------------------
    #define  MEMORY_OFFSET_BLOCK_USER3DATA_SC4000   ?1398100                 // 08.02.2021 (������, ��������, ������ �������� ������, �� NFMBASE_FLASH_MAKEREALADDRESS)
    #define  MEMORY_OFFSET_BLOCK_USER3DATA_SC6000   ?1398100                 // 08.02.2021 (������, ��������, ������ �������� ������, �� NFMBASE_FLASH_MAKEREALADDRESS)
    #define  MEMORY_OFFSET_BLOCK_USER3DATA_SC8000   ?1398100                 // 08.02.2021 (������, ��������, ������ �������� ������, �� NFMBASE_FLASH_MAKEREALADDRESS)
    #define  MEMORY_OFFSET_BLOCK_USER3DATA_SC25XX   ?1398100                 // 08.02.2021 (������, ��������, ������ �������� ������, �� NFMBASE_FLASH_MAKEREALADDRESS)
    #define  MEMORY_OFFSET_BLOCK_USER3DATA_SC2543   699048                   // ������������ ����� 1
    #define  MEMORY_OFFSET_BLOCK_USER3DATA_SC84XX   ?3320472                 // 08.02.2021 (������, ��������, ������ �������� ������, �� NFMBASE_FLASH_MAKEREALADDRESS)
    #define  MEMORY_OFFSET_BLOCK_USER3DATA_SC45XX   ?3320472                 // 08.02.2021 (������, ��������, ������ �������� ������, �� NFMBASE_FLASH_MAKEREALADDRESS)
    //-----------------------------------------

    typedef struct
    {
        size_t BaseIndex_Short;   // Table index of the table for state SHORT of single port
        size_t BaseIndex_Open;    // Table index of the table for state OPEN  of single port
        size_t BaseIndex_Load;    // Table index of the table for state LOAD  of single port
        size_t BaseIndex_Load2;   // Table index of the table for state LOAD2 of single port
        size_t BaseIndex_Open2;   // Table index of the table for state OPEN2 of single port
    }
    sNFMMemory_TableMatrix_SinglePort_t;

    typedef struct
    {
        size_t aBaseIndex[5];     // The same as [sNFMMemory_TableMatrix_SinglePort_t], but as an array
    }
    sNFMMemory_TableMatrix_SinglePort_array_t;
    
    typedef struct
    {
        size_t BaseIndex_S11;     // Table index of the table for state S11 of pair ports (thru)        
        size_t BaseIndex_S21;     // Table index of the table for state S21 of pair ports (thru)
        size_t BaseIndex_S12;     // Table index of the table for state S12 of pair ports (thru)
        size_t BaseIndex_S22;     // Table index of the table for state S22 of pair ports (thru)
    }
    sNFMMemory_TableMatrix_ThruPort_t;
    
    typedef struct
    {
        size_t aBaseIndex[4];     // The same as [sNFMMemory_TableMatrix_ThruPort_t], but as an array
    }
    sNFMMemory_TableMatrix_ThruPort_array_t;
    
    typedef struct
    {
        size_t BaseIndex_S11;     // Table index of the table for state S11 of dual port (check state)
        size_t BaseIndex_S21;     // Table index of the table for state S21 of dual port (check state)
        size_t BaseIndex_S12;     // Table index of the table for state S12 of dual port (check state)
        size_t BaseIndex_S22;     // Table index of the table for state S22 of dual port (check state)
    }
    sNFMMemory_TableMatrix_CheckState_2Port_t;
    
    typedef struct
    {
        size_t aBaseIndex[4];     // The same as [sNFMMemory_TableMatrix_CheckState_2Port_t], but as an array
    }
    sNFMMemory_TableMatrix_CheckState_2Port_array_t;
    
    typedef struct
    {
        size_t BaseIndex_S11;     // Table index of the table for state S11 of quard port (check state)
        size_t BaseIndex_S21;     // Table index of the table for state S21 of quard port (check state)
        size_t BaseIndex_S31;     // Table index of the table for state S31 of quard port (check state)
        size_t BaseIndex_S41;     // Table index of the table for state S41 of quard port (check state)
        
        size_t BaseIndex_S12;     // Table index of the table for state S12 of quard port (check state)
        size_t BaseIndex_S22;     // Table index of the table for state S22 of quard port (check state)
        size_t BaseIndex_S32;     // Table index of the table for state S32 of quard port (check state)
        size_t BaseIndex_S42;     // Table index of the table for state S42 of quard port (check state)
        
        size_t BaseIndex_S13;     // Table index of the table for state S13 of quard port (check state)
        size_t BaseIndex_S23;     // Table index of the table for state S23 of quard port (check state)
        size_t BaseIndex_S33;     // Table index of the table for state S33 of quard port (check state)
        size_t BaseIndex_S43;     // Table index of the table for state S43 of quard port (check state)
        
        size_t BaseIndex_S14;     // Table index of the table for state S14 of quard port (check state)
        size_t BaseIndex_S24;     // Table index of the table for state S24 of quard port (check state)
        size_t BaseIndex_S34;     // Table index of the table for state S34 of quard port (check state)
        size_t BaseIndex_S44;     // Table index of the table for state S44 of quard port (check state)  
    }
    sNFMMemory_TableMatrix_CheckState_4Port_t;
    
    typedef struct
    {
        size_t aBaseIndex[16];    // The same as [sNFMMemory_TableMatrix_CheckState_4Port_t], but as an array
    }
    sNFMMemory_TableMatrix_CheckState_4Port_array_t;

    //--------------------------------------------------
    // uNFMMemory_PortMatrix_Single_2Port_t
    // Table profile for the table of all combinations of signle ports
    typedef union
    {
       struct
       {
       sNFMMemory_TableMatrix_SinglePort_t       sTable_A; // = .aArray[ ePortComb_A - ePortComb_A ]
       sNFMMemory_TableMatrix_SinglePort_t       sTable_B; // = .aArray[ ePortComb_B - ePortComb_A ]
       };
       
       sNFMMemory_TableMatrix_SinglePort_array_t aArray[2];
    }
    uNFMMemory_PortMatrix_Single_2Port_t;

    // uNFMMemory_PortMatrix_Single_4Port_t
    // Table profile for the table of all combinations of signle ports
    typedef union
    {
       struct
       {
       sNFMMemory_TableMatrix_SinglePort_t       sTable_A; // = .aArray[ ePortComb_A - ePortComb_A ]
       sNFMMemory_TableMatrix_SinglePort_t       sTable_B; // = .aArray[ ePortComb_B - ePortComb_A ]
       sNFMMemory_TableMatrix_SinglePort_t       sTable_C; // = .aArray[ ePortComb_C - ePortComb_A ]
       sNFMMemory_TableMatrix_SinglePort_t       sTable_D; // = .aArray[ ePortComb_D - ePortComb_A ]
       };
       
       sNFMMemory_TableMatrix_SinglePort_array_t aArray[4];
    }
    uNFMMemory_PortMatrix_Single_4Port_t;
    
    // uNFMMemory_PortMatrix_Thru_2Port_t
    // Table profile for tables of all combinations of pair ports (thrus)
    typedef union
    {
       struct
       {
       sNFMMemory_TableMatrix_ThruPort_t sTable_AB;  // = .aArrays[ ePortComb_AB - ePortComb_AB ]
       };
       sNFMMemory_TableMatrix_ThruPort_array_t aArrays[1];
    }
    uNFMMemory_PortMatrix_Thru_2Port_t;
    
    // uNFMMemory_PortMatrix_Thru_4Port_t
    // Table profile for tables of all combinations of pair ports (thrus)
    typedef union
    {
       struct
       {
       sNFMMemory_TableMatrix_ThruPort_t sTable_AB;  // = .aArrays[ ePortComb_AB - ePortComb_AB ]
       sNFMMemory_TableMatrix_ThruPort_t sTable_AC;  // = .aArrays[ ePortComb_AC - ePortComb_AB ]
       sNFMMemory_TableMatrix_ThruPort_t sTable_AD;  // = .aArrays[ ePortComb_AD - ePortComb_AB ]
       sNFMMemory_TableMatrix_ThruPort_t sTable_BC;  // = .aArrays[ ePortComb_BC - ePortComb_AB ]
       sNFMMemory_TableMatrix_ThruPort_t sTable_BD;  // = .aArrays[ ePortComb_BD - ePortComb_AB ]
       sNFMMemory_TableMatrix_ThruPort_t sTable_CD;  // = .aArrays[ ePortComb_CD - ePortComb_AB ]
       };
       sNFMMemory_TableMatrix_ThruPort_array_t aArrays[6];
    }
    uNFMMemory_PortMatrix_Thru_4Port_t;
    
    // sNFMMemory_PortMatrix_Check_2Port_t
    // Table profile for the table of all states of quard port (check state)
    typedef union
    {
       sNFMMemory_TableMatrix_CheckState_2Port_t       sTables;
       sNFMMemory_TableMatrix_CheckState_2Port_array_t sArray;
    }
    sNFMMemory_PortMatrix_Check_2Port_t;
    
    // sNFMMemory_PortMatrix_Check_4Port_t
    // Table profile for the table of all states of quard port (check state)
    typedef union
    {
       sNFMMemory_TableMatrix_CheckState_4Port_t       sTables;
       sNFMMemory_TableMatrix_CheckState_4Port_array_t sArray;
    }
    sNFMMemory_PortMatrix_Check_4Port_t;
    
    typedef enum
    {
       eNfmChrzTable1Port, // not implemented (NFM_ROM_GetChrzTableIndex)
       eNfmChrzTable2Port,
       eNfmChrzTable4Port,
       eNfmChrzTable8Port, // not implemented (NFM_ROM_GetChrzTableIndex)
    }
    eNFMMemory_ChrzTableType_t;
    
    typedef struct
    {
       union
       {
          eNFMMemory_ChrzTableType_t eType;
          size_t                     nType;
       }
       ChrzTableType;
       size_t                        maxTableIdx;
    }
    sNFMMemory_ChrzTableIdHeader_t;

    #define DECLARE_CHRZTABLETYPE_1PORT(MAX_TABLES)  .Header = { .ChrzTableType.eType = eNfmChrzTable1Port, .maxTableIdx = (MAX_TABLES) }
    #define DECLARE_CHRZTABLETYPE_2PORT(MAX_TABLES)  .Header = { .ChrzTableType.eType = eNfmChrzTable2Port, .maxTableIdx = (MAX_TABLES) }
    #define DECLARE_CHRZTABLETYPE_4PORT(MAX_TABLES)  .Header = { .ChrzTableType.eType = eNfmChrzTable4Port, .maxTableIdx = (MAX_TABLES) }
    #define DECLARE_CHRZTABLETYPE_8PORT(MAX_TABLES)  .Header = { .ChrzTableType.eType = eNfmChrzTable8Port, .maxTableIdx = (MAX_TABLES) }
    
    // sNFMMemory_ChrzTableMatrix_Undefined_t:
    // Characterization table structure for any NFM
    // Contains only common header
    typedef struct
    {
       sNFMMemory_ChrzTableIdHeader_t         Header;  // Characterization table common information
    }
    sNFMMemory_ChrzTableMatrix_XPort_t;
    
    // sNFMMemory_ChrzTableMatrix_2Port_t:
    // Characterization table profile for 2-port NFM
    // Contains indicies for all the tables of all combinations of ports and states.
    typedef struct
    {
       sNFMMemory_ChrzTableIdHeader_t         Header;  // Characterization table common information
       uNFMMemory_PortMatrix_Single_2Port_t   Single;  // Index-Table for states of sigle ports
       uNFMMemory_PortMatrix_Thru_2Port_t     Thru;    // Index-Table for states of pairs ports (thrus)
       sNFMMemory_PortMatrix_Check_2Port_t    Check;   // Index-Table for states of quard port (check state)
    }
    sNFMMemory_ChrzTableMatrix_2Port_t;

    // sNFMMemory_ChrzTableMatrix_4Port_t:
    // Characterization table profile for 4-port NFM
    // Contains indicies for all the tables of all combinations of ports and states.
    typedef struct
    {
       sNFMMemory_ChrzTableIdHeader_t         Header;  // Characterization table common information
       uNFMMemory_PortMatrix_Single_4Port_t   Single;  // Index-Table for states of sigle ports
       uNFMMemory_PortMatrix_Thru_4Port_t     Thru;    // Index-Table for states of pairs ports (thrus)
       sNFMMemory_PortMatrix_Check_4Port_t    Check;   // Index-Table for states of quard port (check state)
    }
    sNFMMemory_ChrzTableMatrix_4Port_t;
    
    typedef struct
    {
        size_t BaseAddr_TComp;           // Factory Termocompensation Table Base Address
        size_t BaseAddr_Chrz[eCh_MAX];   // [0] = Factory Characterization Base Address (Header)
                                         // [1..3] = User's Characterization Base Addresses
        size_t BaseAddr_Settings;        // Device Settings block address
        size_t Size_Settings;            // Device Settings block size
        
        union
        {
        const void * tbls_raw;
        const sNFMMemory_ChrzTableMatrix_2Port_t * tbls_2Port;
        const sNFMMemory_ChrzTableMatrix_4Port_t * tbls_4Port;
        /* Do not forget to update 'NFM_ROM_GetChrzTableIndex' routine */
        };
    }
    sNFMMemoryProfile_t;
    
    typedef struct
    {
        size_t BaseAddr_SwTable;              // Switch table Base Header Address
        size_t BaseAddr_Table[eChValues_MAX]; // Switch table start chunks (data) address
        size_t BaseAddr_Settings;             // Device Settings block address
        size_t Size_Settings;                 // Device Settings block size
    }sSwitchMemoryProfile_t;
    
    #define NFM_CHRZ_TABLEIDX_INVALID         (0)
    #define NFM_CHRZ_TABLEIDX_2_OFFSET(IDX)   ((IDX)-1)
    
    #define NFM_TCOMP_MAGN_TABLEIDX_2_OFFSET(IDX)   ( ((IDX)-1)*2 + 0 )
    #define NFM_TCOMP_PHASE_TABLEIDX_2_OFFSET(IDX)  ( ((IDX)-1)*2 + 1 )

    #define SIZE_CHRZ_HEADER                  sizeof( sEcalDataHeaderCRC_t     )       // size of characterization main header
    #define SIZE_TCOMP_HEADER                 sizeof( sEcalTCompHeaderCRC_t    )       // size of thermocompensation main header
    #define SIZE_CHRZ_THDR                    sizeof( sEcalChrzTableHeader_t   )       // size of characterization table header
    #define SIZE_CHRZ_TPNT                    sizeof( sEcalChrzTablePoint_t    )       // size of characterization table point 
    
    #define SIZE_TCOMP_MAGN_THDR              sizeof( sEcalTCompTableMagnHeader_t  )   // size of thermocompensation table magnitude header
    #define SIZE_TCOMP_PHASE_THDR             sizeof( sEcalTCompTablePhaseHeader_t  )  // size of thermocompensation table phase header
    
    #define SIZE_TCOMP_MAGN_TPNT              sizeof( sEcalTCompTableMagnPoint_t  )    // size of thermocompensation table magnitude point    
    #define SIZE_TCOMP_PHASE_TPNT             sizeof( sEcalTCompTablePhasePoint_t )    // size of thermocompensation table phase point    
    
    #define SIZE_CHRZ_TCRC                    (sizeof(uint32_t))
    #define SIZE_TCOMP_TCRC                   (sizeof(uint32_t))
    #define SIZE_CHRZ_TABLE(NPOINTS)          ((SIZE_CHRZ_TCRC) + (SIZE_CHRZ_THDR) + (NPOINTS)*(SIZE_CHRZ_TPNT))   // size of characterization table
    
    #define SIZE_TCOMP_MAGN_TABLE(NPOINTS)    ((SIZE_TCOMP_TCRC) + (SIZE_TCOMP_MAGN_THDR)  + (NPOINTS)*(SIZE_TCOMP_MAGN_TPNT) ) // size of thermocompensation magnitude table    
    #define SIZE_TCOMP_PHASE_TABLE(NPOINTS)   ((SIZE_TCOMP_TCRC) + (SIZE_TCOMP_PHASE_THDR) + (NPOINTS)*(SIZE_TCOMP_PHASE_TPNT)) // size of thermocompensation phase table
    
    extern const sNFMMemoryProfile_t memProfile_SC2543v1_ADRF_NFM2543_v1;
    extern const sNFMMemoryProfile_t memProfile_NFM;
    
    extern const sSwitchMemoryProfile_t memProfile_SW; // Switch mem profile
    
    bool NFM_ROM_GetMemoryProtectStatus_Bank0();
    bool NFM_ROM_SetMemoryProtectStatus_Bank0( bool desiredStatus );
    
    size_t NFM_ROM_GetChrzTableIndex( ePortComb_t portCombination, ePortStateId_t portState );
    size_t NFM_ROM_GetTCompTableIndex( ePortComb_t portCombination, ePortStateId_t portState );
    
    const sEcalHeader_t * NFM_ROM_GetCommonHeader( uint8_t * buffer, size_t size );
    const sEcalDataHeader_t * NFM_ROM_GetDataHeader( eChrz_t tableId, uint8_t * buffer, size_t size );
    const sEcalTCompHeader_t * NFM_ROM_GetTCompHeader( uint8_t * buffer, size_t size );
    
    //const sTableHeader_t * SW_ROM_GetCommonHeader( uint8_t * buffer, size_t size );
    
    size_t NFM_ROM_ReadChrzTableHeader(   eChrz_t sectorId,
                                      ePortComb_t portCombination, 
                                      ePortStateId_t portState,
                                      size_t nPoints,   // @nPoints = amount of points in the table
                                      sEcalChrzTableHeader_t * pHeader,
                                      unsigned int * pErrCode
                                      );
    
    size_t NFM_ROM_ReadChrzTablePoints( /*const*/ sNFMGetPoints_t * pContext );
    
    size_t NFM_ROM_GetTCompMagnTableHeader( ePortComb_t portCombination,
                                            ePortStateId_t portState,
                                            size_t nPoints,
                                            sEcalTCompTableMagnHeader_t * pHeader,
                                            unsigned int * pErrCode
                                          );
                      
    size_t NFM_ROM_GetTCompPhaseTableHeader( ePortComb_t portCombination,
                                             ePortStateId_t portState,
                                             size_t nPoints,
                                             sEcalTCompTablePhaseHeader_t * pHeader,
                                             unsigned int * pErrCode
                                           );
                      
    size_t NFM_ROM_GetTCompMagnPoints( /*const*/ sNFMGetPoints_t * pContext );
    size_t NFM_ROM_GetTCompPhasePoints( /*const*/ sNFMGetPoints_t * pContext );

    size_t NFM_ROM_WriteDeviceSettings( uint8_t * buffer, size_t nOffset, size_t nBytesToWrite );
    size_t NFM_ROM_ReadDeviceSettings( uint8_t * buffer, size_t nOffset, size_t nBytesToRead );
    size_t NFM_ROM_GetDeviceSettingsSize();
    bool   NFM_ROM_ValidateUserSettings();
    
    sTableHeaderCRC_t * SW_ROM_GetTableHeader();
    bool SW_ROM_SetDataPoint ( eChunks_t tableId, sTableTablePoint_t * TablePoint );
    bool SW_ROM_Check_Table_crc();
    uint16_t SW_ROM_GetNumberOfPoints();
    const bool SW_ROM_GetDataPoint( eChunks_t tableId, uint8_t point_number, uint8_t * buffer, size_t size );
    bool SW_ROM_Table_Clear();

    
#endif
