stm32l1xx_hal_spi_ex.c 6.0 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32l1xx_hal_spi_ex.c
  4. * @author MCD Application Team
  5. * @brief Extended SPI HAL module driver.
  6. * This file provides firmware functions to manage the following
  7. * SPI peripheral extended functionalities :
  8. * + IO operation functions
  9. *
  10. ******************************************************************************
  11. * @attention
  12. *
  13. * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  14. *
  15. * Redistribution and use in source and binary forms, with or without modification,
  16. * are permitted provided that the following conditions are met:
  17. * 1. Redistributions of source code must retain the above copyright notice,
  18. * this list of conditions and the following disclaimer.
  19. * 2. Redistributions in binary form must reproduce the above copyright notice,
  20. * this list of conditions and the following disclaimer in the documentation
  21. * and/or other materials provided with the distribution.
  22. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  23. * may be used to endorse or promote products derived from this software
  24. * without specific prior written permission.
  25. *
  26. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  27. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  29. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  30. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  32. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  33. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  34. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36. *
  37. ******************************************************************************
  38. */
  39. /* Includes ------------------------------------------------------------------*/
  40. #include "stm32l1xx_hal.h"
  41. /** @addtogroup STM32L1xx_HAL_Driver
  42. * @{
  43. */
  44. /** @addtogroup SPI
  45. * @{
  46. */
  47. #ifdef HAL_SPI_MODULE_ENABLED
  48. /* Private typedef -----------------------------------------------------------*/
  49. /* Private defines -----------------------------------------------------------*/
  50. /* Private macros ------------------------------------------------------------*/
  51. /* Private variables ---------------------------------------------------------*/
  52. /* Private function prototypes -----------------------------------------------*/
  53. /* Exported functions --------------------------------------------------------*/
  54. /** @addtogroup SPI_Exported_Functions
  55. * @{
  56. */
  57. /** @addtogroup SPI_Exported_Functions_Group1
  58. *
  59. * @{
  60. */
  61. /**
  62. * @brief Initializes the SPI according to the specified parameters
  63. * in the SPI_InitTypeDef and create the associated handle.
  64. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
  65. * the configuration information for SPI module.
  66. * @retval HAL status
  67. */
  68. HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
  69. {
  70. /* Check the SPI handle allocation */
  71. if (hspi == NULL)
  72. {
  73. return HAL_ERROR;
  74. }
  75. /* Check the parameters */
  76. assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
  77. assert_param(IS_SPI_MODE(hspi->Init.Mode));
  78. assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction));
  79. assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
  80. assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
  81. assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
  82. assert_param(IS_SPI_NSS(hspi->Init.NSS));
  83. assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
  84. assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
  85. assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
  86. assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
  87. assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
  88. if (hspi->State == HAL_SPI_STATE_RESET)
  89. {
  90. /* Allocate lock resource and initialize it */
  91. hspi->Lock = HAL_UNLOCKED;
  92. /* Init the low level hardware : GPIO, CLOCK, NVIC... */
  93. HAL_SPI_MspInit(hspi);
  94. }
  95. hspi->State = HAL_SPI_STATE_BUSY;
  96. /* Disble the selected SPI peripheral */
  97. __HAL_SPI_DISABLE(hspi);
  98. /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
  99. /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
  100. Communication speed, First bit and CRC calculation state */
  101. hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
  102. hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
  103. hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation);
  104. /* Configure : NSS management */
  105. hspi->Instance->CR2 = (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode);
  106. /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
  107. /* Configure : CRC Polynomial */
  108. hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
  109. #if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
  110. /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
  111. CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
  112. #endif
  113. hspi->ErrorCode = HAL_SPI_ERROR_NONE;
  114. hspi->State = HAL_SPI_STATE_READY;
  115. return HAL_OK;
  116. }
  117. /**
  118. * @}
  119. */
  120. /**
  121. * @}
  122. */
  123. #endif /* HAL_SPI_MODULE_ENABLED */
  124. /**
  125. * @}
  126. */
  127. /**
  128. * @}
  129. */
  130. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/