Добавляется обработка данных приходящих по pcie

src/PciE/PIO.v

@@ -98,10 +98,11 @@ module PIO #(
 
   input [15:0]                  cfg_completer_id,
 
-  input   [32*9-1:0] MeasData_i,
-  input   MeasEnd_i,
-
-  output  StartMeasCmd_o
+  input   [31:0] Data_i,
+  output  [31:0] Cmd_o,
+  output  [7:0] Addr_o,
+  output  ReadReq_o,
+  output  WrReq_o
 
 ); // synthesis syn_hier = "hard"
 
@@ -152,10 +153,11 @@ module PIO #(
 
     .cfg_completer_id ( cfg_completer_id ),        // I [15:0]
 
-    .MeasData_i(MeasData_i),
-    .MeasEnd_i(MeasEnd_i),
-
-    .StartMeasCmd_o(StartMeasCmd_o)
+    .Data_i (Data_i),
+    .Cmd_o  (Cmd_o),
+    .Addr_o (Addr_o),
+    .ReadReq_o  (ReadReq_o),
+    .WrReq_o  (WrReq_o)
   );
 
 

src/PciE/PIO_EP.v

@@ -92,10 +92,11 @@ module PIO_EP #(
 
   input   [15:0]                cfg_completer_id,
 
-  input   [32*9-1:0] MeasData_i,
-  input   MeasEnd_i,
-
-  output  StartMeasCmd_o
+  input   [31:0] Data_i,
+  output  [31:0] Cmd_o,
+  output  [7:0] Addr_o,
+  output  ReadReq_o,
+  output  WrReq_o
 );
 
     // Local wires
@@ -123,9 +124,6 @@ module PIO_EP #(
     wire  [7:0]       req_tag;
     wire  [7:0]       req_be;
     wire  [12:0]      req_addr;
-    
-    wire valToCfgReg;
-    wire valToMeasData;
 
     //
     // ENDPOINT MEMORY : 8KB memory aperture implemented in FPGA BlockRAM(*)
@@ -195,32 +193,29 @@ module PIO_EP #(
     .wr_be(wr_be),
     .wr_data_msb(wr_data),                  // O [31:0]
     .wr_en(wr_en),                          // O
-    .wr_busy(wr_busy),                       // I
-    
-    .ValToCfgReg_o    (valToCfgReg),                                   
-    .ValToMeasData_o  (valToMeasData)                                   
+    .wr_busy(wr_busy)                      // I                                 
   );
 
 
-  IntermediateLogic IntermediateLogic 
-  (
-  .Clk100_i(clk),
-  .Clk50_i(clk_50),
-  .Rst_i(~rst_n),
+  // IntermediateLogic IntermediateLogic 
+  // (
+  // .Clk100_i(clk),
+  // .Clk50_i(clk_50),
+  // .Rst_i(~rst_n),
 
-  .MeasEnd_i(MeasEnd_i),
+  // .MeasEnd_i(MeasEnd_i),
 
-  .ReadReq_i(req_compl_int),
+  // .ReadReq_i(req_compl_int),
 
-  .ValToCfgReg_i(valToCfgReg),
-  .CfgData_i(wr_data),
+  // .ValToCfgReg_i(valToCfgReg),
+  // .CfgData_i(wr_data),
  
-  .ValToMeasData_i(valToMeasData),
-  .MeasData_i(MeasData_i),
+  // .ValToMeasData_i(valToMeasData),
+  // .MeasData_i(MeasData_i),
   
-  .StartMeasCmd_o(StartMeasCmd_o),
-  .Data_o(rd_data)
-  );
+  // .StartMeasCmd_o(StartMeasCmd_o),
+  // .Data_o(rd_data)
+  // );
 
     //
     // Local-Link Transmit Controller
@@ -260,9 +255,9 @@ module PIO_EP #(
 
     // Read Port
 
-    .rd_addr(rd_addr),                        // O [10:0]
-    .rd_be(rd_be),                            // O [3:0]
-    .rd_data(rd_data),                        // I [31:0]
+    .rd_addr(),                        // O [10:0]
+    .rd_be(),                            // O [3:0]
+    .rd_data(Data_i),                        // I [31:0]
 
     .completer_id(cfg_completer_id)           // I [15:0]
 
@@ -270,6 +265,10 @@ module PIO_EP #(
 
   assign req_compl  = req_compl_int;
   assign compl_done = compl_done_int;
+  assign Cmd_o = wr_data;
+  assign Addr_o = wr_addr[10:2];
+  assign ReadReq_o = req_compl_int;
+  assign WrReq_o = wr_en;
 
 endmodule // PIO_EP
 

src/PciE/PIO_RX_ENGINE.v

@@ -112,10 +112,7 @@ module PIO_RX_ENGINE  #(
   output reg [7:0]   wr_be,                         // Memory Write Byte Enable
   output reg [31:0]  wr_data,                       // Memory Write Data
   output reg         wr_en,                         // Memory Write Enable
-  input              wr_busy,                        // Memory Write Busy
-
-  output reg ValToCfgReg_o,
-  output reg ValToMeasData_o
+  input              wr_busy                        // Memory Write Busy
 );
 
  assign wr_data_msb[7:0] = wr_data[31:24];
@@ -202,9 +199,6 @@ module PIO_RX_ENGINE  #(
           state        <= #TCQ PIO_RX_RST_STATE;
           tlp_type     <= #TCQ 8'b0;
 
-          ValToCfgReg_o <= 0;
-          ValToMeasData_o <= 0;
-
         end
         else
         begin
@@ -407,14 +401,6 @@ module PIO_RX_ENGINE  #(
               if (m_axis_rx_tvalid)
               begin
 
-                if (m_axis_rx_tdata[10:2] == 8'h2) begin
-                  ValToMeasData_o <= 1;
-                end
-                else if (m_axis_rx_tdata[10:2] == 8'h01) begin
-                  ValToCfgReg_o <= 1;
-                end
-
-
                 m_axis_rx_tready <= #TCQ 1'b0;
                 req_addr     <= #TCQ {region_select[1:0],m_axis_rx_tdata[10:2], 2'b00};
                 req_compl    <= #TCQ 1'b1;
@@ -432,11 +418,8 @@ module PIO_RX_ENGINE  #(
 
               if (m_axis_rx_tvalid)
               begin
-                if (m_axis_rx_tdata[10:2] == 8'h01) begin
-                  ValToCfgReg_o <= 1;
-                end else begin
-                  wr_en <= #TCQ 1'b1;
-                end 
+               
+                wr_en <= #TCQ 1'b1;
 
                 wr_data      <= #TCQ m_axis_rx_tdata[63:32];
                 
@@ -522,8 +505,6 @@ module PIO_RX_ENGINE  #(
 
             PIO_RX_WAIT_STATE : begin
 
-              ValToCfgReg_o <= 0;
-              ValToMeasData_o <= 0;
               wr_en      <= #TCQ 1'b0;
               req_compl  <= #TCQ 1'b0;
 

src/PciE/pci_exp_usrapp_tx.v

@@ -429,7 +429,7 @@ end
         $display("[%t] : SYSTEM CHECK PASSED", $realtime);
    end else begin
         $display("[%t] : SYSTEM CHECK FAILED", $realtime);
-        $finish;
+ //       $finish;
    end
 
   end

src/PciE/pcie_app_7x.v

@@ -146,10 +146,11 @@ module  pcie_app_7x#(
   output                        cfg_interrupt_stat,
   output  [4:0]                 cfg_pciecap_interrupt_msgnum,
 
-  input   [32*9-1:0] MeasData_i,
-  input   MeasEnd_i,
-
-  output  StartMeasCmd_o
+  input   [31:0] Data_i,
+  output  [31:0] Cmd_o,
+  output  [7:0] Addr_o,
+  output  ReadReq_o,
+  output  WrReq_o
 );
   //----------------------------------------------------------------------------------------------------------------//
   // PCIe Block EP Tieoffs - Example PIO doesn't support the following inputs                                       //
@@ -256,11 +257,13 @@ module  pcie_app_7x#(
     .m_axis_rx_tvalid( m_axis_rx_tvalid ),          // I
     .m_axis_rx_tready( m_axis_rx_tready ),          // O
     .m_axis_rx_tuser ( m_axis_rx_tuser ),            // I
+    
+    .Data_i(Data_i),
+    .Cmd_o(Cmd_o),
+    .Addr_o(Addr_o),
+    .ReadReq_o(ReadReq_o),
+    .WrReq_o(WrReq_o)
 
-    .MeasData_i(MeasData_i),
-    .MeasEnd_i(MeasEnd_i),
-
-    .StartMeasCmd_o(StartMeasCmd_o)
   );
 
 endmodule // pcie_app

src/PciE/xilinx_pcie_2_1_ep_7x.v

@@ -80,10 +80,11 @@ module xilinx_pcie_2_1_ep_7x # (
 
   output Clk_o,
 
-  input   [32*9-1:0] MeasData_i,
-  input   MeasEnd_i,
-
-  output  StartMeasCmd_o,
+  input   [31:0] Data_i,
+  output  [31:0] Cmd_o,
+  output  [7:0] Addr_o,
+  output  ReadReq_o,
+  output  WrReq_o,
 
   output  ClkUser3_o
 );
@@ -584,10 +585,11 @@ pcie_app_7x  #(
   .cfg_interrupt_stat             ( cfg_interrupt_stat ),
   .cfg_pciecap_interrupt_msgnum   ( cfg_pciecap_interrupt_msgnum ),
 
-  .MeasData_i(MeasData_i),
-  .MeasEnd_i(MeasEnd_i),
-
-  .StartMeasCmd_o(StartMeasCmd_o)
+  .Data_i (Data_i),
+  .Cmd_o  (Cmd_o),
+  .Addr_o (Addr_o),
+  .ReadReq_o  (ReadReq_o),
+  .WrReq_o  (WrReq_o)
 );
 
 endmodule

src/Sim/S5443TopSimpleMeasTb.v

@@ -36,47 +36,47 @@ module S5443TopSimpleMeasTb;
 	localparam	[31:0]	THIRD	=	{4'b0,14'h1fff,14'h1fff};
 	localparam	[31:0]	FOURTH	=	{4'b0,14'h2000,14'h1fff};
 	
-	localparam	[3:0]	EP1MUXCMD	=	4'd1;
-	localparam	[3:0]	EP2MUXCMD	=	4'd1;
-	localparam	[3:0]	EP3MUXCMD	=	4'd1;
-	localparam	[3:0]	EP4MUXCMD	=	4'd1;
-	localparam	[3:0]	EP5MUXCMD	=	4'd1;
-	localparam	[3:0]	EP6MUXCMD	=	4'd1;
-	
-	localparam	[3:0]	PG1MUXCMD	=	4'd13;
-	localparam	[3:0]	PG2MUXCMD	=	4'd0;
-	localparam	[3:0]	PG3MUXCMD	=	4'd0;
-	localparam	[3:0]	PG4MUXCMD	=	4'd0;
-	localparam	[3:0]	PG5MUXCMD	=	4'd0;
-	localparam	[3:0]	PG6MUXCMD	=	4'd0;
-	localparam	[3:0]	PG7MUXCMD	=	4'd0;
+	localparam	[4:0]	EP1MUXCMD	=	5'd14;
+	localparam	[4:0]	EP2MUXCMD	=	5'd1;
+	localparam	[4:0]	EP3MUXCMD	=	5'd1;
+	localparam	[4:0]	EP4MUXCMD	=	5'd1;
+	localparam	[4:0]	EP5MUXCMD	=	5'd1;
+	localparam	[4:0]	EP6MUXCMD	=	5'd1;
+	
+	localparam	[4:0]	PG1MUXCMD	=	5'd13;
+	localparam	[4:0]	PG2MUXCMD	=	5'd0;
+	localparam	[4:0]	PG3MUXCMD	=	5'd0;
+	localparam	[4:0]	PG4MUXCMD	=	5'd0;
+	localparam	[4:0]	PG5MUXCMD	=	5'd0;
+	localparam	[4:0]	PG6MUXCMD	=	5'd0;
+	localparam	[4:0]	PG7MUXCMD	=	5'd0;
 	
 	localparam	[2:0]	PG1MODE	=	3'd1;
 	localparam	[2:0]	PG2MODE	=	3'd1;
-	localparam	[2:0]	PG3MODE	=	3'd1;
+	localparam	[2:0]	PG3MODE	=	3'd0;
 	localparam	[2:0]	PG4MODE	=	3'd1;
-	localparam	[2:0]	PG5MODE	=	3'd0;
-	localparam	[2:0]	PG6MODE	=	3'd0;
-	localparam	[2:0]	PG7MODE	=	3'd0;
+	localparam	[2:0]	PG5MODE	=	3'd1;
+	localparam	[2:0]	PG6MODE	=	3'd1;
+	localparam	[2:0]	PG7MODE	=	3'd1;
 	
 	localparam	PG1POL	=	1'b0;
-	localparam	PG2POL	=	1'b1;
+	localparam	PG2POL	=	1'b0;
 	localparam	PG3POL	=	1'b1;
 	localparam	PG4POL	=	1'b0;
 	localparam	PG5POL	=	1'b0;
 	localparam	PG6POL	=	1'b0;
 	localparam	PG7POL	=	1'b0;
-	
-	localparam	[3:0]	EXTTRIGMUXCMD	=	4'd15;
-	localparam	[3:0]	MODMUXCMD		=	4'd1;
-	localparam	[3:0]	GATINGMUXCMD	=	4'd2;
-	localparam	[3:0]	SMPLSTRBMUXCMD	=	4'd3;
-	localparam	[3:0]	DTIMUXCMD		=	4'd7;
+
+	localparam	[4:0]	EXTTRIGMUXCMD	=	5'd15;
+	localparam	[4:0]	DSPTRIGINCMD	=	5'h8;
+	localparam	[4:0]	MUXSLOWMODCMD	=	5'd1;
+	localparam	[4:0]	MUXFASTMODCMD	=	5'd1;
+	localparam	[4:0]	GATINGMUXCMD	=	5'd2;
+	localparam	[4:0]	SMPLSTRBMUXCMD	=	5'd3;
 	
 	//COMMANDS	FOR REG_MAP
 	parameter	[31:0]	MeasCmd =	{8'h11,8'h1,8'h71,8'h0};
 	parameter	[31:0]	SensCtrlCmd =	{31'h0,1'b0};
-	// parameter	[31:0]	MeasCmd =	{8'h11,8'h0,8'h64,8'h0};
 	parameter	[31:0]	AdcCtrl =	{8'h12,24'h2};
 	parameter	[31:0]	IfFtwH 	=	{8'h15,16'h0,8'h38};
 	parameter	[31:0]	IfFtwL 	=	{8'h16,24'h51eb85};
@@ -160,10 +160,10 @@ module S5443TopSimpleMeasTb;
 	parameter	[31:0]	PGMode0RegCmd		=	{8'h0b,3'b0,PG7MODE,PG6MODE,PG5MODE,PG4MODE,PG3MODE,PG2MODE,PG1MODE};
 	parameter	[31:0]	PGMode1RegCmd		=	{8'h1b,7'b0000000,PG7POL,PG6POL,PG5POL,PG4POL,PG3POL,PG2POL,PG1POL,10'b0};
 	
-	parameter	[31:0]	MuxCtrl1RegCmd	=	{8'h1c,4'h0,PG7MUXCMD,PG6MUXCMD,PG5MUXCMD,PG4MUXCMD};
-	parameter	[31:0]	MuxCtrl2RegCmd	=	{8'h1d,4'h0,PG3MUXCMD,PG2MUXCMD,PG1MUXCMD,SMPLSTRBMUXCMD};
-	parameter	[31:0]	MuxCtrl3RegCmd	=	{8'h1e,4'h0,GATINGMUXCMD,EXTTRIGMUXCMD,EP2MUXCMD,EP1MUXCMD};
-	parameter	[31:0]	MuxCtrl4RegCmd	=	{8'h1f,4'h0,EP6MUXCMD,EP5MUXCMD,EP4MUXCMD,EP3MUXCMD};
+	parameter	[31:0]	MuxCtrl1RegCmd		=	{8'h1c,4'h0,PG7MUXCMD,PG6MUXCMD,PG5MUXCMD,PG4MUXCMD};
+	parameter	[31:0]	MuxCtrl2RegCmd		=	{8'h1d,4'h0,PG3MUXCMD,PG2MUXCMD,PG1MUXCMD,SMPLSTRBMUXCMD};
+	parameter	[31:0]	MuxCtrl3RegCmd		=	{8'h1e,4'h0,GATINGMUXCMD,EXTTRIGMUXCMD,EP2MUXCMD,EP1MUXCMD};
+	parameter	[31:0]	MuxCtrl4RegCmd		=	{8'h1f,4'h0,EP6MUXCMD,EP5MUXCMD,EP4MUXCMD,EP3MUXCMD};
 	
 	//=================================================================================================================================================================================================================
 	

src/Top/PciVnaEmulTop.v

@@ -33,13 +33,16 @@ module PciVnaEmulTop
 );
 
 
-wire [32*9-1:0] measData;
+wire [31:0] measData;
 wire clk;
-wire endMeas;
-wire startMeasCmd;
 
 wire clkUser3;
 
+wire [7:0] addr;
+wire [31:0] cmd;
+wire readReq;
+wire wrReq;
+
 xilinx_pcie_2_1_ep_7x EP 
 (
   // SYS Inteface
@@ -55,10 +58,11 @@ xilinx_pcie_2_1_ep_7x EP
 
   .Clk_o(clk),
 
-  .MeasData_i(measData),
-  .MeasEnd_i(endMeas),
-
-  .StartMeasCmd_o(startMeasCmd),
+  .Data_i (measData),
+  .Cmd_o  (cmd),
+  .Addr_o (addr),
+  .ReadReq_o  (readReq),
+  .WrReq_o  (wrReq),
 
   .ClkUser3_o	(clkUser3)
 );
@@ -68,70 +72,67 @@ S5443Top FPGA_M
 	.Clk_i				(clkUser3), 
 	.Led_o				(),
 	
-    .Adc1FclkP_i		(),		
-    .Adc1FclkN_i		(),		
+	.Cmd_i         (cmd),
+	.Addr_i					(addr),
+	.MeasData_o			(measData),
+	.ReadReq_i		(readReq),
+	.WrReq_i			(wrReq),
+
+	.Adc1FclkP_i		(),		
+	.Adc1FclkN_i		(),		
 
-    .Adc1DataDa0P_i		(),
+	.Adc1DataDa0P_i		(),
 	.Adc1DataDa0N_i		(),		
-    .Adc1DataDa1P_i		(),
-    .Adc1DataDa1N_i		(),
+	.Adc1DataDa1P_i		(),
+	.Adc1DataDa1N_i		(),
 
 	.Adc1DataDb0P_i		(),
-    .Adc1DataDb0N_i		(),		
-    .Adc1DataDb1P_i		(),
-    .Adc1DataDb1N_i		(),
-	
-    .Adc2FclkP_i		(),		
-    .Adc2FclkN_i		(),		
-
-    .Adc2DataDa0P_i		(),
-    .Adc2DataDa0N_i		(),		
-    .Adc2DataDa1P_i		(),
-    .Adc2DataDa1N_i		(),
-  
+	.Adc1DataDb0N_i		(),		
+	.Adc1DataDb1P_i		(),
+	.Adc1DataDb1N_i		(),
+
+	.Adc2FclkP_i		(),		
+	.Adc2FclkN_i		(),		
+
+	.Adc2DataDa0P_i		(),
+	.Adc2DataDa0N_i		(),		
+	.Adc2DataDa1P_i		(),
+	.Adc2DataDa1N_i		(),
+
 	.Adc2DataDb0P_i		(),
-    .Adc2DataDb0N_i		(),		
-    .Adc2DataDb1P_i		(),
-    .Adc2DataDb1N_i		(),
+	.Adc2DataDb0N_i		(),		
+	.Adc2DataDb1P_i		(),
+	.Adc2DataDb1N_i		(),
 
 	.AdcInitMosi_o		(),
 	.AdcInitClk_o		(),			
 	.Adc1InitCs_o		(),
 	.Adc2InitCs_o		(),
 	.AdcInitRst_o		(),
-	
-	.Mosi_i				(),
-	.Sck_i				(),
-	.Ss_i				(),
-
-	.LpOutClk_o			(),
-	.LpOutFs_o			(),			
-	.LpOutData_o		(),
 
-	.StartMeas_i		(startMeasCmd),
+	.StartMeas_i		(),
 	.StartMeasEvent_o	(),
-	.EndMeas_o			(endMeas),
+	.EndMeas_o			(),
 	.TimersClk_o		(),
-	
+
 	.Trig6to1_io		(),	
 	.Trig6to1Dir_o		(),	
-	
+
 	.DspTrigOut_i		(),				
 	.DspTrigIn_o		(),				
-	
+
 	.OverloadS_i		(),
 	.Overload_o			(),
-	
+
 	.PortSel_o			(),
 	.PortSelDir_o		(),
-	
+
 	.Mod_o				(),	
-	
+
 	.DspReadyForRx_i		(),
 	.DspReadyForRxToFpgaS_o	(),
-	.AmpEn_o				(),
+	.AmpEn_o				()
 
-	.MeasData_o		(measData)
 );
 
 endmodule

src/Top/S5443Top.v

@@ -45,7 +45,7 @@ module	S5443Top
 	parameter	DataWidth			=	24,
 	parameter	DataNum				=	26,
 	parameter	CmdRegWidth			=	32,
-	parameter	HeaderWidth			=	7,
+	parameter	AddrWidth			=	8,
 	parameter	CmdDataRegWith		=	24,
 	parameter	DataCntWidth		=	5,
 	parameter	Divparam			=	4,
@@ -59,6 +59,14 @@ module	S5443Top
 	input	Clk_i,
 	output	Led_o,
 	
+	//pcie interface
+	input	[CmdRegWidth-1:0] Cmd_i,
+	input	[AddrWidth-1:0] Addr_i,
+
+	output	[ResultWidth-1:0] MeasData_o,
+ 	input	ReadReq_i,
+ 	input	WrReq_i,
+
 	//fpga-adc1 data interface
     input	Adc1FclkP_i,
     input	Adc1FclkN_i,
@@ -99,18 +107,6 @@ module	S5443Top
 	output	DitherCtrlCh1_o,
 	output	DitherCtrlCh2_o,
 	
-	//fpga-dsp cmd interface
-	input	Mosi_i,
-	input	Sck_i,
-	input	Ss_i,
-	input	Miso_i,
-	output	Miso_o,
-	
-	//fpga-dsp data interface
-	output	LpOutClk_o,
-	output	LpOutFs_o,
-	output	[LpDataWidth-1:0]	LpOutData_o,
-	
 	//fpga-dsp signals
 	input	StartMeas_i,		//"high"- start meas, "low"-stop meas
 	output	StartMeasEvent_o,
@@ -142,9 +138,7 @@ module	S5443Top
 	output	DspReadyForRxToFpgaS_o,
 	
 	output	StartMeasDsp_o,
-	output	[ChNum-1:0]	AmpEn_o,	//	0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
-	
-	output  [ResultWidth*9-1:0] MeasData_o
+	output	[ChNum-1:0]	AmpEn_o	//	0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
 );
 //================================================================================
 //  reg/wire
@@ -200,8 +194,7 @@ module	S5443Top
 	wire	[CmdRegWidth-1:0]	cmdDataReg;
 	wire	cmdDataVal;
 	
-	wire	[CmdDataRegWith-1:0]	ansReg;	
-	wire	[HeaderWidth-1:0]		ansAddr;
+	wire	[CmdDataRegWith-1:0]	ansReg;
 	
 	wire	[CmdDataRegWith-1:0]	gainCtrl;
 	wire	[CmdDataRegWith-1:0]	gainLowThreshT1;
@@ -365,6 +358,8 @@ module	S5443Top
 	wire	[CmdDataRegWith-1:0]	muxCtrl3;
 	wire	[CmdDataRegWith-1:0]	muxCtrl4;
 
+	wire	[CmdDataRegWith-1:0]	measSeqCfg;
+
 	wire	[CmdRegWidth-29:0]	pgModeArray		[PGenNum-1:0];
 	wire	pgPulsePolArray		[PGenNum-1:0];
 	wire	pgEnEdgeArray		[PGenNum-1:0];
@@ -411,6 +406,7 @@ module	S5443Top
 	wire	[31:0]	serviceData	=	{ampEnR2,ampEnT2,ampEnR1,ampEnT1};
 	wire	[ResultWidth*(ChNum*2+1)-1:0]	measDataBus;
 
+	wire 	measDataRdreq;
 //================================================================================
 //  assignments
 //================================================================================	
@@ -695,77 +691,6 @@ Clk200Gen	ClocksGenerator
 // 	.Adc2ChR2Data_o	(adc2ChR2Data),
 // 	.Adc2ChT2Data_o	(adc2ChT2Data)
 // );  
- 
-//--------------------------------------------------------------------------------
-//	External DSP Interface
-//--------------------------------------------------------------------------------
-
-/*DspInterface 
-#(	
-	.ODataWidth			(LpDataWidth),	
-	.ResultWidth		(ResultWidth),
-	.ChNum				(ChNum),
-	.CmdRegWidth		(CmdRegWidth),
-	.CmdDataRegWith		(CmdDataRegWith),
-	.HeaderWidth		(HeaderWidth),
-	.DataCntWidth		(DataCntWidth)
-)
-ExternalDspInterface
-(
-	.Clk_i				(gclk),
-	.Rst_i				(initRst),
-	.OscWind_i			(oscWind),
-	.StartMeasDsp_i		(startMeasSyncRR),
-	.DspReadyForRx_i	(dspReadyForRxRegRR),
-	.MeasNum_i			({measNum2[7:0],measNum1}),
-	
-	.Mosi_i				(Mosi_i),
-	.Sck_i				(Sck_i),
-	.Ss_i				(Ss_i),
-
-	.Mode_i				(measCtrl[0]),
-	.PortSel_i			(measCtrl[23:22]),
-	.DecimFactor_i		(measCtrl[3:1]),
-	.IfFtwL_i			(ifFtwL),
-	.IfFtwH_i			(ifFtwH),
-	
-	.OscDataRdFlag_o	(oscDataRdFlag),
-	
-	.Adc1ChT1Data_i		(adcDataBus[ChNum-1]),	
-	.Adc1ChR1Data_i		(adcDataBus[ChNum-1]),	
-	.Adc2ChR2Data_i		(adcDataBus[ChNum-1]),	
-	.Adc2ChT2Data_i		(adcDataBus[ChNum-1]),		
-	
-	.Mosi_o				(adcInitMosi),
-	.Sck_o				(adcInitSck),
-	.Ss0_o				(adc0InitCs),
-	.Ss1_o				(adc1InitCs),
-	.Miso_i				(Miso_i),
-	.Miso_o				(Miso_o),
-	
-	.CmdDataReg_o		(cmdDataReg),
-	.CmdDataVal_o		(cmdDataVal),
-	
-	.AnsReg_i			(ansReg),
-	.AnsAddr_o			(ansAddr),
-	
-	.LpOutFs_o			(LpOutFs_o),
-	.LpOutClk_o			(LpOutClk_o),
-	.LpOutData_o		(LpOutData_o),
-	
-	.Adc1T1ImResult_i	(adc1ImT1),
-	.Adc1T1ReResult_i	(adc1ReT1),
-	.Adc1R1ImResult_i	(adc1ImR1),
-	.Adc1R1ReResult_i	(adc1ReR1),
-	
-	.Adc2R2ImResult_i	(adc2ImR2),
-	.Adc2R2ReResult_i	(adc2ReR2),
-	.Adc2T2ImResult_i	(adc2ImT2),
-	.Adc2T2ReResult_i	(adc2ReT2),
-	.ServiseRegData_i	(ampEnNewStates),
-	
-	.LpOutStart_i		(measDataRdy)
-);*/
 
 //--------------------------------------------------------------------------------
 //	Internal DSP calculation module
@@ -804,7 +729,7 @@ InternalDsp
 	.GatingPulse_i			(gatingPulse),
 
 	.StartMeas_i			(measStart),
-	.StartMeasDsp_i			(startMeasSyncRR),
+	.StartMeasDsp_i			(measSeqCfg[0]),
 	.OscDataRdFlag_i		(oscDataRdFlag),
 
 	.MeasNum_i				({measNum2[7:0],measNum1}),
@@ -845,7 +770,7 @@ InternalDsp
 RegMap	
 #(	
 	.CmdRegWidth	(CmdRegWidth),
-	.HeaderWidth	(HeaderWidth),
+	.AddrWidth		(AddrWidth),
 	.CmdDataRegWith	(CmdDataRegWith)
 )
 RegMapInst
@@ -854,11 +779,15 @@ RegMapInst
 	.Rst_i					(initRst),
 	.PGenRstDone_i			(pGenRstDone),
 	
-	.Val_i					(cmdDataVal),
 	.CalDone_i				(calDone),
-	.Data_i					(cmdDataReg),
-	.AnsAddr_i				(ansAddr),
-	.AnsDataReg_o			(ansReg),
+
+	.Cmd_i					(Cmd_i),
+	.Addr_i					(Addr_i),
+	.ReadReq_i            (ReadReq_i),
+	.WrReq_i              (WrReq_i),
+	.MeasEnd_i				(measDataRdy),
+	.AnsData_o				(ansReg),
+	.MeasDataReq_o			(measDataRdreq),
 	
 	.OverCtrlReg_i			(overCtrl),
 	
@@ -966,7 +895,8 @@ RegMapInst
 	.MuxCtrl1Reg_o			(muxCtrl1),
 	.MuxCtrl2Reg_o			(muxCtrl2),
 	.MuxCtrl3Reg_o			(muxCtrl3),
-	.MuxCtrl4Reg_o			(muxCtrl4)
+	.MuxCtrl4Reg_o			(muxCtrl4),
+	.MeasSeqCfgReg_o		(measSeqCfg)
 );
 
 //--------------------------------------------------------------------------------
@@ -1105,7 +1035,7 @@ MeasTrigMux
 	.MuxCtrl_i		(muxCtrl3[14:10]),
 
 	.DspTrigOut_i	(1'b0),
-	.DspStartCmd_i	(startMeasSyncRR),
+	.DspStartCmd_i	(measSeqCfg[0]),
 	.IntTrig_i		(1'b0),
 	.IntTrig2_i		(1'b0),
 	.PulseBus_i		(7'b0),
@@ -1123,7 +1053,7 @@ MeasStartEventGen	MeasStartEventGenInst
 	.Clk_i				(gclk),
 	
 	.MeasTrig_i			(measTrig),
-	.StartMeasDsp_i		(startMeasSyncRR),
+	.StartMeasDsp_i		(measSeqCfg[0]),
 	
 	.StartMeasEvent_o	(startMeasEvent),
 	.InitTrig_o			()
@@ -1277,7 +1207,7 @@ ExtPortsMux
 	.MuxCtrl_i		(extTrigMuxCtrlArray[l]),
 
 	.DspTrigOut_i	(DspTrigOut_i),
-	.DspStartCmd_i	(startMeasSyncRR), //tut nichego nebilo 14.02.2023 zamknul suda startMeasSync
+	.DspStartCmd_i	(measSeqCfg[0]), //tut nichego nebilo 14.02.2023 zamknul suda startMeasSync
 	.IntTrig_i		(intTrig1),
 	.IntTrig2_i		(intTrig2),
 	.PulseBus_i		(pulseBus),