Test cganges

recreate.tcl

@@ -1,9 +1,9 @@
 #*****************************************************************************************
 # Vivado (TM) v2024.1 (64-bit)
 #
-# recreate.tcl: Tcl script for re-creating project 'pcie1234_ex'
+# recreate.tcl: Tcl script for re-creating project 'PciVnaEmul'
 #
-# Generated by Vivado on Wed Oct 09 12:53:56 +0300 2024
+# Generated by Vivado on Thu Oct 10 10:35:07 +0300 2024
 # IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
 #
 # This file contains the Vivado Tcl commands for re-creating the project to the state*
@@ -23,87 +23,95 @@
 # 2. The following source(s) files that were local or imported into the original project.
 #    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
 #
-#    "D:/testPci/pcie1234_ex/pcie1234_ex.srcs/sources_1/ip/pcie1234/pcie1234.xci"
-#    "D:/testPci/pcie1234_ex/pcie1234_ex.srcs/sources_1/ip/ClkPllSysTo125/ClkPllSysTo125.xci"
+#    "C:/PciVnaEmul_PROJ/PciVnaEmul.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo.xci"
+#    "C:/PciVnaEmul_PROJ/PciVnaEmul.srcs/sources_1/ip/pcie1234/pcie1234.xci"
+#    "C:/PciVnaEmul_PROJ/PciVnaEmul.srcs/sources_1/ip/ClkPllSysTo125/ClkPllSysTo125.xci"
+#    "C:/PciVnaEmul_PROJ/PciVnaEmul.srcs/sources_1/ip/CdcFifo/CdcFifo.xci"
+#    "C:/PciVnaEmul_PROJ/PciVnaEmul.srcs/utils_1/imports/synth_1/PciVnaEmulTop.dcp"
 #
 # 3. The following remote source files that were added to the original project:-
 #
-#    "C:/PciVnaEmul_Repo/src/PulseMeas/ActivePortSelector.v"
-#    "C:/PciVnaEmul_Repo/src/InternalDsp/AdcCalibration.v"
-#    "C:/PciVnaEmul_Repo/src/InternalDsp/ComplPrng.v"
-#    "C:/PciVnaEmul_Repo/src/InternalDsp/CordicNco.v"
-#    "C:/PciVnaEmul_Repo/src/InternalDsp/CordicRotation.v"
-#    "C:/PciVnaEmul_Repo/src/DitherGen/DitherGenv2.v"
-#    "C:/PciVnaEmul_Repo/src/InternalDsp/DspPipeline.v"
-#    "C:/PciVnaEmul_Repo/src/PciE/EP_MEM.v"
-#    "C:/PciVnaEmul_Repo/src/Math/FpCustomMultiplier.v"
-#    "C:/PciVnaEmul_Repo/src/GainOverloadControl/GainControl.v"
-#    "C:/PciVnaEmul_Repo/src/GainOverloadControl/GainControlWrapper.v"
-#    "C:/PciVnaEmul_Repo/src/InitRst/InitRst.v"
-#    "C:/PciVnaEmul_Repo/src/Top/IntermediateLogic.v"
-#    "C:/PciVnaEmul_Repo/src/InternalDsp/InternalDsp.v"
-#    "C:/PciVnaEmul_Repo/src/InternalDsp/MeasCtrlModule.v"
-#    "C:/PciVnaEmul_Repo/src/PulseMeas/MeasStartEventGen.v"
-#    "C:/PciVnaEmul_Repo/src/Math/MultModule.v"
-#    "C:/PciVnaEmul_Repo/src/PulseMeas/Mux.v"
-#    "C:/PciVnaEmul_Repo/src/Math/MyIntToFp.v"
-#    "C:/PciVnaEmul_Repo/src/InternalDsp/NcoRstGen.v"
-#    "C:/PciVnaEmul_Repo/src/GainOverloadControl/OverloadDetect.v"
-#    "C:/PciVnaEmul_Repo/src/PulseMeas/PGenRstGenerator.v"
-#    "C:/PciVnaEmul_Repo/src/PciE/PIO.v"
-#    "C:/PciVnaEmul_Repo/src/PciE/PIO_EP.v"
-#    "C:/PciVnaEmul_Repo/src/PciE/PIO_EP_MEM_ACCESS.v"
-#    "C:/PciVnaEmul_Repo/src/PciE/PIO_RX_ENGINE.v"
-#    "C:/PciVnaEmul_Repo/src/PciE/PIO_TO_CTRL.v"
-#    "C:/PciVnaEmul_Repo/src/PciE/PIO_TX_ENGINE.v"
-#    "C:/PciVnaEmul_Repo/src/PulseMeas/PulseGen.v"
-#    "C:/PciVnaEmul_Repo/src/RegMap/RegMap.v"
-#    "C:/PciVnaEmul_Repo/src/Top/S5443Top.v"
-#    "C:/PciVnaEmul_Repo/src/PulseMeas/SampleStrobeGenRstDemux.v"
-#    "C:/PciVnaEmul_Repo/src/Math/SimpleMult.v"
-#    "C:/PciVnaEmul_Repo/src/PulseMeas/StartAfterGainSel.v"
-#    "C:/PciVnaEmul_Repo/src/Math/SumAcc.v"
-#    "C:/PciVnaEmul_Repo/src/PulseMeas/TrigInt2Mux.v"
-#    "C:/PciVnaEmul_Repo/src/InternalDsp/WinParameters.v"
-#    "C:/PciVnaEmul_Repo/src/InternalDsp/Win_calc.v"
-#    "C:/PciVnaEmul_Repo/src/PciE/pcie1234_pipe_clock.v"
-#    "C:/PciVnaEmul_Repo/src/PciE/pcie1234_support.v"
-#    "C:/PciVnaEmul_Repo/src/PciE/pcie_app_7x.v"
-#    "C:/PciVnaEmul_Repo/src/PciE/xilinx_pcie_2_1_ep_7x.v"
-#    "C:/PciVnaEmul_Repo/src/Top/PciVnaEmulTop.v"
-#    "C:/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_pl.v"
-#    "C:/PciVnaEmul_Repo/src/ClkGen/Clk200Gen.v"
-#    "C:/PciVnaEmul_Repo/src/ExtDspInterface/DspPpiOut.v"
-#    "C:/PciVnaEmul_Repo/src/PciE/pci_exp_expect_tasks.vh"
-#    "C:/PciVnaEmul_Repo/src/PciE/sys_clk_gen.v"
-#    "C:/PciVnaEmul_Repo/src/AdcDataRx/delay_controller_wrap.v"
-#    "C:/PciVnaEmul_Repo/src/PciE/xilinx_pcie_2_1_rport_7x.v"
-#    "C:/PciVnaEmul_Repo/src/AdcDataRx/n_x_serdes_1_to_7_mmcm_idelay_sdr.v"
-#    "C:/PciVnaEmul_Repo/src/AdcDataRx/serdes_1_to_7_mmcm_idelay_sdr.v"
-#    "C:/PciVnaEmul_Repo/src/PciE/pcie1234_gt_top_pipe_mode.v"
-#    "C:/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_cfg.v"
-#    "C:/PciVnaEmul_Repo/src/AdcDataRx/AdcDataInterface.v"
-#    "C:/PciVnaEmul_Repo/src/MeasDataFifo/FifoController.v"
-#    "C:/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_tx.v"
-#    "C:/PciVnaEmul_Repo/src/AdcDataRx/AdcSync.v"
-#    "C:/PciVnaEmul_Repo/src/ExtDspInterface/DspInterface.v"
-#    "C:/PciVnaEmul_Repo/src/AdcDataRx/serdes_1_to_7_slave_idelay_sdr.v"
-#    "C:/PciVnaEmul_Repo/src/PciE/pipe_interconnect.vh"
-#    "C:/PciVnaEmul_Repo/src/ExtDspInterface/SlaveSpi.v"
-#    "C:/PciVnaEmul_Repo/src/PciE/xil_sig2pipe.v"
-#    "C:/PciVnaEmul_Repo/src/MeasDataFifo/MeasDataFifoWrapper.v"
-#    "C:/PciVnaEmul_Repo/src/PulseMeas/PulseGenNew.v"
-#    "C:/PciVnaEmul_Repo/src/PciE/sample_tests1.vh"
-#    "C:/PciVnaEmul_Repo/src/PciE/board_common.vh"
-#    "C:/PciVnaEmul_Repo/src/PciE/pcie_axi_trn_bridge.v"
-#    "C:/PciVnaEmul_Repo/src/AdcDataRx/top5x2_7to1_sdr_rx.v"
-#    "C:/PciVnaEmul_Repo/src/PciE/pcie_2_1_rport_7x.v"
-#    "C:/PciVnaEmul_Repo/src/PciE/sys_clk_gen_ds.v"
-#    "C:/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_rx.v"
-#    "C:/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_com.v"
-#    "C:/PciVnaEmul_Repo/src/PciE/tests.vh"
-#    "C:/PciVnaEmul_Repo/constr/xilinx_pcie_7x_ep_x1g1.xdc"
-#    "C:/PciVnaEmul_Repo/src/PciE/board.v"
+#    "C:/PciVnaEmul_REPO/src/PulseMeas/ActivePortSelector.v"
+#    "C:/PciVnaEmul_REPO/src/InternalDsp/AdcCalibration.v"
+#    "C:/PciVnaEmul_REPO/src/InternalDsp/ComplPrng.v"
+#    "C:/PciVnaEmul_REPO/src/InternalDsp/CordicNco.v"
+#    "C:/PciVnaEmul_REPO/src/InternalDsp/CordicRotation.v"
+#    "C:/PciVnaEmul_REPO/src/DitherGen/DitherGenv2.v"
+#    "C:/PciVnaEmul_REPO/src/InternalDsp/DspPipeline.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/EP_MEM.v"
+#    "C:/PciVnaEmul_REPO/src/Math/FpCustomMultiplier.v"
+#    "C:/PciVnaEmul_REPO/src/GainOverloadControl/GainControl.v"
+#    "C:/PciVnaEmul_REPO/src/GainOverloadControl/GainControlWrapper.v"
+#    "C:/PciVnaEmul_REPO/src/InitRst/InitRst.v"
+#    "C:/PciVnaEmul_REPO/src/Top/IntermediateLogic.v"
+#    "C:/PciVnaEmul_REPO/src/InternalDsp/InternalDsp.v"
+#    "C:/PciVnaEmul_REPO/src/InternalDsp/MeasCtrlModule.v"
+#    "C:/PciVnaEmul_REPO/src/PulseMeas/MeasStartEventGen.v"
+#    "C:/PciVnaEmul_REPO/src/Math/MultModule.v"
+#    "C:/PciVnaEmul_REPO/src/PulseMeas/Mux.v"
+#    "C:/PciVnaEmul_REPO/src/Math/MyIntToFp.v"
+#    "C:/PciVnaEmul_REPO/src/InternalDsp/NcoRstGen.v"
+#    "C:/PciVnaEmul_REPO/src/GainOverloadControl/OverloadDetect.v"
+#    "C:/PciVnaEmul_REPO/src/PulseMeas/PGenRstGenerator.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/PIO.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/PIO_EP.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/PIO_EP_MEM_ACCESS.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/PIO_RX_ENGINE.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/PIO_TO_CTRL.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/PIO_TX_ENGINE.v"
+#    "C:/PciVnaEmul_REPO/src/PulseMeas/PulseGen.v"
+#    "C:/PciVnaEmul_REPO/src/RegMap/RegMap.v"
+#    "C:/PciVnaEmul_REPO/src/Top/S5443Top.v"
+#    "C:/PciVnaEmul_REPO/src/PulseMeas/SampleStrobeGenRstDemux.v"
+#    "C:/PciVnaEmul_REPO/src/Math/SimpleMult.v"
+#    "C:/PciVnaEmul_REPO/src/PulseMeas/StartAfterGainSel.v"
+#    "C:/PciVnaEmul_REPO/src/Math/SumAcc.v"
+#    "C:/PciVnaEmul_REPO/src/PulseMeas/TrigInt2Mux.v"
+#    "C:/PciVnaEmul_REPO/src/InternalDsp/WinParameters.v"
+#    "C:/PciVnaEmul_REPO/src/InternalDsp/Win_calc.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/pcie1234_pipe_clock.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/pcie1234_support.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/pcie_app_7x.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/xilinx_pcie_2_1_ep_7x.v"
+#    "C:/PciVnaEmul_REPO/src/Top/PciVnaEmulTop.v"
+#    "C:/PciVnaEmul_REPO/src/ExtDspInterface/DspInterface.v"
+#    "C:/PciVnaEmul_REPO/src/MeasDataFifo/FifoController.v"
+#    "C:/PciVnaEmul_REPO/src/MeasDataFifo/MeasDataFifoWrapper.v"
+#    "C:/PciVnaEmul_REPO/src/ExtDspInterface/SlaveSpi.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/board_common.vh"
+#    "C:/PciVnaEmul_REPO/src/PciE/pci_exp_expect_tasks.vh"
+#    "C:/PciVnaEmul_REPO/src/PciE/tests.vh"
+#    "C:/PciVnaEmul_REPO/src/PciE/sample_tests1.vh"
+#    "C:/PciVnaEmul_REPO/src/PciE/pipe_interconnect.vh"
+#    "C:/PciVnaEmul_REPO/src/PciE/pcie1234_gt_top_pipe_mode.v"
+#    "C:/PciVnaEmul_REPO/constr/xilinx_pcie_7x_ep_x1g1.xdc"
+#    "C:/PciVnaEmul_REPO/src/Sim/S5443TopSimpleMeasTb.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/EP_MEM.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/PIO.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/PIO_EP.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/PIO_EP_MEM_ACCESS.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/PIO_RX_ENGINE.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/PIO_TO_CTRL.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/PIO_TX_ENGINE.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/board_common.vh"
+#    "C:/PciVnaEmul_REPO/src/PciE/pci_exp_usrapp_cfg.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/pci_exp_expect_tasks.vh"
+#    "C:/PciVnaEmul_REPO/src/PciE/pci_exp_usrapp_com.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/pci_exp_usrapp_pl.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/pci_exp_usrapp_rx.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/tests.vh"
+#    "C:/PciVnaEmul_REPO/src/PciE/sample_tests1.vh"
+#    "C:/PciVnaEmul_REPO/src/PciE/pci_exp_usrapp_tx.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/pcie1234_pipe_clock.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/pcie1234_support.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/pcie_app_7x.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/pcie_axi_trn_bridge.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/sys_clk_gen.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/sys_clk_gen_ds.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/xilinx_pcie_2_1_ep_7x.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/xilinx_pcie_2_1_rport_7x.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/board.v"
+#    "C:/PciVnaEmul_REPO/src/PciE/pipe_interconnect.vh"
 #
 #*****************************************************************************************
 
@@ -111,8 +119,11 @@
 proc checkRequiredFiles { origin_dir} {
   set status true
   set files [list \
-   "D:/testPci/pcie1234_ex/pcie1234_ex.srcs/sources_1/ip/pcie1234/pcie1234.xci" \
-   "D:/testPci/pcie1234_ex/pcie1234_ex.srcs/sources_1/ip/ClkPllSysTo125/ClkPllSysTo125.xci" \
+ "[file normalize "$origin_dir/PciVnaEmul_PROJ/PciVnaEmul.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo.xci"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_PROJ/PciVnaEmul.srcs/sources_1/ip/pcie1234/pcie1234.xci"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_PROJ/PciVnaEmul.srcs/sources_1/ip/ClkPllSysTo125/ClkPllSysTo125.xci"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_PROJ/PciVnaEmul.srcs/sources_1/ip/CdcFifo/CdcFifo.xci"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_PROJ/PciVnaEmul.srcs/utils_1/imports/synth_1/PciVnaEmulTop.dcp"]"\
   ]
   foreach ifile $files {
     if { ![file isfile $ifile] } {
@@ -122,82 +133,87 @@ proc checkRequiredFiles { origin_dir} {
   }
 
   set files [list \
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PulseMeas/ActivePortSelector.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/InternalDsp/AdcCalibration.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/InternalDsp/ComplPrng.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/InternalDsp/CordicNco.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/InternalDsp/CordicRotation.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/DitherGen/DitherGenv2.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/InternalDsp/DspPipeline.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/EP_MEM.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/Math/FpCustomMultiplier.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/GainOverloadControl/GainControl.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/GainOverloadControl/GainControlWrapper.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/InitRst/InitRst.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/Top/IntermediateLogic.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/InternalDsp/InternalDsp.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/InternalDsp/MeasCtrlModule.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PulseMeas/MeasStartEventGen.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/Math/MultModule.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PulseMeas/Mux.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/Math/MyIntToFp.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/InternalDsp/NcoRstGen.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/GainOverloadControl/OverloadDetect.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PulseMeas/PGenRstGenerator.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/PIO.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/PIO_EP.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/PIO_EP_MEM_ACCESS.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/PIO_RX_ENGINE.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/PIO_TO_CTRL.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/PIO_TX_ENGINE.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PulseMeas/PulseGen.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/RegMap/RegMap.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/Top/S5443Top.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PulseMeas/SampleStrobeGenRstDemux.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/Math/SimpleMult.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PulseMeas/StartAfterGainSel.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/Math/SumAcc.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PulseMeas/TrigInt2Mux.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/InternalDsp/WinParameters.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/InternalDsp/Win_calc.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/pcie1234_pipe_clock.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/pcie1234_support.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/pcie_app_7x.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/xilinx_pcie_2_1_ep_7x.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/Top/PciVnaEmulTop.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_pl.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/ClkGen/Clk200Gen.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/ExtDspInterface/DspPpiOut.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/pci_exp_expect_tasks.vh"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/sys_clk_gen.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/AdcDataRx/delay_controller_wrap.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/xilinx_pcie_2_1_rport_7x.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/AdcDataRx/n_x_serdes_1_to_7_mmcm_idelay_sdr.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/AdcDataRx/serdes_1_to_7_mmcm_idelay_sdr.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/pcie1234_gt_top_pipe_mode.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_cfg.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/AdcDataRx/AdcDataInterface.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/MeasDataFifo/FifoController.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_tx.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/AdcDataRx/AdcSync.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/ExtDspInterface/DspInterface.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/AdcDataRx/serdes_1_to_7_slave_idelay_sdr.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/pipe_interconnect.vh"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/ExtDspInterface/SlaveSpi.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/xil_sig2pipe.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/MeasDataFifo/MeasDataFifoWrapper.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PulseMeas/PulseGenNew.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/sample_tests1.vh"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/board_common.vh"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/pcie_axi_trn_bridge.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/AdcDataRx/top5x2_7to1_sdr_rx.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/pcie_2_1_rport_7x.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/sys_clk_gen_ds.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_rx.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_com.v"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/tests.vh"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/constr/xilinx_pcie_7x_ep_x1g1.xdc"]"\
- "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/board.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PulseMeas/ActivePortSelector.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/InternalDsp/AdcCalibration.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/InternalDsp/ComplPrng.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/InternalDsp/CordicNco.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/InternalDsp/CordicRotation.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/DitherGen/DitherGenv2.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/InternalDsp/DspPipeline.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/EP_MEM.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/Math/FpCustomMultiplier.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/GainOverloadControl/GainControl.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/GainOverloadControl/GainControlWrapper.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/InitRst/InitRst.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/Top/IntermediateLogic.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/InternalDsp/InternalDsp.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/InternalDsp/MeasCtrlModule.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PulseMeas/MeasStartEventGen.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/Math/MultModule.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PulseMeas/Mux.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/Math/MyIntToFp.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/InternalDsp/NcoRstGen.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/GainOverloadControl/OverloadDetect.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PulseMeas/PGenRstGenerator.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/PIO.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/PIO_EP.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/PIO_EP_MEM_ACCESS.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/PIO_RX_ENGINE.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/PIO_TO_CTRL.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/PIO_TX_ENGINE.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PulseMeas/PulseGen.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/RegMap/RegMap.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/Top/S5443Top.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PulseMeas/SampleStrobeGenRstDemux.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/Math/SimpleMult.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PulseMeas/StartAfterGainSel.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/Math/SumAcc.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PulseMeas/TrigInt2Mux.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/InternalDsp/WinParameters.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/InternalDsp/Win_calc.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/pcie1234_pipe_clock.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/pcie1234_support.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/pcie_app_7x.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/xilinx_pcie_2_1_ep_7x.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/Top/PciVnaEmulTop.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/ExtDspInterface/DspInterface.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/MeasDataFifo/FifoController.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/MeasDataFifo/MeasDataFifoWrapper.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/ExtDspInterface/SlaveSpi.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/board_common.vh"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/pci_exp_expect_tasks.vh"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/tests.vh"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/sample_tests1.vh"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/pipe_interconnect.vh"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/pcie1234_gt_top_pipe_mode.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/constr/xilinx_pcie_7x_ep_x1g1.xdc"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/Sim/S5443TopSimpleMeasTb.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/EP_MEM.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/PIO.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/PIO_EP.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/PIO_EP_MEM_ACCESS.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/PIO_RX_ENGINE.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/PIO_TO_CTRL.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/PIO_TX_ENGINE.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/board_common.vh"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/pci_exp_usrapp_cfg.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/pci_exp_expect_tasks.vh"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/pci_exp_usrapp_com.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/pci_exp_usrapp_pl.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/pci_exp_usrapp_rx.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/tests.vh"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/sample_tests1.vh"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/pci_exp_usrapp_tx.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/pcie1234_pipe_clock.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/pcie1234_support.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/pcie_app_7x.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/pcie_axi_trn_bridge.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/sys_clk_gen.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/sys_clk_gen_ds.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/xilinx_pcie_2_1_ep_7x.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/xilinx_pcie_2_1_rport_7x.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/board.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_REPO/src/PciE/pipe_interconnect.vh"]"\
   ]
   foreach ifile $files {
     if { ![file isfile $ifile] } {
@@ -217,7 +233,7 @@ if { [info exists ::origin_dir_loc] } {
 }
 
 # Set the project name
-set _xil_proj_name_ "pcie1234_ex"
+set _xil_proj_name_ "PciVnaEmul"
 
 # Use project name variable, if specified in the tcl shell
 if { [info exists ::user_project_name] } {
@@ -273,7 +289,7 @@ if { $::argc > 0 } {
 }
 
 # Set the directory path for the original project from where this script was exported
-set orig_proj_dir "D:/testPci/pcie1234_ex"
+set orig_proj_dir "[file normalize "$origin_dir/PciVnaEmul_PROJ"]"
 
 # Check for paths and files needed for project creation
 set validate_required 0
@@ -301,22 +317,15 @@ set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
 set_property -name "enable_resource_estimation" -value "0" -objects $obj
 set_property -name "enable_vhdl_2008" -value "1" -objects $obj
 set_property -name "ip_cache_permissions" -value "read write" -objects $obj
-set_property -name "ip_output_repo" -value "D:/testPci/${_xil_proj_name_}/${_xil_proj_name_}.cache/ip" -objects $obj
+set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
 set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
 set_property -name "part" -value "xc7a100tfgg484-2" -objects $obj
 set_property -name "revised_directory_structure" -value "1" -objects $obj
-set_property -name "sim.central_dir" -value "D:/testPci/${_xil_proj_name_}/${_xil_proj_name_}.ip_user_files" -objects $obj
+set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
 set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
 set_property -name "simulator_language" -value "Mixed" -objects $obj
 set_property -name "sim_compile_state" -value "1" -objects $obj
-set_property -name "webtalk.activehdl_export_sim" -value "8" -objects $obj
-set_property -name "webtalk.ies_export_sim" -value "7" -objects $obj
-set_property -name "webtalk.modelsim_export_sim" -value "8" -objects $obj
-set_property -name "webtalk.questa_export_sim" -value "8" -objects $obj
-set_property -name "webtalk.riviera_export_sim" -value "8" -objects $obj
-set_property -name "webtalk.vcs_export_sim" -value "8" -objects $obj
-set_property -name "webtalk.xsim_export_sim" -value "8" -objects $obj
-set_property -name "webtalk.xsim_launch_sim" -value "57" -objects $obj
+set_property -name "webtalk.xsim_launch_sim" -value "69" -objects $obj
 set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
 
 # Create 'sources_1' fileset (if not found)
@@ -327,120 +336,130 @@ if {[string equal [get_filesets -quiet sources_1] ""]} {
 # Set 'sources_1' fileset object
 set obj [get_filesets sources_1]
 set files [list \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PulseMeas/ActivePortSelector.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/InternalDsp/AdcCalibration.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/InternalDsp/ComplPrng.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/InternalDsp/CordicNco.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/InternalDsp/CordicRotation.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/DitherGen/DitherGenv2.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/InternalDsp/DspPipeline.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/EP_MEM.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/Math/FpCustomMultiplier.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/GainOverloadControl/GainControl.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/GainOverloadControl/GainControlWrapper.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/InitRst/InitRst.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/Top/IntermediateLogic.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/InternalDsp/InternalDsp.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/InternalDsp/MeasCtrlModule.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PulseMeas/MeasStartEventGen.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/Math/MultModule.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PulseMeas/Mux.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/Math/MyIntToFp.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/InternalDsp/NcoRstGen.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/GainOverloadControl/OverloadDetect.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PulseMeas/PGenRstGenerator.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/PIO.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/PIO_EP.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/PIO_EP_MEM_ACCESS.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/PIO_RX_ENGINE.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/PIO_TO_CTRL.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/PIO_TX_ENGINE.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PulseMeas/PulseGen.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/RegMap/RegMap.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/Top/S5443Top.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PulseMeas/SampleStrobeGenRstDemux.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/Math/SimpleMult.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PulseMeas/StartAfterGainSel.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/Math/SumAcc.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PulseMeas/TrigInt2Mux.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/InternalDsp/WinParameters.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/InternalDsp/Win_calc.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/pcie1234_pipe_clock.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/pcie1234_support.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/pcie_app_7x.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/xilinx_pcie_2_1_ep_7x.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/Top/PciVnaEmulTop.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_pl.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/ClkGen/Clk200Gen.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/ExtDspInterface/DspPpiOut.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/pci_exp_expect_tasks.vh"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/sys_clk_gen.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/AdcDataRx/delay_controller_wrap.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/xilinx_pcie_2_1_rport_7x.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/AdcDataRx/n_x_serdes_1_to_7_mmcm_idelay_sdr.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/AdcDataRx/serdes_1_to_7_mmcm_idelay_sdr.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/pcie1234_gt_top_pipe_mode.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_cfg.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/AdcDataRx/AdcDataInterface.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/MeasDataFifo/FifoController.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_tx.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/AdcDataRx/AdcSync.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/ExtDspInterface/DspInterface.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/AdcDataRx/serdes_1_to_7_slave_idelay_sdr.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/pipe_interconnect.vh"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/ExtDspInterface/SlaveSpi.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/xil_sig2pipe.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/MeasDataFifo/MeasDataFifoWrapper.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PulseMeas/PulseGenNew.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/sample_tests1.vh"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/board_common.vh"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/pcie_axi_trn_bridge.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/AdcDataRx/top5x2_7to1_sdr_rx.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/pcie_2_1_rport_7x.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/sys_clk_gen_ds.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_rx.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_com.v"] \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/tests.vh"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PulseMeas/ActivePortSelector.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/InternalDsp/AdcCalibration.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/InternalDsp/ComplPrng.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/InternalDsp/CordicNco.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/InternalDsp/CordicRotation.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/DitherGen/DitherGenv2.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/InternalDsp/DspPipeline.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/EP_MEM.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/Math/FpCustomMultiplier.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/GainOverloadControl/GainControl.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/GainOverloadControl/GainControlWrapper.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/InitRst/InitRst.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/Top/IntermediateLogic.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/InternalDsp/InternalDsp.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/InternalDsp/MeasCtrlModule.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PulseMeas/MeasStartEventGen.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/Math/MultModule.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PulseMeas/Mux.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/Math/MyIntToFp.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/InternalDsp/NcoRstGen.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/GainOverloadControl/OverloadDetect.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PulseMeas/PGenRstGenerator.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/PIO.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/PIO_EP.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/PIO_EP_MEM_ACCESS.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/PIO_RX_ENGINE.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/PIO_TO_CTRL.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/PIO_TX_ENGINE.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PulseMeas/PulseGen.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/RegMap/RegMap.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/Top/S5443Top.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PulseMeas/SampleStrobeGenRstDemux.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/Math/SimpleMult.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PulseMeas/StartAfterGainSel.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/Math/SumAcc.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PulseMeas/TrigInt2Mux.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/InternalDsp/WinParameters.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/InternalDsp/Win_calc.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/pcie1234_pipe_clock.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/pcie1234_support.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/pcie_app_7x.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/xilinx_pcie_2_1_ep_7x.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/Top/PciVnaEmulTop.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/ExtDspInterface/DspInterface.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/MeasDataFifo/FifoController.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/MeasDataFifo/MeasDataFifoWrapper.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/ExtDspInterface/SlaveSpi.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/board_common.vh"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/pci_exp_expect_tasks.vh"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/tests.vh"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/sample_tests1.vh"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/pipe_interconnect.vh"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/pcie1234_gt_top_pipe_mode.v"] \
 ]
 add_files -norecurse -fileset $obj $files
 
-# Import local files from the original project
-set files [list \
- "D:/testPci/pcie1234_ex/pcie1234_ex.srcs/sources_1/ip/pcie1234/pcie1234.xci"\
- "D:/testPci/pcie1234_ex/pcie1234_ex.srcs/sources_1/ip/ClkPllSysTo125/ClkPllSysTo125.xci"\
-]
-set imported_files ""
-foreach f $files {
-  lappend imported_files [import_files -fileset sources_1 $f]
-}
-
 # Set 'sources_1' fileset file properties for remote files
-set file "$origin_dir/PciVnaEmul_Repo/src/PciE/pci_exp_expect_tasks.vh"
+set file "$origin_dir/PciVnaEmul_REPO/src/PciE/board_common.vh"
 set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property -name "file_type" -value "Verilog Header" -objects $file_obj
 
-set file "$origin_dir/PciVnaEmul_Repo/src/PciE/pipe_interconnect.vh"
+set file "$origin_dir/PciVnaEmul_REPO/src/PciE/pci_exp_expect_tasks.vh"
 set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property -name "file_type" -value "Verilog Header" -objects $file_obj
 
-set file "$origin_dir/PciVnaEmul_Repo/src/PciE/sample_tests1.vh"
+set file "$origin_dir/PciVnaEmul_REPO/src/PciE/tests.vh"
 set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property -name "file_type" -value "Verilog Header" -objects $file_obj
 
-set file "$origin_dir/PciVnaEmul_Repo/src/PciE/board_common.vh"
+set file "$origin_dir/PciVnaEmul_REPO/src/PciE/sample_tests1.vh"
 set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property -name "file_type" -value "Verilog Header" -objects $file_obj
 
-set file "$origin_dir/PciVnaEmul_Repo/src/PciE/tests.vh"
+set file "$origin_dir/PciVnaEmul_REPO/src/PciE/pipe_interconnect.vh"
 set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property -name "file_type" -value "Verilog Header" -objects $file_obj
 
 
+# Set 'sources_1' fileset file properties for local files
+# None
+
+# Set 'sources_1' fileset properties
+set obj [get_filesets sources_1]
+set_property -name "dataflow_viewer_settings" -value "min_width=16" -objects $obj
+set_property -name "top" -value "PciVnaEmulTop" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/PciVnaEmul_PROJ/PciVnaEmul.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo.xci" ]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+
+# Set 'sources_1' fileset file properties for remote files
+# None
+
+# Set 'sources_1' fileset file properties for local files
+set file "MeasDataFifo/MeasDataFifo.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/PciVnaEmul_PROJ/PciVnaEmul.srcs/sources_1/ip/pcie1234/pcie1234.xci" ]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+
+# Set 'sources_1' fileset file properties for remote files
+# None
+
 # Set 'sources_1' fileset file properties for local files
 set file "pcie1234/pcie1234.xci"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
@@ -450,6 +469,19 @@ if { ![get_property "is_locked" $file_obj] } {
   set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
 }
 
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/PciVnaEmul_PROJ/PciVnaEmul.srcs/sources_1/ip/ClkPllSysTo125/ClkPllSysTo125.xci" ]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+
+# Set 'sources_1' fileset file properties for remote files
+# None
+
+# Set 'sources_1' fileset file properties for local files
 set file "ClkPllSysTo125/ClkPllSysTo125.xci"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
@@ -459,11 +491,26 @@ if { ![get_property "is_locked" $file_obj] } {
 }
 
 
-# Set 'sources_1' fileset properties
+# Set 'sources_1' fileset object
 set obj [get_filesets sources_1]
-set_property -name "dataflow_viewer_settings" -value "min_width=16" -objects $obj
-set_property -name "top" -value "PciVnaEmulTop" -objects $obj
-set_property -name "top_auto_set" -value "0" -objects $obj
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/PciVnaEmul_PROJ/PciVnaEmul.srcs/sources_1/ip/CdcFifo/CdcFifo.xci" ]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+
+# Set 'sources_1' fileset file properties for remote files
+# None
+
+# Set 'sources_1' fileset file properties for local files
+set file "CdcFifo/CdcFifo.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
 
 # Create 'constrs_1' fileset (if not found)
 if {[string equal [get_filesets -quiet constrs_1] ""]} {
@@ -474,16 +521,18 @@ if {[string equal [get_filesets -quiet constrs_1] ""]} {
 set obj [get_filesets constrs_1]
 
 # Add/Import constrs file and set constrs file properties
-set file "[file normalize "$origin_dir/PciVnaEmul_Repo/constr/xilinx_pcie_7x_ep_x1g1.xdc"]"
+set file "[file normalize "$origin_dir/PciVnaEmul_REPO/constr/xilinx_pcie_7x_ep_x1g1.xdc"]"
 set file_added [add_files -norecurse -fileset $obj [list $file]]
-set file "$origin_dir/PciVnaEmul_Repo/constr/xilinx_pcie_7x_ep_x1g1.xdc"
+set file "$origin_dir/PciVnaEmul_REPO/constr/xilinx_pcie_7x_ep_x1g1.xdc"
 set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
 set_property -name "file_type" -value "XDC" -objects $file_obj
 
 # Set 'constrs_1' fileset properties
 set obj [get_filesets constrs_1]
+set_property -name "target_constrs_file" -value "[file normalize "$origin_dir/PciVnaEmul_REPO/constr/xilinx_pcie_7x_ep_x1g1.xdc"]" -objects $obj
 set_property -name "target_part" -value "xc7a100tfgg484-2" -objects $obj
+set_property -name "target_ucf" -value "[file normalize "$origin_dir/PciVnaEmul_REPO/constr/xilinx_pcie_7x_ep_x1g1.xdc"]" -objects $obj
 
 # Create 'sim_1' fileset (if not found)
 if {[string equal [get_filesets -quiet sim_1] ""]} {
@@ -493,25 +542,91 @@ if {[string equal [get_filesets -quiet sim_1] ""]} {
 # Set 'sim_1' fileset object
 set obj [get_filesets sim_1]
 set files [list \
- [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/board.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/Sim/S5443TopSimpleMeasTb.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/EP_MEM.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/PIO.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/PIO_EP.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/PIO_EP_MEM_ACCESS.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/PIO_RX_ENGINE.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/PIO_TO_CTRL.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/PIO_TX_ENGINE.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/board_common.vh"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/pci_exp_usrapp_cfg.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/pci_exp_expect_tasks.vh"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/pci_exp_usrapp_com.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/pci_exp_usrapp_pl.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/pci_exp_usrapp_rx.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/tests.vh"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/sample_tests1.vh"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/pci_exp_usrapp_tx.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/pcie1234_pipe_clock.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/pcie1234_support.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/pcie_app_7x.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/pcie_axi_trn_bridge.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/sys_clk_gen.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/sys_clk_gen_ds.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/xilinx_pcie_2_1_ep_7x.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/xilinx_pcie_2_1_rport_7x.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/board.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_REPO/src/PciE/pipe_interconnect.vh"] \
 ]
 add_files -norecurse -fileset $obj $files
 
 # Set 'sim_1' fileset file properties for remote files
-# None
+set file "$origin_dir/PciVnaEmul_REPO/src/PciE/board_common.vh"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog Header" -objects $file_obj
+
+set file "$origin_dir/PciVnaEmul_REPO/src/PciE/pci_exp_expect_tasks.vh"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog Header" -objects $file_obj
+
+set file "$origin_dir/PciVnaEmul_REPO/src/PciE/tests.vh"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog Header" -objects $file_obj
+
+set file "$origin_dir/PciVnaEmul_REPO/src/PciE/sample_tests1.vh"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog Header" -objects $file_obj
+
+set file "$origin_dir/PciVnaEmul_REPO/src/PciE/pipe_interconnect.vh"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog Header" -objects $file_obj
+
 
 # Set 'sim_1' fileset file properties for local files
 # None
 
 # Set 'sim_1' fileset properties
 set obj [get_filesets sim_1]
-set_property -name "top" -value "board" -objects $obj
+set_property -name "top" -value "S5443TopSimpleMeasTb" -objects $obj
 set_property -name "top_auto_set" -value "0" -objects $obj
 set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
 
 # Set 'utils_1' fileset object
 set obj [get_filesets utils_1]
-# Empty (no sources present)
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/PciVnaEmul_PROJ/PciVnaEmul.srcs/utils_1/imports/synth_1/PciVnaEmulTop.dcp" ]\
+]
+set imported_files ""
+foreach f $files {
+  lappend imported_files [import_files -fileset utils_1 $f]
+}
+
+# Set 'utils_1' fileset file properties for remote files
+# None
+
+# Set 'utils_1' fileset file properties for local files
+set file "synth_1/PciVnaEmulTop.dcp"
+set file_obj [get_files -of_objects [get_filesets utils_1] [list "*$file"]]
+set_property -name "netlist_only" -value "0" -objects $file_obj
+
 
 # Set 'utils_1' fileset properties
 set obj [get_filesets utils_1]
@@ -524,10 +639,10 @@ catch {
 
 # Create 'synth_1' run (if not found)
 if {[string equal [get_runs -quiet synth_1] ""]} {
-    create_run -name synth_1 -part xc7a100tfgg484-2 -flow {Vivado Synthesis 2020} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
+    create_run -name synth_1 -part xc7a100tfgg484-2 -flow {Vivado Synthesis 2024} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
 } else {
   set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
-  set_property flow "Vivado Synthesis 2020" [get_runs synth_1]
+  set_property flow "Vivado Synthesis 2024" [get_runs synth_1]
 }
 set obj [get_runs synth_1]
 set_property set_report_strategy_name 1 $obj
@@ -543,21 +658,19 @@ if { $obj != "" } {
 }
 set obj [get_runs synth_1]
 set_property -name "part" -value "xc7a100tfgg484-2" -objects $obj
+set_property -name "incremental_checkpoint" -value "$proj_dir/${_xil_proj_name_}.srcs/utils_1/imports/synth_1/PciVnaEmulTop.dcp" -objects $obj
 set_property -name "auto_incremental_checkpoint" -value "1" -objects $obj
 set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
-set_property -name "steps.synth_design.args.flatten_hierarchy" -value "none" -objects $obj
-set_property -name "steps.synth_design.args.gated_clock_conversion" -value "auto" -objects $obj
-set_property -name "steps.synth_design.args.incremental_mode" -value "aggressive" -objects $obj
 
 # set the current synth run
 current_run -synthesis [get_runs synth_1]
 
 # Create 'impl_1' run (if not found)
 if {[string equal [get_runs -quiet impl_1] ""]} {
-    create_run -name impl_1 -part xc7a100tfgg484-2 -flow {Vivado Implementation 2020} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
+    create_run -name impl_1 -part xc7a100tfgg484-2 -flow {Vivado Implementation 2024} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
 } else {
   set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
-  set_property flow "Vivado Implementation 2020" [get_runs impl_1]
+  set_property flow "Vivado Implementation 2024" [get_runs impl_1]
 }
 set obj [get_runs impl_1]
 set_property set_report_strategy_name 1 $obj
@@ -571,6 +684,7 @@ set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_tim
 if { $obj != "" } {
 set_property -name "is_enabled" -value "0" -objects $obj
 set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
 
 }
 # Create 'impl_1_opt_report_drc_0' report (if not found)
@@ -589,6 +703,7 @@ set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timi
 if { $obj != "" } {
 set_property -name "is_enabled" -value "0" -objects $obj
 set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
 
 }
 # Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
@@ -599,6 +714,7 @@ set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_repor
 if { $obj != "" } {
 set_property -name "is_enabled" -value "0" -objects $obj
 set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
 
 }
 # Create 'impl_1_place_report_io_0' report (if not found)
@@ -652,6 +768,7 @@ set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_ti
 if { $obj != "" } {
 set_property -name "is_enabled" -value "0" -objects $obj
 set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
 
 }
 # Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
@@ -662,6 +779,7 @@ set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_powe
 if { $obj != "" } {
 set_property -name "is_enabled" -value "0" -objects $obj
 set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
 
 }
 # Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
@@ -672,6 +790,7 @@ set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report
 if { $obj != "" } {
 set_property -name "is_enabled" -value "0" -objects $obj
 set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
 
 }
 # Create 'impl_1_route_report_drc_0' report (if not found)
@@ -713,6 +832,7 @@ if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_rou
 set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
 if { $obj != "" } {
 set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
 
 }
 # Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
@@ -747,6 +867,7 @@ if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_pos
 set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
 if { $obj != "" } {
 set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
 set_property -name "options.warn_on_violation" -value "1" -objects $obj
 
 }
@@ -762,7 +883,6 @@ set_property -name "options.warn_on_violation" -value "1" -objects $obj
 set obj [get_runs impl_1]
 set_property -name "part" -value "xc7a100tfgg484-2" -objects $obj
 set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
-set_property -name "steps.write_bitstream.args.bin_file" -value "1" -objects $obj
 set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
 set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
 

src/PciE/PIO.v

@@ -72,6 +72,7 @@ module PIO #(
   parameter TCQ        = 1
 )(
   input                         user_clk,
+  input                         clk_50,
   input                         user_reset,
   input                         user_lnk_up,
 
@@ -97,7 +98,7 @@ module PIO #(
 
   input [15:0]                  cfg_completer_id,
 
-  input   [63:0] MeasData_i,
+  input   [32*9-1:0] MeasData_i,
   input   MeasEnd_i,
 
   output  StartMeasCmd_o
@@ -129,6 +130,7 @@ module PIO #(
   ) PIO_EP_inst (
 
     .clk( user_clk ),                             // I
+    .clk_50( clk_50 ),                             // I
     .rst_n( pio_reset_n ),                        // I
 
     .s_axis_tx_tready( s_axis_tx_tready ),        // I

src/PciE/PIO_EP.v

@@ -68,6 +68,7 @@ module PIO_EP #(
 ) (
 
   input                         clk,
+  input                         clk_50,
   input                         rst_n,
 
   // AXIS TX
@@ -91,7 +92,7 @@ module PIO_EP #(
 
   input   [15:0]                cfg_completer_id,
 
-  input   [63:0] MeasData_i,
+  input   [32*9-1:0] MeasData_i,
   input   MeasEnd_i,
 
   output  StartMeasCmd_o
@@ -203,7 +204,8 @@ module PIO_EP #(
 
   IntermediateLogic IntermediateLogic 
   (
-  .Clk_i(clk),
+  .Clk100_i(clk),
+  .Clk50_i(clk_50),
   .Rst_i(~rst_n),
 
   .MeasEnd_i(MeasEnd_i),

src/PciE/pcie_app_7x.v

@@ -72,6 +72,7 @@ module  pcie_app_7x#(
 )(
 
   input                         user_clk,
+  input                         clk_50,
   input                         user_reset,
   input                         user_lnk_up,
 
@@ -145,7 +146,7 @@ module  pcie_app_7x#(
   output                        cfg_interrupt_stat,
   output  [4:0]                 cfg_pciecap_interrupt_msgnum,
 
-  input   [63:0] MeasData_i,
+  input   [32*9-1:0] MeasData_i,
   input   MeasEnd_i,
 
   output  StartMeasCmd_o
@@ -234,6 +235,7 @@ module  pcie_app_7x#(
   ) PIO (
 
     .user_clk ( user_clk ),                         // I
+    .clk_50 ( clk_50 ),                         // I
     .user_reset ( user_reset ),                     // I
     .user_lnk_up ( user_lnk_up ),                   // I
 

src/PciE/xilinx_pcie_2_1_ep_7x.v

@@ -80,7 +80,7 @@ module xilinx_pcie_2_1_ep_7x # (
 
   output Clk_o,
 
-  input   [63:0] MeasData_i,
+  input   [32*9-1:0] MeasData_i,
   input   MeasEnd_i,
 
   output  StartMeasCmd_o,
@@ -493,6 +493,7 @@ pcie_app_7x  #(
 
   // Common
   .user_clk                       ( user_clk ),
+  .clk_50                         (ClkUser3_o),
   .user_reset                     ( user_reset_q ),
   .user_lnk_up                    ( user_lnk_up_q ),
 

src/Sim/S5443TopSimpleMeasTb.v

@@ -311,21 +311,44 @@ end
 
 wire [31:0] dataToCfgReg = (tb_cnt == 10)? 32'h1:32'h0;
 wire valToCfgReg = (tb_cnt==10)? 1'b1:1'b0;
+wire [32*9-1:0] measData;
+
+reg [5:0] rdReqCnt;
+
+always @(posedge Clk100) begin
+	if (rst) begin
+		rdReqCnt <= 0;
+	end else begin
+		if (tb_cnt > 300 && tb_cnt <= 410) begin
+			if (rdReqCnt <= 10) begin
+				rdReqCnt <= rdReqCnt +1;
+			end else begin
+				rdReqCnt <= 0;
+			end
+		end else begin
+			rdReqCnt <= 0;
+		end
+	end
+end
+
+wire readReq = (rdReqCnt==10);
+wire valToMeasData = (rdReqCnt == 10);
 
 IntermediateLogic IntermediateLogic 
 (
-  	.Clk_i(Clk100),
+  	.Clk100_i(Clk100),
+  	.Clk50_i(Clk50),
   	.Rst_i(rst),
 	
   	.MeasEnd_i(endMeas),
 	
-  	.ReadReq_i(1'b0),
+  	.ReadReq_i(readReq),
 	
   	.ValToCfgReg_i(valToCfgReg),
   	.CfgData_i(dataToCfgReg),
  	
-  	.ValToMeasData_i(),
-  	.MeasData_i(),
+  	.ValToMeasData_i(valToMeasData),
+  	.MeasData_i(measData),
   	
   	.StartMeasCmd_o(StartMeasCmd_o),
   	.Data_o()
@@ -402,7 +425,8 @@ S5443Top MasterFpga
 	//gain lines
 	.DspReadyForRx_i		(),
 	.DspReadyForRxToFpgaS_o	(),
-	.AmpEn_o				()	//	0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
+	.AmpEn_o				(),	//	0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
+	.MeasData_o 			(measData)
 );
 
 parameter	IDLE	=	2'h0;

src/Top/IntermediateLogic.v

@@ -22,7 +22,8 @@
 
 module IntermediateLogic 
 (
-input Clk_i,
+input Clk100_i,
+input Clk50_i,
 input Rst_i,
 
 input MeasEnd_i,
@@ -33,7 +34,7 @@ input ValToCfgReg_i,
 input [31:0] CfgData_i,
 
 input ValToMeasData_i,
-input [32*2-1:0] MeasData_i,
+input [32*9-1:0] MeasData_i,
 
 output reg StartMeasCmd_o,
 
@@ -41,9 +42,9 @@ output [31:0] Data_o
 );
 
 reg [31:0] cfgReg;
-reg [63:0] measDataR;
+wire [32*9-1:0] measDataR;
 reg [31:0] dataOut;
-reg [1:0] measDwCnt;
+reg [3:0] measDwCnt;
 
 reg measEndR;
 reg measEndRR;
@@ -54,13 +55,12 @@ wire valToCfgPos;
 reg valToMeasDataR;
 wire valToMeasDataPos;
 
-
 assign Data_o = dataOut;
 
 assign valToCfgPos = (ValToCfgReg_i&!valToCfgRegR);
 assign valToMeasDataPos = (ValToMeasData_i&!valToMeasDataR);
 
-always @(posedge Clk_i or posedge Rst_i) begin
+always @(posedge Clk100_i or posedge Rst_i) begin
 	if (Rst_i) begin
 		StartMeasCmd_o <= 0;
 		valToCfgRegR <= 0;
@@ -72,7 +72,7 @@ always @(posedge Clk_i or posedge Rst_i) begin
 	end
 end
 
-always @(posedge Clk_i or posedge Rst_i) begin
+always @(posedge Clk100_i or posedge Rst_i) begin
 	if (Rst_i) begin
 		measEndR <= 0;
 		measEndRR <= 0;
@@ -82,7 +82,7 @@ always @(posedge Clk_i or posedge Rst_i) begin
 	end
 end
 
-always @(posedge Clk_i or posedge Rst_i) begin
+always @(posedge Clk100_i or posedge Rst_i) begin
 	if (Rst_i) begin
 		cfgReg <= 0;
 	end else begin
@@ -96,37 +96,27 @@ always @(posedge Clk_i or posedge Rst_i) begin
 	end
 end
 
-always @(posedge Clk_i or posedge Rst_i) begin
+always @(posedge Clk100_i or posedge Rst_i) begin
 	if (Rst_i) begin
-		measDwCnt <= 1;
+		measDwCnt <= 0;
 	end else begin
-		if (ReadReq_i) begin
-			if (measDwCnt!=2'd2) begin
+		if (ReadReq_i&ValToMeasData_i) begin
+			if (measDwCnt!=4'd8) begin
 				measDwCnt <= 	measDwCnt+1;
 			end else begin
-				measDwCnt <= 1;
+				measDwCnt <= 0;
 			end
 		end
 	end
 end
 
-always @(posedge Clk_i or posedge Rst_i) begin
-	if (Rst_i) begin
-		measDataR <= 0;
-	end else begin
-		if (measEndRR) begin
-			measDataR <= MeasData_i;
-		end 
-	end
-end
-
-always @(posedge Clk_i or posedge Rst_i) begin
+always @(posedge Clk100_i or posedge Rst_i) begin
 	if (Rst_i) begin
 		dataOut <= 0;
 	end else begin
 		if (ReadReq_i) begin
 			if (ValToMeasData_i) begin
-				dataOut <= measDataR[measDwCnt*32-1-:32];
+				dataOut <= measDataR[measDwCnt*32+:32];
 			end else if (ValToCfgReg_i) begin
 				dataOut <= cfgReg;
 			end 
@@ -134,4 +124,68 @@ always @(posedge Clk_i or posedge Rst_i) begin
 	end
 end
 
+
+//====================================================================
+// fifo logic
+
+wire fifoFull;
+wire fifoEmpty;
+reg wrEn;
+reg rdEn;
+
+always @(posedge Clk100_i)	begin
+	if (Rst_i) begin
+		wrEn <= 1'b0;
+	end else begin
+		if (!fifoFull) begin
+			if (measEndRR) begin
+				wrEn <= 1'b1;
+			end	else	begin
+				wrEn <= 1'b0;
+			end	
+		end else begin
+			wrEn <= 1'b0;
+		end
+	end
+end
+
+always @(posedge Clk100_i) begin
+	if	(Rst_i) begin
+		rdEn <=	1'b0;
+	end else begin
+		if (!fifoEmpty) begin
+			rdEn <= 1'b1;
+		end	else	begin
+			rdEn <= 1'b0;
+		end
+	end
+end
+
+// CdcFifo CdcFifo 
+// (
+// 	.rst(Rst_i),                  // input wire rst
+// 	.wr_clk(Clk50_i),            // input wire wr_clk
+// 	.rd_clk(Clk100_i),            // input wire rd_clk
+// 	.din(MeasData_i),                  // input wire [287 : 0] din
+// 	.wr_en(wrEn),              // input wire wr_en
+// 	.rd_en(rdEn),              // input wire rd_en
+// 	.dout(measDataR),                // output wire [287 : 0] dout
+// 	.full(fifoFull),                // output wire full
+// 	.empty(fifoEmpty),              // output wire empty
+// 	.wr_rst_busy(),  // output wire wr_rst_busy
+// 	.rd_rst_busy()  // output wire rd_rst_busy
+// );
+
+MeasDataFifo MeasDataFifo
+(
+	.clk	(Clk100_i),
+	.srst	(Rst_i),
+	.din	(MeasData_i),
+	.wr_en	(wrEn),
+	.rd_en	(rdEn),
+	.dout	(measDataR),
+	.full	(fifoFull),
+	.empty	(fifoEmpty)
+);
+
 endmodule

src/Top/PciVnaEmulTop.v

@@ -33,7 +33,7 @@ module PciVnaEmulTop
 );
 
 
-wire [63:0] measData;
+wire [32*9-1:0] measData;
 wire clk;
 wire endMeas;
 wire startMeasCmd;

src/Top/S5443Top.v

@@ -144,7 +144,7 @@ module	S5443Top
 	output	StartMeasDsp_o,
 	output	[ChNum-1:0]	AmpEn_o,	//	0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
 	
-	output  [ResultWidth*2-1:0] MeasData_o
+	output  [ResultWidth*9-1:0] MeasData_o
 );
 //================================================================================
 //  reg/wire
@@ -402,6 +402,15 @@ module	S5443Top
 	reg		dspReadyForRxRegRR;
 	
 	wire	sampleStrobeGenRst;
+
+	wire	[7:0]	ampEnT1	=	{{7{1'b0}},ampEnNewStates[0]};
+	wire	[7:0]	ampEnR1	=	{{7{1'b0}},ampEnNewStates[1]};
+	wire	[7:0]	ampEnR2	=	{{7{1'b0}},ampEnNewStates[2]};
+	wire	[7:0]	ampEnT2	=	{{7{1'b0}},ampEnNewStates[3]};
+
+	wire	[31:0]	serviceData	=	{ampEnR2,ampEnT2,ampEnR1,ampEnT1};
+	wire	[ResultWidth*(ChNum*2+1)-1:0]	measDataBus;
+
 //================================================================================
 //  assignments
 //================================================================================	
@@ -526,7 +535,8 @@ module	S5443Top
 	
 	assign	StartMeasEvent_o	=	startMeasEvent;
 	
-	assign	EndMeas_o	=	stopMeas|stopMeasR; //stretching pulse for 1 more clk period
+	assign	EndMeas_o	=	measDataRdy; //stretching pulse for 1 more clk period
+	// assign	EndMeas_o	=	stopMeas|stopMeasR; //stretching pulse for 1 more clk period
 	
 	assign	gainLowThresholdBus		[ChNum-4]	=	gainLowThreshT1;
 	assign	gainLowThresholdBus		[ChNum-3]	=	gainLowThreshR1;
@@ -563,13 +573,25 @@ module	S5443Top
 	assign	Trig6to1_io	[3]	=	(measCtrl[19])	?	1'bz:extPortsMuxedOut[3];	//1 - in, 0 - out
 	assign	Trig6to1_io	[4]	=	(measCtrl[20])	?	1'bz:extPortsMuxedOut[4];	//1 - in, 0 - out
 	assign	Trig6to1_io	[5]	=	(measCtrl[21])	?	1'bz:extPortsMuxedOut[5];	//1 - in, 0 - out
+
+	assign	measDataBus	[(ResultWidth-1)-:ResultWidth]		=	adc1ImT1;
+	assign	measDataBus	[(ResultWidth*2)-1-:ResultWidth]	=	adc1ReT1;
+	assign	measDataBus	[(ResultWidth*3)-1-:ResultWidth]	=	adc1ImR1;
+	assign	measDataBus	[(ResultWidth*4)-1-:ResultWidth]	=	adc1ReR1;
+	assign	measDataBus	[(ResultWidth*5)-1-:ResultWidth]	=	adc2ImT2;
+	assign	measDataBus	[(ResultWidth*6)-1-:ResultWidth]	=	adc2ReT2;
+	assign	measDataBus	[(ResultWidth*7)-1-:ResultWidth]	=	adc2ImR2;
+	assign	measDataBus	[(ResultWidth*8)-1-:ResultWidth]	=	adc2ReR2;
+	assign	measDataBus	[(ResultWidth*9)-1-:ResultWidth]	=	serviceData;
 	
 	assign	DspReadyForRxToFpgaS_o	=	dspReadyForRxRegR;
 	assign	StartMeasDsp_o	=	startMeasSyncR;
 
 	assign TimersClk_o = 0;
 
-	assign MeasData_o = {adc1ImT1,adc1ReT1};
+	assign MeasData_o = measDataBus;
+
+
 //================================================================================
 //  CODING
 //================================================================================