Test cganges

recreate.tcl

@@ -3,7 +3,7 @@
 #
 # recreate.tcl: Tcl script for re-creating project 'pcie1234_ex'
 #
-# Generated by Vivado on Wed Oct 09 12:07:02 +0300 2024
+# Generated by Vivado on Wed Oct 09 12:53:56 +0300 2024
 # IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
 #
 # This file contains the Vivado Tcl commands for re-creating the project to the state*
@@ -23,93 +23,87 @@
 # 2. The following source(s) files that were local or imported into the original project.
 #    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
 #
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/PulseMeas/ActivePortSelector.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/AdcCalibration.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/ComplPrng.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/CordicNco.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/CordicRotation.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/DitherGen/DitherGenv2.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/DspPipeline.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/EP_MEM.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Math/FpCustomMultiplier.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/GainOverloadControl/GainControl.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/GainOverloadControl/GainControlWrapper.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InitRst/InitRst.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Top/IntermediateLogic.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/InternalDsp.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/MeasCtrlModule.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/PulseMeas/MeasStartEventGen.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Math/MultModule.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/PulseMeas/Mux.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Math/MyIntToFp.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/NcoRstGen.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/GainOverloadControl/OverloadDetect.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/PulseMeas/PGenRstGenerator.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/PIO.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/PIO_EP.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/PIO_EP_MEM_ACCESS.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/PIO_RX_ENGINE.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/PIO_TO_CTRL.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/PIO_TX_ENGINE.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/PulseMeas/PulseGen.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/RegMap/RegMap.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Top/S5443Top.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/PulseMeas/SampleStrobeGenRstDemux.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Math/SimpleMult.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/PulseMeas/StartAfterGainSel.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Math/SumAcc.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/PulseMeas/TrigInt2Mux.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/WinParameters.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/Win_calc.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/pcie1234_pipe_clock.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/pcie1234_support.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/pcie_app_7x.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/xilinx_pcie_2_1_ep_7x.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Top/PciVnaEmulTop.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/PulseMeas/PulseGenNew.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/ClkGen/Clk200Gen.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/ExtDspInterface/DspInterface.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/ExtDspInterface/DspPpiOut.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/MeasDataFifo/FifoController.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/MeasDataFifo/MeasDataFifoWrapper.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/ExtDspInterface/SlaveSpi.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/hierarchy.txt"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/AdcDataRx/AdcDataInterface.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/AdcDataRx/n_x_serdes_1_to_7_mmcm_idelay_sdr.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/AdcDataRx/serdes_1_to_7_slave_idelay_sdr.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/AdcDataRx/serdes_1_to_7_mmcm_idelay_sdr.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/AdcDataRx/top5x2_7to1_sdr_rx.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/AdcDataRx/AdcSync.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/AdcDataRx/delay_controller_wrap.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Top/IntermediateLogicTb.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Sim/S5443TopPulseProfileTb.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Sim/S5443TopSimpleMeasTb.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/ip/ClkPllSysTo125/ClkPllSysTo125.xci"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/ip/pcie1234/pcie1234.xci"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/xilinx_pcie_7x_ep_x1g1.xdc"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/board_common.vh"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/pci_exp_usrapp_cfg.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/pci_exp_expect_tasks.vh"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/pci_exp_usrapp_com.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/pci_exp_usrapp_pl.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/pci_exp_usrapp_rx.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/tests.vh"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/sample_tests1.vh"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/pci_exp_usrapp_tx.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/pcie1234_gt_top_pipe_mode.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/pcie_2_1_rport_7x.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/pcie_axi_trn_bridge.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/sys_clk_gen.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/sys_clk_gen_ds.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/xilinx_pcie_2_1_rport_7x.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/board.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/pipe_interconnect.vh"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/imports/xil_sig2pipe.v"
-#    "C:/Users/Work_Pc/Music/pcie1234_ex/board_behav.wcfg"
+#    "D:/testPci/pcie1234_ex/pcie1234_ex.srcs/sources_1/ip/pcie1234/pcie1234.xci"
+#    "D:/testPci/pcie1234_ex/pcie1234_ex.srcs/sources_1/ip/ClkPllSysTo125/ClkPllSysTo125.xci"
 #
 # 3. The following remote source files that were added to the original project:-
 #
-#    <none>
+#    "C:/PciVnaEmul_Repo/src/PulseMeas/ActivePortSelector.v"
+#    "C:/PciVnaEmul_Repo/src/InternalDsp/AdcCalibration.v"
+#    "C:/PciVnaEmul_Repo/src/InternalDsp/ComplPrng.v"
+#    "C:/PciVnaEmul_Repo/src/InternalDsp/CordicNco.v"
+#    "C:/PciVnaEmul_Repo/src/InternalDsp/CordicRotation.v"
+#    "C:/PciVnaEmul_Repo/src/DitherGen/DitherGenv2.v"
+#    "C:/PciVnaEmul_Repo/src/InternalDsp/DspPipeline.v"
+#    "C:/PciVnaEmul_Repo/src/PciE/EP_MEM.v"
+#    "C:/PciVnaEmul_Repo/src/Math/FpCustomMultiplier.v"
+#    "C:/PciVnaEmul_Repo/src/GainOverloadControl/GainControl.v"
+#    "C:/PciVnaEmul_Repo/src/GainOverloadControl/GainControlWrapper.v"
+#    "C:/PciVnaEmul_Repo/src/InitRst/InitRst.v"
+#    "C:/PciVnaEmul_Repo/src/Top/IntermediateLogic.v"
+#    "C:/PciVnaEmul_Repo/src/InternalDsp/InternalDsp.v"
+#    "C:/PciVnaEmul_Repo/src/InternalDsp/MeasCtrlModule.v"
+#    "C:/PciVnaEmul_Repo/src/PulseMeas/MeasStartEventGen.v"
+#    "C:/PciVnaEmul_Repo/src/Math/MultModule.v"
+#    "C:/PciVnaEmul_Repo/src/PulseMeas/Mux.v"
+#    "C:/PciVnaEmul_Repo/src/Math/MyIntToFp.v"
+#    "C:/PciVnaEmul_Repo/src/InternalDsp/NcoRstGen.v"
+#    "C:/PciVnaEmul_Repo/src/GainOverloadControl/OverloadDetect.v"
+#    "C:/PciVnaEmul_Repo/src/PulseMeas/PGenRstGenerator.v"
+#    "C:/PciVnaEmul_Repo/src/PciE/PIO.v"
+#    "C:/PciVnaEmul_Repo/src/PciE/PIO_EP.v"
+#    "C:/PciVnaEmul_Repo/src/PciE/PIO_EP_MEM_ACCESS.v"
+#    "C:/PciVnaEmul_Repo/src/PciE/PIO_RX_ENGINE.v"
+#    "C:/PciVnaEmul_Repo/src/PciE/PIO_TO_CTRL.v"
+#    "C:/PciVnaEmul_Repo/src/PciE/PIO_TX_ENGINE.v"
+#    "C:/PciVnaEmul_Repo/src/PulseMeas/PulseGen.v"
+#    "C:/PciVnaEmul_Repo/src/RegMap/RegMap.v"
+#    "C:/PciVnaEmul_Repo/src/Top/S5443Top.v"
+#    "C:/PciVnaEmul_Repo/src/PulseMeas/SampleStrobeGenRstDemux.v"
+#    "C:/PciVnaEmul_Repo/src/Math/SimpleMult.v"
+#    "C:/PciVnaEmul_Repo/src/PulseMeas/StartAfterGainSel.v"
+#    "C:/PciVnaEmul_Repo/src/Math/SumAcc.v"
+#    "C:/PciVnaEmul_Repo/src/PulseMeas/TrigInt2Mux.v"
+#    "C:/PciVnaEmul_Repo/src/InternalDsp/WinParameters.v"
+#    "C:/PciVnaEmul_Repo/src/InternalDsp/Win_calc.v"
+#    "C:/PciVnaEmul_Repo/src/PciE/pcie1234_pipe_clock.v"
+#    "C:/PciVnaEmul_Repo/src/PciE/pcie1234_support.v"
+#    "C:/PciVnaEmul_Repo/src/PciE/pcie_app_7x.v"
+#    "C:/PciVnaEmul_Repo/src/PciE/xilinx_pcie_2_1_ep_7x.v"
+#    "C:/PciVnaEmul_Repo/src/Top/PciVnaEmulTop.v"
+#    "C:/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_pl.v"
+#    "C:/PciVnaEmul_Repo/src/ClkGen/Clk200Gen.v"
+#    "C:/PciVnaEmul_Repo/src/ExtDspInterface/DspPpiOut.v"
+#    "C:/PciVnaEmul_Repo/src/PciE/pci_exp_expect_tasks.vh"
+#    "C:/PciVnaEmul_Repo/src/PciE/sys_clk_gen.v"
+#    "C:/PciVnaEmul_Repo/src/AdcDataRx/delay_controller_wrap.v"
+#    "C:/PciVnaEmul_Repo/src/PciE/xilinx_pcie_2_1_rport_7x.v"
+#    "C:/PciVnaEmul_Repo/src/AdcDataRx/n_x_serdes_1_to_7_mmcm_idelay_sdr.v"
+#    "C:/PciVnaEmul_Repo/src/AdcDataRx/serdes_1_to_7_mmcm_idelay_sdr.v"
+#    "C:/PciVnaEmul_Repo/src/PciE/pcie1234_gt_top_pipe_mode.v"
+#    "C:/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_cfg.v"
+#    "C:/PciVnaEmul_Repo/src/AdcDataRx/AdcDataInterface.v"
+#    "C:/PciVnaEmul_Repo/src/MeasDataFifo/FifoController.v"
+#    "C:/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_tx.v"
+#    "C:/PciVnaEmul_Repo/src/AdcDataRx/AdcSync.v"
+#    "C:/PciVnaEmul_Repo/src/ExtDspInterface/DspInterface.v"
+#    "C:/PciVnaEmul_Repo/src/AdcDataRx/serdes_1_to_7_slave_idelay_sdr.v"
+#    "C:/PciVnaEmul_Repo/src/PciE/pipe_interconnect.vh"
+#    "C:/PciVnaEmul_Repo/src/ExtDspInterface/SlaveSpi.v"
+#    "C:/PciVnaEmul_Repo/src/PciE/xil_sig2pipe.v"
+#    "C:/PciVnaEmul_Repo/src/MeasDataFifo/MeasDataFifoWrapper.v"
+#    "C:/PciVnaEmul_Repo/src/PulseMeas/PulseGenNew.v"
+#    "C:/PciVnaEmul_Repo/src/PciE/sample_tests1.vh"
+#    "C:/PciVnaEmul_Repo/src/PciE/board_common.vh"
+#    "C:/PciVnaEmul_Repo/src/PciE/pcie_axi_trn_bridge.v"
+#    "C:/PciVnaEmul_Repo/src/AdcDataRx/top5x2_7to1_sdr_rx.v"
+#    "C:/PciVnaEmul_Repo/src/PciE/pcie_2_1_rport_7x.v"
+#    "C:/PciVnaEmul_Repo/src/PciE/sys_clk_gen_ds.v"
+#    "C:/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_rx.v"
+#    "C:/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_com.v"
+#    "C:/PciVnaEmul_Repo/src/PciE/tests.vh"
+#    "C:/PciVnaEmul_Repo/constr/xilinx_pcie_7x_ep_x1g1.xdc"
+#    "C:/PciVnaEmul_Repo/src/PciE/board.v"
 #
 #*****************************************************************************************
 
@@ -117,89 +111,8 @@
 proc checkRequiredFiles { origin_dir} {
   set status true
   set files [list \
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/PulseMeas/ActivePortSelector.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/AdcCalibration.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/ComplPrng.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/CordicNco.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/CordicRotation.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/DitherGen/DitherGenv2.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/DspPipeline.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/EP_MEM.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Math/FpCustomMultiplier.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/GainOverloadControl/GainControl.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/GainOverloadControl/GainControlWrapper.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InitRst/InitRst.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Top/IntermediateLogic.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/InternalDsp.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/MeasCtrlModule.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/PulseMeas/MeasStartEventGen.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Math/MultModule.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/PulseMeas/Mux.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Math/MyIntToFp.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/NcoRstGen.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/GainOverloadControl/OverloadDetect.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/PulseMeas/PGenRstGenerator.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/PIO.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/PIO_EP.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/PIO_EP_MEM_ACCESS.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/PIO_RX_ENGINE.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/PIO_TO_CTRL.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/PIO_TX_ENGINE.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/PulseMeas/PulseGen.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/RegMap/RegMap.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Top/S5443Top.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/PulseMeas/SampleStrobeGenRstDemux.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Math/SimpleMult.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/PulseMeas/StartAfterGainSel.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Math/SumAcc.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/PulseMeas/TrigInt2Mux.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/WinParameters.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/Win_calc.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/pcie1234_pipe_clock.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/pcie1234_support.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/pcie_app_7x.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/xilinx_pcie_2_1_ep_7x.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Top/PciVnaEmulTop.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/PulseMeas/PulseGenNew.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/ClkGen/Clk200Gen.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/ExtDspInterface/DspInterface.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/ExtDspInterface/DspPpiOut.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/MeasDataFifo/FifoController.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/MeasDataFifo/MeasDataFifoWrapper.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/ExtDspInterface/SlaveSpi.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/hierarchy.txt"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/AdcDataRx/AdcDataInterface.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/AdcDataRx/n_x_serdes_1_to_7_mmcm_idelay_sdr.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/AdcDataRx/serdes_1_to_7_slave_idelay_sdr.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/AdcDataRx/serdes_1_to_7_mmcm_idelay_sdr.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/AdcDataRx/top5x2_7to1_sdr_rx.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/AdcDataRx/AdcSync.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/AdcDataRx/delay_controller_wrap.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Top/IntermediateLogicTb.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Sim/S5443TopPulseProfileTb.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Sim/S5443TopSimpleMeasTb.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/ip/ClkPllSysTo125/ClkPllSysTo125.xci"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/ip/pcie1234/pcie1234.xci"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/xilinx_pcie_7x_ep_x1g1.xdc"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/board_common.vh"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/pci_exp_usrapp_cfg.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/pci_exp_expect_tasks.vh"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/pci_exp_usrapp_com.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/pci_exp_usrapp_pl.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/pci_exp_usrapp_rx.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/tests.vh"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/sample_tests1.vh"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/pci_exp_usrapp_tx.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/pcie1234_gt_top_pipe_mode.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/pcie_2_1_rport_7x.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/pcie_axi_trn_bridge.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/sys_clk_gen.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/sys_clk_gen_ds.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/xilinx_pcie_2_1_rport_7x.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/board.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/pipe_interconnect.vh"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/xil_sig2pipe.v"]"\
- "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/board_behav.wcfg"]"\
+   "D:/testPci/pcie1234_ex/pcie1234_ex.srcs/sources_1/ip/pcie1234/pcie1234.xci" \
+   "D:/testPci/pcie1234_ex/pcie1234_ex.srcs/sources_1/ip/ClkPllSysTo125/ClkPllSysTo125.xci" \
   ]
   foreach ifile $files {
     if { ![file isfile $ifile] } {
@@ -208,6 +121,91 @@ proc checkRequiredFiles { origin_dir} {
     }
   }
 
+  set files [list \
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PulseMeas/ActivePortSelector.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/InternalDsp/AdcCalibration.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/InternalDsp/ComplPrng.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/InternalDsp/CordicNco.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/InternalDsp/CordicRotation.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/DitherGen/DitherGenv2.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/InternalDsp/DspPipeline.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/EP_MEM.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/Math/FpCustomMultiplier.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/GainOverloadControl/GainControl.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/GainOverloadControl/GainControlWrapper.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/InitRst/InitRst.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/Top/IntermediateLogic.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/InternalDsp/InternalDsp.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/InternalDsp/MeasCtrlModule.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PulseMeas/MeasStartEventGen.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/Math/MultModule.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PulseMeas/Mux.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/Math/MyIntToFp.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/InternalDsp/NcoRstGen.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/GainOverloadControl/OverloadDetect.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PulseMeas/PGenRstGenerator.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/PIO.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/PIO_EP.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/PIO_EP_MEM_ACCESS.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/PIO_RX_ENGINE.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/PIO_TO_CTRL.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/PIO_TX_ENGINE.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PulseMeas/PulseGen.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/RegMap/RegMap.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/Top/S5443Top.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PulseMeas/SampleStrobeGenRstDemux.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/Math/SimpleMult.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PulseMeas/StartAfterGainSel.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/Math/SumAcc.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PulseMeas/TrigInt2Mux.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/InternalDsp/WinParameters.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/InternalDsp/Win_calc.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/pcie1234_pipe_clock.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/pcie1234_support.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/pcie_app_7x.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/xilinx_pcie_2_1_ep_7x.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/Top/PciVnaEmulTop.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_pl.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/ClkGen/Clk200Gen.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/ExtDspInterface/DspPpiOut.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/pci_exp_expect_tasks.vh"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/sys_clk_gen.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/AdcDataRx/delay_controller_wrap.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/xilinx_pcie_2_1_rport_7x.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/AdcDataRx/n_x_serdes_1_to_7_mmcm_idelay_sdr.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/AdcDataRx/serdes_1_to_7_mmcm_idelay_sdr.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/pcie1234_gt_top_pipe_mode.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_cfg.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/AdcDataRx/AdcDataInterface.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/MeasDataFifo/FifoController.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_tx.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/AdcDataRx/AdcSync.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/ExtDspInterface/DspInterface.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/AdcDataRx/serdes_1_to_7_slave_idelay_sdr.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/pipe_interconnect.vh"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/ExtDspInterface/SlaveSpi.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/xil_sig2pipe.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/MeasDataFifo/MeasDataFifoWrapper.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PulseMeas/PulseGenNew.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/sample_tests1.vh"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/board_common.vh"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/pcie_axi_trn_bridge.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/AdcDataRx/top5x2_7to1_sdr_rx.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/pcie_2_1_rport_7x.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/sys_clk_gen_ds.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_rx.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_com.v"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/tests.vh"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/constr/xilinx_pcie_7x_ep_x1g1.xdc"]"\
+ "[file normalize "$origin_dir/PciVnaEmul_Repo/src/PciE/board.v"]"\
+  ]
+  foreach ifile $files {
+    if { ![file isfile $ifile] } {
+      puts " Could not find remote file $ifile "
+      set status false
+    }
+  }
+
   return $status
 }
 # Set the reference directory for source file relative paths (by default the value is script directory path)
@@ -275,7 +273,7 @@ if { $::argc > 0 } {
 }
 
 # Set the directory path for the original project from where this script was exported
-set orig_proj_dir "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex"]"
+set orig_proj_dir "D:/testPci/pcie1234_ex"
 
 # Check for paths and files needed for project creation
 set validate_required 0
@@ -303,11 +301,11 @@ set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
 set_property -name "enable_resource_estimation" -value "0" -objects $obj
 set_property -name "enable_vhdl_2008" -value "1" -objects $obj
 set_property -name "ip_cache_permissions" -value "read write" -objects $obj
-set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
+set_property -name "ip_output_repo" -value "D:/testPci/${_xil_proj_name_}/${_xil_proj_name_}.cache/ip" -objects $obj
 set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
 set_property -name "part" -value "xc7a100tfgg484-2" -objects $obj
 set_property -name "revised_directory_structure" -value "1" -objects $obj
-set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
+set_property -name "sim.central_dir" -value "D:/testPci/${_xil_proj_name_}/${_xil_proj_name_}.ip_user_files" -objects $obj
 set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
 set_property -name "simulator_language" -value "Mixed" -objects $obj
 set_property -name "sim_compile_state" -value "1" -objects $obj
@@ -328,69 +326,88 @@ if {[string equal [get_filesets -quiet sources_1] ""]} {
 
 # Set 'sources_1' fileset object
 set obj [get_filesets sources_1]
+set files [list \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PulseMeas/ActivePortSelector.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/InternalDsp/AdcCalibration.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/InternalDsp/ComplPrng.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/InternalDsp/CordicNco.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/InternalDsp/CordicRotation.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/DitherGen/DitherGenv2.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/InternalDsp/DspPipeline.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/EP_MEM.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/Math/FpCustomMultiplier.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/GainOverloadControl/GainControl.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/GainOverloadControl/GainControlWrapper.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/InitRst/InitRst.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/Top/IntermediateLogic.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/InternalDsp/InternalDsp.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/InternalDsp/MeasCtrlModule.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PulseMeas/MeasStartEventGen.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/Math/MultModule.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PulseMeas/Mux.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/Math/MyIntToFp.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/InternalDsp/NcoRstGen.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/GainOverloadControl/OverloadDetect.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PulseMeas/PGenRstGenerator.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/PIO.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/PIO_EP.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/PIO_EP_MEM_ACCESS.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/PIO_RX_ENGINE.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/PIO_TO_CTRL.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/PIO_TX_ENGINE.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PulseMeas/PulseGen.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/RegMap/RegMap.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/Top/S5443Top.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PulseMeas/SampleStrobeGenRstDemux.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/Math/SimpleMult.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PulseMeas/StartAfterGainSel.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/Math/SumAcc.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PulseMeas/TrigInt2Mux.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/InternalDsp/WinParameters.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/InternalDsp/Win_calc.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/pcie1234_pipe_clock.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/pcie1234_support.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/pcie_app_7x.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/xilinx_pcie_2_1_ep_7x.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/Top/PciVnaEmulTop.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_pl.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/ClkGen/Clk200Gen.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/ExtDspInterface/DspPpiOut.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/pci_exp_expect_tasks.vh"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/sys_clk_gen.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/AdcDataRx/delay_controller_wrap.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/xilinx_pcie_2_1_rport_7x.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/AdcDataRx/n_x_serdes_1_to_7_mmcm_idelay_sdr.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/AdcDataRx/serdes_1_to_7_mmcm_idelay_sdr.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/pcie1234_gt_top_pipe_mode.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_cfg.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/AdcDataRx/AdcDataInterface.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/MeasDataFifo/FifoController.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_tx.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/AdcDataRx/AdcSync.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/ExtDspInterface/DspInterface.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/AdcDataRx/serdes_1_to_7_slave_idelay_sdr.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/pipe_interconnect.vh"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/ExtDspInterface/SlaveSpi.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/xil_sig2pipe.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/MeasDataFifo/MeasDataFifoWrapper.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PulseMeas/PulseGenNew.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/sample_tests1.vh"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/board_common.vh"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/pcie_axi_trn_bridge.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/AdcDataRx/top5x2_7to1_sdr_rx.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/pcie_2_1_rport_7x.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/sys_clk_gen_ds.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_rx.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/pci_exp_usrapp_com.v"] \
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/tests.vh"] \
+]
+add_files -norecurse -fileset $obj $files
+
 # Import local files from the original project
 set files [list \
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/PulseMeas/ActivePortSelector.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/AdcCalibration.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/ComplPrng.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/CordicNco.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/CordicRotation.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/DitherGen/DitherGenv2.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/DspPipeline.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/EP_MEM.v" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Math/FpCustomMultiplier.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/GainOverloadControl/GainControl.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/GainOverloadControl/GainControlWrapper.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InitRst/InitRst.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Top/IntermediateLogic.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/InternalDsp.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/MeasCtrlModule.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/PulseMeas/MeasStartEventGen.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Math/MultModule.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/PulseMeas/Mux.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Math/MyIntToFp.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/NcoRstGen.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/GainOverloadControl/OverloadDetect.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/PulseMeas/PGenRstGenerator.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/PIO.v" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/PIO_EP.v" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/PIO_EP_MEM_ACCESS.v" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/PIO_RX_ENGINE.v" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/PIO_TO_CTRL.v" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/PIO_TX_ENGINE.v" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/PulseMeas/PulseGen.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/RegMap/RegMap.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Top/S5443Top.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/PulseMeas/SampleStrobeGenRstDemux.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Math/SimpleMult.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/PulseMeas/StartAfterGainSel.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Math/SumAcc.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/PulseMeas/TrigInt2Mux.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/WinParameters.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/InternalDsp/Win_calc.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/pcie1234_pipe_clock.v" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/pcie1234_support.v" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/pcie_app_7x.v" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/xilinx_pcie_2_1_ep_7x.v" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Top/PciVnaEmulTop.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/PulseMeas/PulseGenNew.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/ClkGen/Clk200Gen.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/ExtDspInterface/DspInterface.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/ExtDspInterface/DspPpiOut.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/MeasDataFifo/FifoController.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/MeasDataFifo/MeasDataFifoWrapper.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/ExtDspInterface/SlaveSpi.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/hierarchy.txt" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/AdcDataRx/AdcDataInterface.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/AdcDataRx/n_x_serdes_1_to_7_mmcm_idelay_sdr.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/AdcDataRx/serdes_1_to_7_slave_idelay_sdr.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/AdcDataRx/serdes_1_to_7_mmcm_idelay_sdr.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/AdcDataRx/top5x2_7to1_sdr_rx.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/AdcDataRx/AdcSync.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/AdcDataRx/delay_controller_wrap.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Top/IntermediateLogicTb.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Sim/S5443TopPulseProfileTb.v"]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/imports/src/Sim/S5443TopSimpleMeasTb.v"]\
+ "D:/testPci/pcie1234_ex/pcie1234_ex.srcs/sources_1/ip/pcie1234/pcie1234.xci"\
+ "D:/testPci/pcie1234_ex/pcie1234_ex.srcs/sources_1/ip/ClkPllSysTo125/ClkPllSysTo125.xci"\
 ]
 set imported_files ""
 foreach f $files {
@@ -398,44 +415,34 @@ foreach f $files {
 }
 
 # Set 'sources_1' fileset file properties for remote files
-# None
-
-# Set 'sources_1' fileset file properties for local files
-set file "Top/IntermediateLogicTb.v"
+set file "$origin_dir/PciVnaEmul_Repo/src/PciE/pci_exp_expect_tasks.vh"
+set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property -name "used_in" -value "implementation simulation" -objects $file_obj
-set_property -name "used_in_synthesis" -value "0" -objects $file_obj
+set_property -name "file_type" -value "Verilog Header" -objects $file_obj
 
-set file "Sim/S5443TopPulseProfileTb.v"
+set file "$origin_dir/PciVnaEmul_Repo/src/PciE/pipe_interconnect.vh"
+set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property -name "used_in" -value "implementation simulation" -objects $file_obj
-set_property -name "used_in_synthesis" -value "0" -objects $file_obj
+set_property -name "file_type" -value "Verilog Header" -objects $file_obj
 
-set file "Sim/S5443TopSimpleMeasTb.v"
+set file "$origin_dir/PciVnaEmul_Repo/src/PciE/sample_tests1.vh"
+set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property -name "used_in" -value "implementation simulation" -objects $file_obj
-set_property -name "used_in_synthesis" -value "0" -objects $file_obj
-
+set_property -name "file_type" -value "Verilog Header" -objects $file_obj
 
-# Set 'sources_1' fileset properties
-set obj [get_filesets sources_1]
-set_property -name "dataflow_viewer_settings" -value "min_width=16" -objects $obj
-set_property -name "top" -value "PciVnaEmulTop" -objects $obj
-set_property -name "top_auto_set" -value "0" -objects $obj
+set file "$origin_dir/PciVnaEmul_Repo/src/PciE/board_common.vh"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog Header" -objects $file_obj
 
-# Set 'sources_1' fileset object
-set obj [get_filesets sources_1]
-# Import local files from the original project
-set files [list \
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/ip/ClkPllSysTo125/ClkPllSysTo125.xci" ]\
-]
-set imported_files [import_files -fileset sources_1 $files]
+set file "$origin_dir/PciVnaEmul_Repo/src/PciE/tests.vh"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog Header" -objects $file_obj
 
-# Set 'sources_1' fileset file properties for remote files
-# None
 
 # Set 'sources_1' fileset file properties for local files
-set file "ClkPllSysTo125/ClkPllSysTo125.xci"
+set file "pcie1234/pcie1234.xci"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
 set_property -name "registered_with_manager" -value "1" -objects $file_obj
@@ -443,20 +450,7 @@ if { ![get_property "is_locked" $file_obj] } {
   set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
 }
 
-
-# Set 'sources_1' fileset object
-set obj [get_filesets sources_1]
-# Import local files from the original project
-set files [list \
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/pcie1234_ex.srcs/sources_1/ip/pcie1234/pcie1234.xci"]\
-]
-set imported_files [import_files -fileset sources_1 $files]
-
-# Set 'sources_1' fileset file properties for remote files
-# None
-
-# Set 'sources_1' fileset file properties for local files
-set file "pcie1234/pcie1234.xci"
+set file "ClkPllSysTo125/ClkPllSysTo125.xci"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
 set_property -name "registered_with_manager" -value "1" -objects $file_obj
@@ -465,6 +459,12 @@ if { ![get_property "is_locked" $file_obj] } {
 }
 
 
+# Set 'sources_1' fileset properties
+set obj [get_filesets sources_1]
+set_property -name "dataflow_viewer_settings" -value "min_width=16" -objects $obj
+set_property -name "top" -value "PciVnaEmulTop" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
 # Create 'constrs_1' fileset (if not found)
 if {[string equal [get_filesets -quiet constrs_1] ""]} {
   create_fileset -constrset constrs_1
@@ -474,17 +474,16 @@ if {[string equal [get_filesets -quiet constrs_1] ""]} {
 set obj [get_filesets constrs_1]
 
 # Add/Import constrs file and set constrs file properties
-set file "[file normalize "$origin_dir/Users/Work_Pc/Music/pcie1234_ex/imports/xilinx_pcie_7x_ep_x1g1.xdc"]"
-set file_imported [import_files -fileset constrs_1 [list $file]]
-set file "imports/xilinx_pcie_7x_ep_x1g1.xdc"
+set file "[file normalize "$origin_dir/PciVnaEmul_Repo/constr/xilinx_pcie_7x_ep_x1g1.xdc"]"
+set file_added [add_files -norecurse -fileset $obj [list $file]]
+set file "$origin_dir/PciVnaEmul_Repo/constr/xilinx_pcie_7x_ep_x1g1.xdc"
+set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
 set_property -name "file_type" -value "XDC" -objects $file_obj
 
 # Set 'constrs_1' fileset properties
 set obj [get_filesets constrs_1]
-set_property -name "target_constrs_file" -value "[get_files [list "*imports/xilinx_pcie_7x_ep_x1g1.xdc"]]" -objects $obj
 set_property -name "target_part" -value "xc7a100tfgg484-2" -objects $obj
-set_property -name "target_ucf" -value "[get_files [list "*imports/xilinx_pcie_7x_ep_x1g1.xdc"]]" -objects $obj
 
 # Create 'sim_1' fileset (if not found)
 if {[string equal [get_filesets -quiet sim_1] ""]} {
@@ -493,136 +492,20 @@ if {[string equal [get_filesets -quiet sim_1] ""]} {
 
 # Set 'sim_1' fileset object
 set obj [get_filesets sim_1]
-# Import local files from the original project
 set files [list \
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/board_common.vh" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/pci_exp_usrapp_cfg.v" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/pci_exp_expect_tasks.vh" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/pci_exp_usrapp_com.v" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/pci_exp_usrapp_pl.v" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/pci_exp_usrapp_rx.v" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/tests.vh" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/sample_tests1.vh" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/pci_exp_usrapp_tx.v" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/pcie1234_gt_top_pipe_mode.v" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/pcie_2_1_rport_7x.v" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/pcie_axi_trn_bridge.v" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/sys_clk_gen.v" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/sys_clk_gen_ds.v" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/xilinx_pcie_2_1_rport_7x.v" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/board.v" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/pipe_interconnect.vh" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/imports/xil_sig2pipe.v" ]\
- [file normalize "${origin_dir}/Users/Work_Pc/Music/pcie1234_ex/board_behav.wcfg" ]\
+ [file normalize "${origin_dir}/PciVnaEmul_Repo/src/PciE/board.v"] \
 ]
-set imported_files ""
-foreach f $files {
-  lappend imported_files [import_files -fileset sim_1 $f]
-}
+add_files -norecurse -fileset $obj $files
 
 # Set 'sim_1' fileset file properties for remote files
 # None
 
 # Set 'sim_1' fileset file properties for local files
-set file "imports/board_common.vh"
-set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
-set_property -name "file_type" -value "Verilog Header" -objects $file_obj
-set_property -name "used_in" -value "simulation" -objects $file_obj
-set_property -name "used_in_synthesis" -value "0" -objects $file_obj
-
-set file "imports/pci_exp_usrapp_cfg.v"
-set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
-set_property -name "used_in" -value "implementation simulation" -objects $file_obj
-set_property -name "used_in_synthesis" -value "0" -objects $file_obj
-
-set file "imports/pci_exp_expect_tasks.vh"
-set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
-set_property -name "file_type" -value "Verilog Header" -objects $file_obj
-set_property -name "used_in" -value "simulation" -objects $file_obj
-set_property -name "used_in_synthesis" -value "0" -objects $file_obj
-
-set file "imports/pci_exp_usrapp_com.v"
-set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
-set_property -name "used_in" -value "implementation simulation" -objects $file_obj
-set_property -name "used_in_synthesis" -value "0" -objects $file_obj
-
-set file "imports/pci_exp_usrapp_pl.v"
-set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
-set_property -name "used_in" -value "implementation simulation" -objects $file_obj
-set_property -name "used_in_synthesis" -value "0" -objects $file_obj
-
-set file "imports/pci_exp_usrapp_rx.v"
-set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
-set_property -name "used_in" -value "implementation simulation" -objects $file_obj
-set_property -name "used_in_synthesis" -value "0" -objects $file_obj
-
-set file "imports/tests.vh"
-set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
-set_property -name "file_type" -value "Verilog Header" -objects $file_obj
-set_property -name "used_in" -value "simulation" -objects $file_obj
-set_property -name "used_in_synthesis" -value "0" -objects $file_obj
-
-set file "imports/sample_tests1.vh"
-set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
-set_property -name "file_type" -value "Verilog Header" -objects $file_obj
-set_property -name "used_in" -value "simulation" -objects $file_obj
-set_property -name "used_in_synthesis" -value "0" -objects $file_obj
-
-set file "imports/pci_exp_usrapp_tx.v"
-set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
-set_property -name "used_in" -value "implementation simulation" -objects $file_obj
-set_property -name "used_in_synthesis" -value "0" -objects $file_obj
-
-set file "imports/pcie1234_gt_top_pipe_mode.v"
-set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
-set_property -name "used_in" -value "implementation simulation" -objects $file_obj
-set_property -name "used_in_synthesis" -value "0" -objects $file_obj
-
-set file "imports/pcie_2_1_rport_7x.v"
-set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
-set_property -name "used_in" -value "implementation simulation" -objects $file_obj
-set_property -name "used_in_synthesis" -value "0" -objects $file_obj
-
-set file "imports/pcie_axi_trn_bridge.v"
-set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
-set_property -name "used_in" -value "implementation simulation" -objects $file_obj
-set_property -name "used_in_synthesis" -value "0" -objects $file_obj
-
-set file "imports/sys_clk_gen.v"
-set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
-set_property -name "used_in" -value "implementation simulation" -objects $file_obj
-set_property -name "used_in_synthesis" -value "0" -objects $file_obj
-
-set file "imports/sys_clk_gen_ds.v"
-set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
-set_property -name "used_in" -value "implementation simulation" -objects $file_obj
-set_property -name "used_in_synthesis" -value "0" -objects $file_obj
-
-set file "imports/xilinx_pcie_2_1_rport_7x.v"
-set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
-set_property -name "used_in" -value "implementation simulation" -objects $file_obj
-set_property -name "used_in_synthesis" -value "0" -objects $file_obj
-
-set file "imports/board.v"
-set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
-set_property -name "used_in" -value "implementation simulation" -objects $file_obj
-set_property -name "used_in_synthesis" -value "0" -objects $file_obj
-
-set file "imports/pipe_interconnect.vh"
-set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
-set_property -name "file_type" -value "Verilog Header" -objects $file_obj
-set_property -name "used_in" -value "simulation" -objects $file_obj
-set_property -name "used_in_synthesis" -value "0" -objects $file_obj
-
-set file "imports/xil_sig2pipe.v"
-set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
-set_property -name "used_in" -value "implementation simulation" -objects $file_obj
-set_property -name "used_in_synthesis" -value "0" -objects $file_obj
-
+# None
 
 # Set 'sim_1' fileset properties
 set obj [get_filesets sim_1]
-set_property -name "top" -value "S5443TopSimpleMeasTb" -objects $obj
+set_property -name "top" -value "board" -objects $obj
 set_property -name "top_auto_set" -value "0" -objects $obj
 set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
 
@@ -660,6 +543,7 @@ if { $obj != "" } {
 }
 set obj [get_runs synth_1]
 set_property -name "part" -value "xc7a100tfgg484-2" -objects $obj
+set_property -name "auto_incremental_checkpoint" -value "1" -objects $obj
 set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
 set_property -name "steps.synth_design.args.flatten_hierarchy" -value "none" -objects $obj
 set_property -name "steps.synth_design.args.gated_clock_conversion" -value "auto" -objects $obj