xilinx_pcie_2_1_ep_7x | |--pcie1234_support | |--pcie1234_pipe_clock | |--pcie1234 (Core Top level module Generated by Vivado in synth directory) | |--pcie_7x_v3_3_14_top (Static Top level file) | |--pcie_7x_v3_3_14_core_top | | | |--pcie1234_pcie_top | | | | | |--pcie1234_axi_basic_top | | | | | | | |--pcie1234_axi_basic_rx | | | | | | | | | |--pcie1234_axi_basic_rx_pipeline | | | | |--pcie1234_axi_basic_rx_null_gen | | | | | | | |--pcie1234_axi_basic_tx | | | | | | | |--pcie1234_axi_basic_tx_pipeline | | | |--pcie1234_axi_basic_tx_thrtl_ctl | | | | | |--pcie1234_pcie_7x | | | | | | | |--pcie1234_pcie_bram_top_7x | | | | | | | | | |--pcie1234_pcie_brams_7x (an instance each for Rx & Tx) | | | | | | | | | |--pcie1234_pcie_bram_7x | | | | | | | |--PCIE_2_1 (Integrated Block Instance) | | | | | |--pcie1234_pcie_pipe_pipeline | | | | | |--pcie1234_pcie_pipe_misc | | |--pcie1234_pcie_pipe_lane (per lane) | | | |--pcie1234_gt_top | | | |--pcie1234_gt_rx_valid_filter | | | |--pcie1234_pipe_wrapper | | | | | |--pcie1234_pipe_reset | | |--pcie1234_qpll_reset | | |--pcie1234_pipe_user | | |--pcie1234_pipe_rate | | |--pcie1234_pipe_sync | | |--pcie1234_pipe_drp | | |--pcie1234_pipe_eq | | | |--pcie1234_rxeq_scan | | | | | | |--pcie1234_gt_common | | | |--pcie1234_qpll_drp | | | |--pcie1234_qpll_wrapper | | | | | |--pcie1234_gt_wrapper | |--pcie_app_7x (PIO design, in example_design directory) | |--PIO | |--PIO_EP | | | |--PIO_EP_MEM_ACCESS | | | | | |--EP_MEM | | | | | |--RAMB36 | | | |--PIO_RX_ENGINE | |--PIO_TX_ENGINE | |--PIO_TO_CTRL