PciVnaEmul/src/PulseMeas/SampleStrobeGenRstDemux.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:02:35 04/20/2020 
// Design Name: 
// Module Name:    mult_module 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module	SampleStrobeGenRstDemux	
#(	
	parameter	CmdRegWidth		=	24,
	parameter	PGenNum			=	7,
	parameter	TrigPortsNum	=	6
)
(
	input	Rst_i,
	input	[CmdRegWidth-28:0]	MuxCtrl_i,
	input	GenRst_i,
	
	output	[PGenNum-1:0]	RstDemuxOut_o
);	

//================================================================================
//  LOCALPARAM

//================================================================================
//	REG/WIRE
	reg	[PGenNum-1:0]	demuxOut;
//================================================================================
//  ASSIGNMENTS
	assign	RstDemuxOut_o	=	demuxOut;

//================================================================================
//  CODING

always	@(*)	begin
	if	(!Rst_i)	begin
		case(MuxCtrl_i)
			5'd0:	begin
						demuxOut	=	{6'b000000,GenRst_i};
					end
			5'd1:	begin
						demuxOut	=	{5'b00000,GenRst_i,1'b0};
					end
			5'd2:	begin
						demuxOut	=	{5'b0000,GenRst_i,2'b00};
					end
			5'd3:	begin
						demuxOut	=	{3'b000,GenRst_i,3'b000};
					end
			5'd4:	begin
						demuxOut	=	{2'b00,GenRst_i,5'b0000};
					end
			5'd5:	begin
						demuxOut	=	{1'b0,GenRst_i,5'b00000};
					end
			5'd6:	begin
						demuxOut	=	{GenRst_i,6'b000000};
					end
			default	:begin
						demuxOut	=	7'b0000000;
					end
		endcase
	end	else	begin
		demuxOut	=	0;
	end
end
endmodule