PciVnaEmul/constr/xilinx_pcie_7x_ep_x1g1.xdc

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##-----------------------------------------------------------------------------
## Project    : Series-7 Integrated Block for PCI Express
## File       : xilinx_pcie_7x_ep_x1g1.xdc
## Version    : 3.3
#
###############################################################################
# User Configuration
# Link Width   - x1
# Link Speed   - gen1
# Family       - artix7
# Part         - xc7a100t
# Package      - fgg484
# Speed grade  - -2
# PCIe Block   - X0Y0
###############################################################################
#
###############################################################################
# User Time Names / User Time Groups / Time Specs
###############################################################################

###############################################################################
# User Physical Constraints
###############################################################################


###############################################################################
# Pinout and Related I/O Constraints
###############################################################################

#
# SYS reset (input) signal.  The sys_reset_n signal should be
# obtained from the PCI Express interface if possible.  For
# slot based form factors, a system reset signal is usually
# present on the connector.  For cable based form factors, a
# system reset signal may not be available.  In this case, the
# system reset signal must be generated locally by some form of
# supervisory circuit.  You may change the IOSTANDARD and LOC
# to suit your requirements and VCCO voltage banking rules.
# Some 7 series devices do not have 3.3 V I/Os available.
# Therefore the appropriate level shift is required to operate
# with these devices that contain only 1.8 V banks.
#

set_property IOSTANDARD LVCMOS33 [get_ports sys_rst_n]
set_property PULLTYPE PULLUP [get_ports sys_rst_n]

###############################################################################
# Physical Constraints
###############################################################################
#
# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n
# signals are the PCI Express reference clock. Virtex-7 GT
# Transceiver architecture requires the use of a dedicated clock
# resources (FPGA input pins) associated with each GT Transceiver.
# To use these pins an IBUFDS primitive (refclk_ibuf) is
# instantiated in user's design.
# Please refer to the Virtex-7 GT Transceiver User Guide
# (UG) for guidelines regarding clock resource selection.
#

set_property LOC IBUFDS_GTE2_X0Y3 [get_cells refclk_ibuf]

###############################################################################
# Timing Constraints
###############################################################################
#
create_clock -period 10.000 -name sys_clk [get_ports sys_clk_p]
#
#
set_false_path -to [get_pins {pcie1234_support_i/pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/S0}]
set_false_path -to [get_pins {pcie1234_support_i/pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/S1}]
#
#
set_case_analysis 1 [get_pins {pcie1234_support_i/pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/S0}]
set_case_analysis 0 [get_pins {pcie1234_support_i/pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/S1}]
set_property DONT_TOUCH true [get_cells -of [get_nets -of [get_pins {pcie1234_support_i/pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/S0}]]]

#
#
# Timing ignoring the below pins to avoid CDC analysis, but care has been taken in RTL to sync properly to other clock domain.
#
#
##############################################################################
# Tandem Configuration Constraints
###############################################################################

set_false_path -from [get_ports sys_rst_n]

###############################################################################
# End
###############################################################################

set_property PACKAGE_PIN F10 [get_ports sys_clk_p]
set_property PACKAGE_PIN J20 [get_ports sys_rst_n]
set_property LOC GTPE2_CHANNEL_X0Y4 [get_cells {EP/pcie1234_support/pcie1234_i/inst/inst/gt_top.gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
set_property PACKAGE_PIN A8 [get_ports {pci_exp_rxn[1]}]
set_property PACKAGE_PIN B8 [get_ports {pci_exp_rxp[1]}]
set_property DRIVE 12 [get_ports {pci_exp_txn[1]}]
set_property LOC GTPE2_CHANNEL_X0Y5 [get_cells {EP/pcie1234_support/pcie1234_i/inst/inst/gt_top.gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
set_property PACKAGE_PIN C11 [get_ports {pci_exp_rxn[0]}]

set_property LOC GTPE2_CHANNEL_X0Y4 [get_cells {PciVnaEmulTop/pcie1234_support/pcie1234_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]

set_property LOC GTPE2_CHANNEL_X0Y5 [get_cells {PciVnaEmulTop/pcie1234_support/pcie1234_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]



connect_debug_port u_ila_0/clk [get_nets [list EP/pcie1234_support/pipe_clock_i/pclk_sel_reg_0]]
connect_debug_port u_ila_0/probe0 [get_nets [list {EP/pcie1234_support/pclk_sel_reg1_reg[1][0]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][1]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][2]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][3]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][4]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][5]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][6]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][7]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][8]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][9]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][10]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][11]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][12]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][13]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][14]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][15]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][16]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][17]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][18]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][19]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][20]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][21]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][22]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][23]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][24]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][25]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][26]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][27]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][28]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][29]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][30]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][31]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][32]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][33]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][34]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][35]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][36]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][37]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][38]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][39]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][40]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][41]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][42]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][43]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][44]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][45]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][46]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][47]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][48]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][49]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][50]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][51]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][52]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][53]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][54]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][55]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][56]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][57]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][58]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][59]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][60]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][61]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][62]} {EP/pcie1234_support/pclk_sel_reg1_reg[1][63]}]]
connect_debug_port dbg_hub/clk [get_nets u_ila_0_pclk_sel_reg_0]




connect_debug_port u_ila_0/probe10 [get_nets [list EP/app/PIO/PIO_EP_inst/IntermediateLogic/valToCfgPos]]




connect_debug_port u_ila_0/probe11 [get_nets [list {FPGA_M/PGen[3].TestPgen/nextState[0]}]]
connect_debug_port u_ila_0/probe19 [get_nets [list {FPGA_M/PGen[3].TestPgen/delayDone0}]]
connect_debug_port u_ila_0/probe29 [get_nets [list {FPGA_M/PGen[3].TestPgen/patternDone1}]]
connect_debug_port u_ila_0/probe39 [get_nets [list {FPGA_M/PGen[0].TestPgen/delayDone0}]]

connect_debug_port u_ila_0/probe2 [get_nets [list {FPGA_M/PGen[0].TestPgen/currState[0]} {FPGA_M/PGen[0].TestPgen/currState[1]}]]
connect_debug_port u_ila_0/probe3 [get_nets [list {FPGA_M/PGen[3].TestPgen/currState[0]} {FPGA_M/PGen[3].TestPgen/currState[1]}]]
connect_debug_port u_ila_0/probe4 [get_nets [list {FPGA_M/PGen[0].TestPgen/currWidthValue[0]}]]
connect_debug_port u_ila_0/probe5 [get_nets [list {FPGA_M/PGen[3].TestPgen/delayCnt_reg[0]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[1]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[2]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[3]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[4]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[5]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[6]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[7]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[8]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[9]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[10]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[11]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[12]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[13]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[14]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[15]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[16]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[17]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[18]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[19]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[20]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[21]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[22]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[23]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[24]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[25]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[26]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[27]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[28]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[29]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[30]} {FPGA_M/PGen[3].TestPgen/delayCnt_reg[31]}]]
connect_debug_port u_ila_0/probe6 [get_nets [list {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[0]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[1]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[2]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[3]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[4]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[5]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[6]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[7]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[8]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[9]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[10]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[11]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[12]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[13]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[14]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[15]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[16]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[17]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[18]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[19]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[20]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[21]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[22]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[23]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[24]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[25]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[26]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[27]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[28]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[29]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[30]} {FPGA_M/PGen[3].TestPgen/pulseCnt_reg[31]}]]
connect_debug_port u_ila_0/probe7 [get_nets [list {FPGA_M/PGen[3].TestPgen/widthCnt_reg[0]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[1]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[2]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[3]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[4]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[5]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[6]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[7]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[8]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[9]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[10]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[11]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[12]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[13]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[14]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[15]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[16]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[17]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[18]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[19]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[20]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[21]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[22]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[23]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[24]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[25]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[26]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[27]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[28]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[29]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[30]} {FPGA_M/PGen[3].TestPgen/widthCnt_reg[31]}]]
connect_debug_port u_ila_0/probe8 [get_nets [list {FPGA_M/PGen[0].TestPgen/nextState[0]} {FPGA_M/PGen[0].TestPgen/nextState[1]}]]
connect_debug_port u_ila_0/probe9 [get_nets [list {FPGA_M/PGen[3].TestPgen/currWidthValue[0]}]]
connect_debug_port u_ila_0/probe10 [get_nets [list {FPGA_M/PGen[0].TestPgen/delayCnt_reg[0]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[1]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[2]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[3]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[4]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[5]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[6]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[7]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[8]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[9]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[10]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[11]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[12]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[13]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[14]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[15]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[16]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[17]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[18]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[19]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[20]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[21]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[22]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[23]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[24]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[25]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[26]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[27]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[28]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[29]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[30]} {FPGA_M/PGen[0].TestPgen/delayCnt_reg[31]}]]
connect_debug_port u_ila_0/probe11 [get_nets [list {FPGA_M/PGen[0].TestPgen/widthCnt_reg[0]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[1]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[2]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[3]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[4]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[5]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[6]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[7]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[8]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[9]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[10]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[11]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[12]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[13]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[14]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[15]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[16]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[17]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[18]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[19]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[20]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[21]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[22]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[23]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[24]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[25]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[26]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[27]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[28]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[29]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[30]} {FPGA_M/PGen[0].TestPgen/widthCnt_reg[31]}]]
connect_debug_port u_ila_0/probe19 [get_nets [list {FPGA_M/PGen[0].TestPgen/EnPulse_i}]]
connect_debug_port u_ila_0/probe20 [get_nets [list {FPGA_M/PGen[3].TestPgen/EnPulse_i}]]
connect_debug_port u_ila_0/probe21 [get_nets [list {FPGA_M/PGen[0].TestPgen/enPulseR}]]
connect_debug_port u_ila_0/probe22 [get_nets [list {FPGA_M/PGen[3].TestPgen/enPulseR}]]
connect_debug_port u_ila_0/probe23 [get_nets [list {FPGA_M/PGen[0].TestPgen/enPulseR_reg_n_0}]]
connect_debug_port u_ila_0/probe31 [get_nets [list {FPGA_M/PGen[3].TestPgen/Pulse_o}]]
connect_debug_port u_ila_0/probe32 [get_nets [list {FPGA_M/PGen[0].TestPgen/Pulse_o}]]
connect_debug_port u_ila_0/probe33 [get_nets [list {FPGA_M/PGen[0].TestPgen/pulseDone0}]]
connect_debug_port u_ila_0/probe34 [get_nets [list {FPGA_M/PGen[3].TestPgen/pulseDone0}]]



create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list EP/pcie1234_support/pipe_clock_i/CLK_PCLK]]
set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe0]
set_property port_width 32 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[0]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[1]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[2]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[3]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[4]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[5]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[6]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[7]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[8]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[9]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[10]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[11]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[12]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[13]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[14]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[15]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[16]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[17]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[18]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[19]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[20]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[21]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[22]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[23]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[24]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[25]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[26]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[27]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[28]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[29]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[30]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/CfgData_i[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe1]
set_property port_width 32 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[0]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[1]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[2]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[3]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[4]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[5]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[6]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[7]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[8]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[9]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[10]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[11]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[12]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[13]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[14]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[15]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[16]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[17]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[18]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[19]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[20]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[21]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[22]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[23]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[24]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[25]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[26]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[27]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[28]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[29]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[30]} {EP/app/PIO/PIO_EP_inst/IntermediateLogic/cfgReg[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 64 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {measData[0]} {measData[1]} {measData[2]} {measData[3]} {measData[4]} {measData[5]} {measData[6]} {measData[7]} {measData[8]} {measData[9]} {measData[10]} {measData[11]} {measData[12]} {measData[13]} {measData[14]} {measData[15]} {measData[16]} {measData[17]} {measData[18]} {measData[19]} {measData[20]} {measData[21]} {measData[22]} {measData[23]} {measData[24]} {measData[25]} {measData[26]} {measData[27]} {measData[28]} {measData[29]} {measData[30]} {measData[31]} {measData[32]} {measData[33]} {measData[34]} {measData[35]} {measData[36]} {measData[37]} {measData[38]} {measData[39]} {measData[40]} {measData[41]} {measData[42]} {measData[43]} {measData[44]} {measData[45]} {measData[46]} {measData[47]} {measData[48]} {measData[49]} {measData[50]} {measData[51]} {measData[52]} {measData[53]} {measData[54]} {measData[55]} {measData[56]} {measData[57]} {measData[58]} {measData[59]} {measData[60]} {measData[61]} {measData[62]} {measData[63]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 1 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list endMeas]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list FPGA_M/intTrig1]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list FPGA_M/InternalDsp/MeasEnd_o]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list FPGA_M/measStart]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
set_property port_width 1 [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list FPGA_M/measTrig]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
set_property port_width 1 [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list FPGA_M/InternalDsp/MeasWind_o]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
set_property port_width 1 [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list FPGA_M/InternalDsp/measWindEnd]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list FPGA_M/pgMuxedOut_0]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list EP/app/PIO/PIO_EP_inst/req_compl]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list startMeasCmd]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list FPGA_M/StartMeasEvent_o]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
connect_debug_port u_ila_0/probe14 [get_nets [list FPGA_M/startMeasSyncRR]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
connect_debug_port u_ila_0/probe15 [get_nets [list EP/app/PIO/PIO_EP_inst/valToCfgReg]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
connect_debug_port u_ila_0/probe16 [get_nets [list EP/app/PIO/PIO_EP_inst/valToMeasData]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets u_ila_0_CLK_PCLK]