Актуализация кода по аналогии с 4х портовой версией.

src/constrs/S5243Top.xdc

@@ -314,77 +314,25 @@ connect_debug_port u_ila_0/probe3 [get_nets [list {InternalDsp/DspChannel[0].Adc
 connect_debug_port u_ila_0/probe6 [get_nets [list intTrig2]]
 
 
-create_debug_core u_ila_0 ila
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
-set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
-set_property port_width 1 [get_debug_ports u_ila_0/clk]
-connect_debug_port u_ila_0/clk [get_nets [list gclk_BUFG]]
-set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe0]
-set_property port_width 7 [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {pulseBus[0]} {pulseBus[1]} {pulseBus[2]} {pulseBus[3]} {pulseBus[4]} {pulseBus[5]} {pulseBus[6]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe1]
-set_property port_width 1 [get_debug_ports u_ila_0/probe1]
-connect_debug_port u_ila_0/probe1 [get_nets [list InternalDsp/EndMeas_o]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
-set_property port_width 1 [get_debug_ports u_ila_0/probe2]
-connect_debug_port u_ila_0/probe2 [get_nets [list intTrig1]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe3]
-set_property port_width 1 [get_debug_ports u_ila_0/probe3]
-connect_debug_port u_ila_0/probe3 [get_nets [list InternalDsp/MeasEnd_o]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe4]
-set_property port_width 1 [get_debug_ports u_ila_0/probe4]
-connect_debug_port u_ila_0/probe4 [get_nets [list measTrig]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe5]
-set_property port_width 1 [get_debug_ports u_ila_0/probe5]
-connect_debug_port u_ila_0/probe5 [get_nets [list InternalDsp/MeasWind_o]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe6]
-set_property port_width 1 [get_debug_ports u_ila_0/probe6]
-connect_debug_port u_ila_0/probe6 [get_nets [list InternalDsp/measWindEnd]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe7]
-set_property port_width 1 [get_debug_ports u_ila_0/probe7]
-connect_debug_port u_ila_0/probe7 [get_nets [list InternalDsp/StartMeas_i]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe8]
-set_property port_width 1 [get_debug_ports u_ila_0/probe8]
-connect_debug_port u_ila_0/probe8 [get_nets [list InternalDsp/StartMeasDsp_i]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe9]
-set_property port_width 1 [get_debug_ports u_ila_0/probe9]
-connect_debug_port u_ila_0/probe9 [get_nets [list startMeasEvent]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
-set_property port_width 1 [get_debug_ports u_ila_0/probe10]
-connect_debug_port u_ila_0/probe10 [get_nets [list startMeasSync_reg_n_0]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe11]
-set_property port_width 1 [get_debug_ports u_ila_0/probe11]
-connect_debug_port u_ila_0/probe11 [get_nets [list MeasStartEventGenInst/MeasTrig_i]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe12]
-set_property port_width 1 [get_debug_ports u_ila_0/probe12]
-connect_debug_port u_ila_0/probe12 [get_nets [list MeasStartEventGenInst/measTrigReg]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe13]
-set_property port_width 1 [get_debug_ports u_ila_0/probe13]
-connect_debug_port u_ila_0/probe13 [get_nets [list MeasStartEventGenInst/measTrigReg_reg_n_0]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe14]
-set_property port_width 1 [get_debug_ports u_ila_0/probe14]
-connect_debug_port u_ila_0/probe14 [get_nets [list MeasStartEventGenInst/StartMeasDsp_i]]
-set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
-set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
-set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
-connect_debug_port dbg_hub/clk [get_nets gclk_BUFG]
+
+
+
+connect_debug_port u_ila_0/probe2 [get_nets [list {pGenMeasRst[0]} {pGenMeasRst[1]} {pGenMeasRst[2]} {pGenMeasRst[3]} {pGenMeasRst[5]} {pGenMeasRst[6]}]]
+
+
+connect_debug_port u_ila_0/probe6 [get_nets [list MeasStartEventGenInst/measTrigPos]]
+
+
+connect_debug_port u_ila_0/probe17 [get_nets [list MeasStartEventGenInst/startMeasEvent_reg_LDC_i_1_n_0]]
+connect_debug_port u_ila_0/probe18 [get_nets [list MeasStartEventGenInst/startMeasEvent_reg_LDC_i_2_n_0]]
+connect_debug_port u_ila_0/probe19 [get_nets [list MeasStartEventGenInst/startMeasEvent_reg_LDC_n_0]]
+connect_debug_port u_ila_0/probe20 [get_nets [list MeasStartEventGenInst/startMeasEvent_reg_P_n_0]]
+
+
+connect_debug_port u_ila_0/probe5 [get_nets [list MeasStartEventGenInst/measTrigRegR]]
+
+connect_debug_port u_ila_0/probe4 [get_nets [list MeasStartEventGenInst/measTrigReg]]
+
+
+connect_debug_port u_ila_0/probe9 [get_nets [list MeasStartEventGenInst/startMeasEventVal_reg_n_0]]
+

src/src/PulseMeas/MeasStartEventGen.v

@@ -1,4 +1,5 @@
 `timescale 1ns / 1ps
+(* keep_hierarchy = "yes" *)	
 //////////////////////////////////////////////////////////////////////////////////
 // Company: 
 // Engineer: 
@@ -44,6 +45,7 @@ module	MeasStartEventGen
 //  LOCALPARAM
 
 //================================================================================
+	reg		startMeasEventVal;
 	reg		startMeasEvent;
 	reg		initTrig;
 	
@@ -59,18 +61,34 @@ module	MeasStartEventGen
 
 	always	@(posedge	Clk_i)	begin
 		if	(!Rst_i)	begin
-			measTrigReg	<=	MeasTrig_i;
+			measTrigReg	 <=	MeasTrig_i;
 		end	else	begin
-			measTrigReg	=	0;
+			measTrigReg	 <=	0;
 		end
 	end
 	
-	always	@(*)	begin
+	always	@(posedge Clk_i)	begin
 		if	(!Rst_i)	begin
 			if	(StartMeasDsp_i)	begin
 				if	(measTrigPos)	begin
-					startMeasEvent	=	MeasTrig_i;
+					startMeasEventVal	<=	1'b1;
 				end 
+			end	else	begin
+				startMeasEventVal	<=	0;
+			end
+		end	else	begin
+			startMeasEventVal	<=	0;
+		end
+	end
+	
+	always	@(*)	begin
+		if	(!Rst_i)	begin
+			if	(StartMeasDsp_i)	begin
+				if	(startMeasEventVal)	begin
+					startMeasEvent	=	measTrigReg;
+				end else begin
+					startMeasEvent	=	0;
+				end
 			end	else	begin
 				startMeasEvent	=	0;
 			end

src/src/Top/S5243Top.v

@@ -1185,6 +1185,7 @@ PulseGenNew
 PulseGenerator
 (
 	.Rst_i			(initRst|pGenRst[j]|pGenMeasRst[j]),
+	// .Rst_i			(initRst|pGenRst[j]),
 	.Clk_i			(gclk),
 	.EnPulse_i		(pgMuxedOut[j]),