`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// company: 
// engineer: 
// 
// create date:    16:37:06 07/11/2019 
// design name: 
// module name:    dsp_linkport_interface 
// project name: 
// target devices: 
// tool versions: 
// description: 					
//
// dependencies: 
//
// revision: 
// revision 0.01 - file created
// additional comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module	DecimFilterWrapperTest
#(	
	parameter	AdcDataWidth		=	14,
	parameter	N	=	9,
	parameter	M	=	1,
	parameter	FilteredDataWidth	=	32,
	parameter	FirOutDataWidth		=	48,
	parameter	FirOutCutBit		=	42,
	parameter	LsbForR1	=	10'd16,
	parameter	LsbForR2	=	10'd16,
	parameter	LsbForR4	=	10'd16
)
(
	input	Clk_i,
	input	[2:0]	DecimFactor_i,
	input	Rst_i,
	
	input	DataVal_i,
	input	signed	[AdcDataWidth-1:0]	Data_i,
	
	// output	signed	[16-1:0]	Data_o,
	output	signed	[FilteredDataWidth-1:0]	Data_o,
	output	DataVal_o
);
//================================================================================
//	REG/WIRE
//================================================================================
	wire	signed	[FilteredDataWidth-1:0]	decimData;
	wire	decimDataVal;
	
	localparam	extendBitNum	=	FilteredDataWidth-AdcDataWidth;
	
	wire	[FilteredDataWidth-1:0]	adcExtData	=	{{extendBitNum{Data_i[AdcDataWidth-1]}},Data_i};
	
	reg dataValReg;
	wire dataValNeg = !DataVal_i&dataValReg;
//================================================================================
//	ASSIGNMENTS
//================================================================================

	assign Data_o		=	decimData;
	assign DataVal_o	=	decimDataVal;

//================================================================================
//	CODING
//================================================================================
	always @(posedge Clk_i) begin
		if (!Rst_i) begin
			dataValReg <= DataVal_i;
		end else begin
			dataValReg <= 0;
		end
	end
	
cicFilterTest 
#(
	.N (N),	//filter order
	.M (M),	//comb delay
	.filteredDataWidth	(FilteredDataWidth),
	.inOutDataWidth		(FilteredDataWidth),
	.decimCntWidth		(7)
)
cicFilterInstI
(
	.Clk_i			(Clk_i),
	// .Rst_i			(Rst_i|dataValNeg),
	.Rst_i			(Rst_i),
	// .DecimFactor_i	(currDecimFactor),
	.DecimFactor_i	(DecimFactor_i),
	.Data_i			({{extendBitNum{Data_i[AdcDataWidth-1]}},Data_i}),
	.DataNd_i		(DataVal_i),
	.Data_o			(decimData),
	.DataValid_o	(decimDataVal)
);

endmodule








