`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:42:08 10/27/2020 
// Design Name: 
// Module Name:    decimBlock 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module decimBlock
#(	
	// parameter	R	=	2,
	parameter	inOutDataWidth	=	18,
	parameter	decimCntWidth	=	7
)
(
	input Clk_i,
	input Rst_i,
	input [2:0]	DecimFactor_i,
	input [inOutDataWidth-1:0] Data_i,
	input DataNd_i,
	output [inOutDataWidth-1:0] Data_o,
	output DataValid_o
);

reg	[decimCntWidth-1:0]	decimCnt;
reg	[inOutDataWidth-1:0]	dataReg;
reg	valReg;

reg	[2:0]	decimFactor;

always	@(posedge	Clk_i)	begin
	if	(!Rst_i)	begin
		if	(DecimFactor_i	<=	3'd1)	begin
			decimFactor	<=	3'd1;
		end	else	begin
			decimFactor	<=	DecimFactor_i;
		end
	end	else	begin
		decimFactor	<=	3'd1;
	end
end


always	@(posedge	Clk_i)	begin
	if	(!Rst_i)	begin
		if	(DataNd_i)	begin
			if	(decimCnt	==	decimFactor-1)	begin
				decimCnt	<=	{decimCntWidth{1'b0}};
				// valReg		<=	DataNd_i;
				// dataReg		<=	Data_i;
			end	else	begin
				decimCnt	<=	decimCnt+7'd1;
				// valReg		<=	1'b0;
			end
			// valReg		<=	DataNd_i;
		end	else	begin
			decimCnt	<=	{decimCntWidth{1'b0}};
			// valReg		<=	1'b0;
		end
	end	else	begin
		decimCnt	<=	{decimCntWidth{1'b0}};
		// valReg		<=	1'b0;
		// dataReg	<=	Data_i;
	end
end
	
always	@(posedge	Clk_i)	begin
	if	(!Rst_i)	begin
		// if	(decimCnt	==	decimFactor-1)	begin
		if	(decimCnt	==	0)	begin
			dataReg		<=	Data_i;
			valReg		<=	DataNd_i;
		end	else begin
			valReg		<=	1'b0;
		end
	end	else	begin
		dataReg	<=	0;
		valReg	<=	1'b0;
	end
end

assign	Data_o	=	dataReg;
assign	DataValid_o	=	valReg;
endmodule
