module intFilterBlock 
#(	
	parameter	inOutDataWidth	=	18,
	parameter	filteredDataWidth	=	25
)
(
	input Clk_i,
	input Rst_i,
	input [inOutDataWidth-1:0] Data_i,
	input DataNd_i,
	output [filteredDataWidth-1:0] Data_o,
	output DataValid_o
);

	reg [filteredDataWidth-1:0] outAcc;
	reg outVal;
	
	assign Data_o = outAcc;
	assign DataValid_o = outVal;
	
	always @(posedge Clk_i or posedge Rst_i) begin
		if (Rst_i) begin
			outAcc <= 0;
		end else begin
			if (DataNd_i) begin
				outAcc <= outAcc+Data_i;
				outVal <= 1'b1;
			end else begin
				outAcc <= 0;
				outVal <= 1'b0;
			end 
		end
	end
	
	
endmodule