# set_property PACKAGE_PIN U17 [get_ports Adc1DataDa0P_i]
# set_property PACKAGE_PIN R18 [get_ports Adc1DataDa1P_i]
# set_property PACKAGE_PIN M18 [get_ports Adc1DataDb0P_i]
# set_property PACKAGE_PIN L17 [get_ports Adc1DataDb1P_i]

# set_property PACKAGE_PIN H18 [get_ports Adc2DataDa0P_i]
# set_property PACKAGE_PIN F18 [get_ports Adc2DataDa1P_i]
# set_property PACKAGE_PIN C17 [get_ports Adc2DataDb0P_i]
# set_property PACKAGE_PIN B17 [get_ports Adc2DataDb1P_i]


set_property PACKAGE_PIN H18 [get_ports Adc1DataDa0P_i]
set_property PACKAGE_PIN F18 [get_ports Adc1DataDa1P_i]
set_property PACKAGE_PIN C17 [get_ports Adc1DataDb0P_i]
set_property PACKAGE_PIN B17 [get_ports Adc1DataDb1P_i]

set_property PACKAGE_PIN U17 [get_ports Adc2DataDa0P_i]
set_property PACKAGE_PIN R18 [get_ports Adc2DataDa1P_i]
set_property PACKAGE_PIN M18 [get_ports Adc2DataDb0P_i]
set_property PACKAGE_PIN L17 [get_ports Adc2DataDb1P_i]

#==========================================================================
#   TIMING CONSTRAINTS


#==========================================================================
#	INPUT CLOCKS
set_property PACKAGE_PIN P2 [get_ports ClkP_i]
set_property IOSTANDARD LVDS_25 [get_ports ClkP_i]
set_property IOSTANDARD LVDS_25 [get_ports ClkN_i]

create_clock -period 20.000 [get_ports ClkP_i]

#==========================================================================
#	ADC1

set_property PACKAGE_PIN D18 [get_ports Adc1FclkP_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc1FclkP_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc1FclkN_i]

set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDa0P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDa0N_i]

set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDa1P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDa1N_i]

set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDb0P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDb0N_i]

set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDb1P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDb1N_i]

#==========================================================================
#	ADC2

set_property PACKAGE_PIN R16 [get_ports Adc2FclkP_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc2FclkP_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc2FclkN_i]

set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDa0P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDa0N_i]

set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDa1P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDa1N_i]

set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDb0P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDb0N_i]

set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDb1P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDb1N_i]

#==========================================================================
# DSP interface

set_property PACKAGE_PIN K17 [get_ports Miso_o]
set_property IOSTANDARD LVCMOS25 [get_ports Miso_o]

set_property PACKAGE_PIN K18 [get_ports Mosi_i]
set_property IOSTANDARD LVCMOS25 [get_ports Mosi_i]

set_property PACKAGE_PIN V12 [get_ports Ss_i]
set_property IOSTANDARD LVCMOS25 [get_ports Ss_i]

set_property PACKAGE_PIN T14 [get_ports Sck_i]
set_property IOSTANDARD LVCMOS25 [get_ports Sck_i]
#create_clock -period 24.000 [get_ports Sck_i]
create_clock -period 16.000 [get_ports Sck_i]

set_property PACKAGE_PIN R1 [get_ports LpOutClk_o]
set_property IOSTANDARD LVCMOS33 [get_ports LpOutClk_o]

set_property PACKAGE_PIN N1 [get_ports LpOutFs_o]
set_property IOSTANDARD LVCMOS33 [get_ports LpOutFs_o]

set_property PACKAGE_PIN V7 [get_ports {LpOutData_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[0]}]
set_property PACKAGE_PIN U7 [get_ports {LpOutData_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[1]}]
set_property PACKAGE_PIN V6 [get_ports {LpOutData_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[2]}]
set_property PACKAGE_PIN U6 [get_ports {LpOutData_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[3]}]
set_property PACKAGE_PIN V5 [get_ports {LpOutData_o[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[4]}]
set_property PACKAGE_PIN T5 [get_ports {LpOutData_o[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[5]}]
set_property PACKAGE_PIN T4 [get_ports {LpOutData_o[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[6]}]
set_property PACKAGE_PIN V4 [get_ports {LpOutData_o[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[7]}]
set_property PACKAGE_PIN U3 [get_ports {LpOutData_o[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[8]}]
set_property PACKAGE_PIN V3 [get_ports {LpOutData_o[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[9]}]
set_property PACKAGE_PIN U2 [get_ports {LpOutData_o[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[10]}]
set_property PACKAGE_PIN V2 [get_ports {LpOutData_o[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[11]}]
set_property PACKAGE_PIN T2 [get_ports {LpOutData_o[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[12]}]
set_property PACKAGE_PIN U1 [get_ports {LpOutData_o[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[13]}]
set_property PACKAGE_PIN R2 [get_ports {LpOutData_o[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[14]}]
set_property PACKAGE_PIN T1 [get_ports {LpOutData_o[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[15]}]

#==========================================================================
#  ADC SPI

set_property PACKAGE_PIN E15 [get_ports Adc1InitMosi_o]
set_property IOSTANDARD LVCMOS25 [get_ports Adc1InitMosi_o]
set_property PACKAGE_PIN N15 [get_ports Adc2InitMosi_o]
set_property IOSTANDARD LVCMOS25 [get_ports Adc2InitMosi_o]

set_property PACKAGE_PIN F15 [get_ports Adc1InitClk_o]
set_property IOSTANDARD LVCMOS25 [get_ports Adc1InitClk_o]
set_property PACKAGE_PIN P16 [get_ports Adc2InitClk_o]
set_property IOSTANDARD LVCMOS25 [get_ports Adc2InitClk_o]

set_property PACKAGE_PIN G15 [get_ports Adc1InitCs_o]
set_property IOSTANDARD LVCMOS25 [get_ports Adc1InitCs_o]
set_property PACKAGE_PIN P15 [get_ports Adc2InitCs_o]
set_property IOSTANDARD LVCMOS25 [get_ports Adc2InitCs_o]

set_property PACKAGE_PIN H15 [get_ports Adc1InitRst_o]
set_property IOSTANDARD LVCMOS25 [get_ports Adc1InitRst_o]
set_property PACKAGE_PIN R15 [get_ports Adc2InitRst_o]
set_property IOSTANDARD LVCMOS25 [get_ports Adc2InitRst_o]
#
#==========================================================================
#  OTHER

set_property PACKAGE_PIN J6 [get_ports Led_o]
set_property IOSTANDARD LVCMOS33 [get_ports Led_o]

set_property PACKAGE_PIN R4 [get_ports Overload_o]
set_property IOSTANDARD LVCMOS33 [get_ports Overload_o]

#set_property PACKAGE_PIN R8 [get_ports OverloadS_i]		;#NC
#set_property IOSTANDARD LVCMOS33 [get_ports OverloadS_i]

set_property PACKAGE_PIN T3 [get_ports StartMeas_i]
set_property IOSTANDARD LVCMOS33 [get_ports StartMeas_i]

set_property PACKAGE_PIN N3 [get_ports EndMeas_o]
set_property IOSTANDARD LVCMOS33 [get_ports EndMeas_o]

#set_property PACKAGE_PIN T3 [get_ports StartMeas_o]		;#NC
#set_property IOSTANDARD LVCMOS33 [get_ports StartMeas_o]

set_property PACKAGE_PIN R3 [get_ports TimersClk_o]
set_property IOSTANDARD LVCMOS33 [get_ports TimersClk_o]

# set_property PACKAGE_PIN V14 [get_ports {AmpEn_o[0]}]
# set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[0]}]
# set_property PACKAGE_PIN H17 [get_ports {AmpEn_o[1]}]
# set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[1]}]
# set_property PACKAGE_PIN V16 [get_ports {AmpEn_o[2]}]
# set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[2]}]
# set_property PACKAGE_PIN B16 [get_ports {AmpEn_o[3]}]
# set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[3]}]


set_property PACKAGE_PIN H17 [get_ports {AmpEn_o[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[0]}]

set_property PACKAGE_PIN B16 [get_ports {AmpEn_o[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[1]}]

set_property PACKAGE_PIN V16 [get_ports {AmpEn_o[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[2]}]

set_property PACKAGE_PIN V14 [get_ports {AmpEn_o[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[3]}]



set_property PACKAGE_PIN K3 [get_ports {PortSel_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PortSel_o[0]}]
set_property PACKAGE_PIN K4 [get_ports {PortSel_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PortSel_o[1]}]
#set_property PACKAGE_PIN R3 [get_ports {PortSel_o[2]}]		;#NC
#set_property IOSTANDARD LVCMOS25 [get_ports {PortSel_o[2]}]
#set_property PACKAGE_PIN P3 [get_ports {PortSel_o[3]}]		;#NC
#set_property IOSTANDARD LVCMOS25 [get_ports {PortSel_o[3]}]

#set_property PACKAGE_PIN F14 [get_ports {PortSelDir_o[0]}]		;#NC BUFF_DIR
#set_property IOSTANDARD LVCMOS25 [get_ports {PortSelDir_o[0]}]
#set_property PACKAGE_PIN F15 [get_ports {PortSelDir_o[1]}]		;#NC
#set_property IOSTANDARD LVCMOS25 [get_ports {PortSelDir_o[1]}]
#set_property PACKAGE_PIN R4 [get_ports {PortSelDir_o[2]}]		;#NC
#set_property IOSTANDARD LVCMOS25 [get_ports {PortSelDir_o[2]}]
#set_property PACKAGE_PIN M4 [get_ports {PortSelDir_o[3]}]		;#NC
#set_property IOSTANDARD LVCMOS25 [get_ports {PortSelDir_o[3]}]

#set_property PACKAGE_PIN R7 [get_ports SensEnM_io]			;#NC
#set_property IOSTANDARD LVCMOS33 [get_ports SensEnM_io]

#set_property PACKAGE_PIN T3 [get_ports StartMeasDsp_o]		;#NC
#set_property IOSTANDARD LVCMOS33 [get_ports StartMeasDsp_o]

set_property PACKAGE_PIN K2 [get_ports Mod_o]
set_property IOSTANDARD LVCMOS33 [get_ports Mod_o]


set_property PACKAGE_PIN N2 [get_ports DspTrigOut_i]
set_property IOSTANDARD LVCMOS33 [get_ports DspTrigOut_i]
set_property PACKAGE_PIN M2 [get_ports DspTrigIn_o]
set_property IOSTANDARD LVCMOS33 [get_ports DspTrigIn_o]

set_property PACKAGE_PIN L4 [get_ports {Trig6to1_io[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Trig6to1_io[0]}]
set_property PACKAGE_PIN K1 [get_ports {Trig6to1_io[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Trig6to1_io[1]}]
set_property PACKAGE_PIN B13 [get_ports {Trig6to1_io[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1_io[2]}]
set_property PACKAGE_PIN A13 [get_ports {Trig6to1_io[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1_io[3]}]
set_property PACKAGE_PIN B14 [get_ports {Trig6to1_io[4]}]
set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1_io[4]}]
set_property PACKAGE_PIN A14 [get_ports {Trig6to1_io[5]}]
set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1_io[5]}]

set_property PACKAGE_PIN N5 [get_ports {Trig6to1Dir_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Trig6to1Dir_o[0]}]
set_property PACKAGE_PIN M5 [get_ports {Trig6to1Dir_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Trig6to1Dir_o[1]}]
set_property PACKAGE_PIN D12 [get_ports {Trig6to1Dir_o[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1Dir_o[2]}]
set_property PACKAGE_PIN E12 [get_ports {Trig6to1Dir_o[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1Dir_o[3]}]
set_property PACKAGE_PIN B15 [get_ports {Trig6to1Dir_o[4]}]
set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1Dir_o[4]}]
set_property PACKAGE_PIN A15 [get_ports {Trig6to1Dir_o[5]}]
set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1Dir_o[5]}]

set_property PACKAGE_PIN A16 [get_ports DitherCtrlCh1_o]
set_property IOSTANDARD LVCMOS25 [get_ports DitherCtrlCh1_o]

set_property PACKAGE_PIN V15 [get_ports DitherCtrlCh2_o]
set_property IOSTANDARD LVCMOS25 [get_ports DitherCtrlCh2_o]

set_property PACKAGE_PIN M1 [get_ports DspReadyForRx_i]
set_property IOSTANDARD LVCMOS33 [get_ports DspReadyForRx_i]

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Ss_i_IBUF]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Sck_i_IBUF]


set_false_path -from [get_clocks -of_objects [get_pins Clk200Gen/rx_plle2_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins Clk200Gen/rx_plle2_adv_inst/CLKOUT0]]













connect_debug_port u_ila_0/probe8 [get_nets [list ExternalDspInterface/DecimFilter/OscWind_i]]








connect_debug_port u_ila_0/probe0 [get_nets [list {ExternalDspInterface/DecimFilter/DataFitler/systolicFilterBlockInst/coeffReg[0]} {ExternalDspInterface/DecimFilter/DataFitler/systolicFilterBlockInst/coeffReg[1]} {ExternalDspInterface/DecimFilter/DataFitler/systolicFilterBlockInst/coeffReg[2]} {ExternalDspInterface/DecimFilter/DataFitler/systolicFilterBlockInst/coeffReg[3]} {ExternalDspInterface/DecimFilter/DataFitler/systolicFilterBlockInst/coeffReg[4]} {ExternalDspInterface/DecimFilter/DataFitler/systolicFilterBlockInst/coeffReg[5]} {ExternalDspInterface/DecimFilter/DataFitler/systolicFilterBlockInst/coeffReg[6]} {ExternalDspInterface/DecimFilter/DataFitler/systolicFilterBlockInst/coeffReg[7]} {ExternalDspInterface/DecimFilter/DataFitler/systolicFilterBlockInst/coeffReg[8]} {ExternalDspInterface/DecimFilter/DataFitler/systolicFilterBlockInst/coeffReg[9]} {ExternalDspInterface/DecimFilter/DataFitler/systolicFilterBlockInst/coeffReg[10]} {ExternalDspInterface/DecimFilter/DataFitler/systolicFilterBlockInst/coeffReg[11]} {ExternalDspInterface/DecimFilter/DataFitler/systolicFilterBlockInst/coeffReg[12]} {ExternalDspInterface/DecimFilter/DataFitler/systolicFilterBlockInst/coeffReg[13]} {ExternalDspInterface/DecimFilter/DataFitler/systolicFilterBlockInst/coeffReg[14]} {ExternalDspInterface/DecimFilter/DataFitler/systolicFilterBlockInst/coeffReg[15]} {ExternalDspInterface/DecimFilter/DataFitler/systolicFilterBlockInst/coeffReg[16]} {ExternalDspInterface/DecimFilter/DataFitler/systolicFilterBlockInst/coeffReg[17]}]]



connect_debug_port u_ila_0/probe2 [get_nets [list {ExternalDspInterface/DecimFilter/RomCtrl/currBaseAddr[1]} {ExternalDspInterface/DecimFilter/RomCtrl/currBaseAddr[2]} {ExternalDspInterface/DecimFilter/RomCtrl/currBaseAddr[3]} {ExternalDspInterface/DecimFilter/RomCtrl/currBaseAddr[6]}]]
connect_debug_port u_ila_0/probe8 [get_nets [list ExternalDspInterface/DecimFilter/RomCtrl/coefDataVal_reg_n_0]]
connect_debug_port u_ila_0/probe9 [get_nets [list ExternalDspInterface/DecimFilter/RomCtrl/coefDataValReg]]


connect_debug_port u_ila_0/probe0 [get_nets [list {ExternalDspInterface/DecimFilter/RomCtrl/currBaseAddr[1]} {ExternalDspInterface/DecimFilter/RomCtrl/currBaseAddr[2]} {ExternalDspInterface/DecimFilter/RomCtrl/currBaseAddr[3]} {ExternalDspInterface/DecimFilter/RomCtrl/currBaseAddr[6]}]]


connect_debug_port u_ila_0/probe0 [get_nets [list {ExternalDspInterface/DecimFilter/RomCtrl/currMaxAddr[5]} {ExternalDspInterface/DecimFilter/RomCtrl/currMaxAddr[6]}]]
connect_debug_port u_ila_0/probe1 [get_nets [list {ExternalDspInterface/DecimFilter/DecimFactor_i[0]} {ExternalDspInterface/DecimFilter/DecimFactor_i[1]} {ExternalDspInterface/DecimFilter/DecimFactor_i[2]}]]
connect_debug_port u_ila_0/probe2 [get_nets [list {ExternalDspInterface/DecimFilter/coefAddr[0]} {ExternalDspInterface/DecimFilter/coefAddr[1]} {ExternalDspInterface/DecimFilter/coefAddr[2]} {ExternalDspInterface/DecimFilter/coefAddr[3]} {ExternalDspInterface/DecimFilter/coefAddr[4]} {ExternalDspInterface/DecimFilter/coefAddr[5]} {ExternalDspInterface/DecimFilter/coefAddr[6]}]]
connect_debug_port u_ila_0/probe3 [get_nets [list {ExternalDspInterface/DecimFilter/coefData[0]} {ExternalDspInterface/DecimFilter/coefData[1]} {ExternalDspInterface/DecimFilter/coefData[2]} {ExternalDspInterface/DecimFilter/coefData[3]} {ExternalDspInterface/DecimFilter/coefData[4]} {ExternalDspInterface/DecimFilter/coefData[5]} {ExternalDspInterface/DecimFilter/coefData[6]} {ExternalDspInterface/DecimFilter/coefData[7]} {ExternalDspInterface/DecimFilter/coefData[8]} {ExternalDspInterface/DecimFilter/coefData[9]} {ExternalDspInterface/DecimFilter/coefData[10]} {ExternalDspInterface/DecimFilter/coefData[11]} {ExternalDspInterface/DecimFilter/coefData[12]} {ExternalDspInterface/DecimFilter/coefData[13]} {ExternalDspInterface/DecimFilter/coefData[14]} {ExternalDspInterface/DecimFilter/coefData[15]} {ExternalDspInterface/DecimFilter/coefData[16]} {ExternalDspInterface/DecimFilter/coefData[17]}]]
connect_debug_port u_ila_0/probe4 [get_nets [list {ExternalDspInterface/currDataChannel[0]} {ExternalDspInterface/currDataChannel[1]} {ExternalDspInterface/currDataChannel[2]} {ExternalDspInterface/currDataChannel[3]} {ExternalDspInterface/currDataChannel[4]} {ExternalDspInterface/currDataChannel[5]} {ExternalDspInterface/currDataChannel[6]} {ExternalDspInterface/currDataChannel[7]} {ExternalDspInterface/currDataChannel[8]} {ExternalDspInterface/currDataChannel[9]} {ExternalDspInterface/currDataChannel[10]} {ExternalDspInterface/currDataChannel[11]} {ExternalDspInterface/currDataChannel[12]} {ExternalDspInterface/currDataChannel[13]}]]
connect_debug_port u_ila_0/probe5 [get_nets [list ExternalDspInterface/DecimFilter/coefDataVal]]




create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list gclk_BUFG]]
set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe0]
set_property port_width 16 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {ExternalDspInterface/LpOutData_o[0]} {ExternalDspInterface/LpOutData_o[1]} {ExternalDspInterface/LpOutData_o[2]} {ExternalDspInterface/LpOutData_o[3]} {ExternalDspInterface/LpOutData_o[4]} {ExternalDspInterface/LpOutData_o[5]} {ExternalDspInterface/LpOutData_o[6]} {ExternalDspInterface/LpOutData_o[7]} {ExternalDspInterface/LpOutData_o[8]} {ExternalDspInterface/LpOutData_o[9]} {ExternalDspInterface/LpOutData_o[10]} {ExternalDspInterface/LpOutData_o[11]} {ExternalDspInterface/LpOutData_o[12]} {ExternalDspInterface/LpOutData_o[13]} {ExternalDspInterface/LpOutData_o[14]} {ExternalDspInterface/LpOutData_o[15]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe1]
set_property port_width 14 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {ExternalDspInterface/Adc1ChR1Data_i[0]} {ExternalDspInterface/Adc1ChR1Data_i[1]} {ExternalDspInterface/Adc1ChR1Data_i[2]} {ExternalDspInterface/Adc1ChR1Data_i[3]} {ExternalDspInterface/Adc1ChR1Data_i[4]} {ExternalDspInterface/Adc1ChR1Data_i[5]} {ExternalDspInterface/Adc1ChR1Data_i[6]} {ExternalDspInterface/Adc1ChR1Data_i[7]} {ExternalDspInterface/Adc1ChR1Data_i[8]} {ExternalDspInterface/Adc1ChR1Data_i[9]} {ExternalDspInterface/Adc1ChR1Data_i[10]} {ExternalDspInterface/Adc1ChR1Data_i[11]} {ExternalDspInterface/Adc1ChR1Data_i[12]} {ExternalDspInterface/Adc1ChR1Data_i[13]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe2]
set_property port_width 14 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {ExternalDspInterface/currDataChannel[0]} {ExternalDspInterface/currDataChannel[1]} {ExternalDspInterface/currDataChannel[2]} {ExternalDspInterface/currDataChannel[3]} {ExternalDspInterface/currDataChannel[4]} {ExternalDspInterface/currDataChannel[5]} {ExternalDspInterface/currDataChannel[6]} {ExternalDspInterface/currDataChannel[7]} {ExternalDspInterface/currDataChannel[8]} {ExternalDspInterface/currDataChannel[9]} {ExternalDspInterface/currDataChannel[10]} {ExternalDspInterface/currDataChannel[11]} {ExternalDspInterface/currDataChannel[12]} {ExternalDspInterface/currDataChannel[13]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe3]
set_property port_width 32 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {ExternalDspInterface/filteredDecimDataI[0]} {ExternalDspInterface/filteredDecimDataI[1]} {ExternalDspInterface/filteredDecimDataI[2]} {ExternalDspInterface/filteredDecimDataI[3]} {ExternalDspInterface/filteredDecimDataI[4]} {ExternalDspInterface/filteredDecimDataI[5]} {ExternalDspInterface/filteredDecimDataI[6]} {ExternalDspInterface/filteredDecimDataI[7]} {ExternalDspInterface/filteredDecimDataI[8]} {ExternalDspInterface/filteredDecimDataI[9]} {ExternalDspInterface/filteredDecimDataI[10]} {ExternalDspInterface/filteredDecimDataI[11]} {ExternalDspInterface/filteredDecimDataI[12]} {ExternalDspInterface/filteredDecimDataI[13]} {ExternalDspInterface/filteredDecimDataI[14]} {ExternalDspInterface/filteredDecimDataI[15]} {ExternalDspInterface/filteredDecimDataI[16]} {ExternalDspInterface/filteredDecimDataI[17]} {ExternalDspInterface/filteredDecimDataI[18]} {ExternalDspInterface/filteredDecimDataI[19]} {ExternalDspInterface/filteredDecimDataI[20]} {ExternalDspInterface/filteredDecimDataI[21]} {ExternalDspInterface/filteredDecimDataI[22]} {ExternalDspInterface/filteredDecimDataI[23]} {ExternalDspInterface/filteredDecimDataI[24]} {ExternalDspInterface/filteredDecimDataI[25]} {ExternalDspInterface/filteredDecimDataI[26]} {ExternalDspInterface/filteredDecimDataI[27]} {ExternalDspInterface/filteredDecimDataI[28]} {ExternalDspInterface/filteredDecimDataI[29]} {ExternalDspInterface/filteredDecimDataI[30]} {ExternalDspInterface/filteredDecimDataI[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list ExternalDspInterface/decimDataBusVal]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list ExternalDspInterface/filteredDecimDataVal]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list ExternalDspInterface/LpOutFs_o]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
set_property port_width 1 [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list ExternalDspInterface/OscWind_i]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets gclk_BUFG]
