module intFilterBlock 
#(	parameter	inOutDataWidth	=	18,
	parameter	filteredDataWidth	=	25
)
(
	input Clk_i,
	input [inOutDataWidth-1:0] Data_i,
	input DataNd_i,
	output [filteredDataWidth-1:0] Data_o,
	output DataValid_o
);

	reg [1:0] ndShReg;
	
	always @ (posedge Clk_i)
		ndShReg <= {ndShReg[0:0], DataNd_i};
	
	reg signed [inOutDataWidth-1:0] inReg;
	reg signed [filteredDataWidth-1:0] sumResult;
	
	always	@(posedge	Clk_i)	begin
		if (DataNd_i)	begin
			inReg <= Data_i;
		end
	end
	
	always @ (posedge Clk_i)	begin
		if (ndShReg[0])	begin
			sumResult <= inReg + sumResult;
		end	else	begin
			sumResult <= 0;
		end
	end

	assign Data_o = sumResult;
	assign DataValid_o = ndShReg[1];

endmodule