`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// company: 
// engineer: 
// 
// create date:    11:47:44 07/11/2019 
// design name: 
// module name:    adc_data_interface 
// project name: 
// target devices: 
// tool versions: 
// description: 
//
// dependencies: 
//
// revision: 
// revision 0.01 - file created
// additional comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module	AdcDataInterface	
#(	
	parameter	AdcDataWidth	=	14,
	parameter	ChNum			=	4,
	parameter	Ratio			=	8
)
(
	input	Clk_i,
	input	RefClk_i,
	input	Locked_i,
	input	Rst_i,
	
	input	[AdcDataWidth-1:0]	testAdc,
		
	input	Adc1FclkP_i,		
    input	Adc1FclkN_i,		
	
    input	Adc1DataDa0P_i,
	input	Adc1DataDa0N_i,
    input	Adc1DataDa1P_i,
    input	Adc1DataDa1N_i,
	
	input	Adc1DataDb0P_i,
    input	Adc1DataDb0N_i,
    input	Adc1DataDb1P_i,
    input	Adc1DataDb1N_i,
		
	input	Adc2FclkP_i,		
    input	Adc2FclkN_i,		
	
	input	Adc2DataDa0P_i,
    input	Adc2DataDa0N_i,
    input	Adc2DataDa1P_i,
    input	Adc2DataDa1N_i,
	
	input	Adc2DataDb0P_i,
    input	Adc2DataDb0N_i,
    input	Adc2DataDb1P_i,
    input	Adc2DataDb1N_i,
	
	output	[AdcDataWidth-1:0]	Adc1ChT1Data_o,
	output	[AdcDataWidth-1:0]	Adc1ChR1Data_o,
	output	[AdcDataWidth-1:0]	Adc2ChR2Data_o,
	output	[AdcDataWidth-1:0]	Adc2ChT2Data_o
);
//================================================================================
//  reg/wire
//================================================================================	
	wire    [ChNum-1:0]    	adc1P;
    wire    [ChNum-1:0]    	adc1N;
    wire    [ChNum-1:0]    	adc2P;
    wire    [ChNum-1:0]    	adc2N;
	
	reg	[AdcDataWidth*2-1:0]	adc1DataSyncPipe	[2:0];
	reg	[AdcDataWidth*2-1:0]	adc2DataSyncPipe	[2:0];

	wire	[(ChNum-2)*AdcDataWidth-1:0]	adc1Dout;
	wire	[(ChNum-2)*AdcDataWidth-1:0]	adc2Dout;
	
	wire	[AdcDataWidth-1:0]	adc1ChAData;
	wire	[AdcDataWidth-1:0]	adc1ChBData;
	wire	[AdcDataWidth-1:0]	adc2ChAData;
	wire	[AdcDataWidth-1:0]	adc2ChBData;	
	
	reg		[AdcDataWidth-1:0]	adc1ChT1DataSyncR;	
	reg		[AdcDataWidth-1:0]	adc1ChR1DataSyncR;
	reg		[AdcDataWidth-1:0]	adc2ChT2DataSyncR;
	reg		[AdcDataWidth-1:0]	adc2ChR2DataSyncR;
	
	wire	[AdcDataWidth-1:0]	adc1ChT1DataSync;	
	wire	[AdcDataWidth-1:0]	adc1ChR1DataSync;
	wire	[AdcDataWidth-1:0]	adc2ChT2DataSync;
	wire	[AdcDataWidth-1:0]	adc2ChR2DataSync;
	
	assign  adc1P	= {Adc1DataDb1P_i, Adc1DataDb0P_i, Adc1DataDa1P_i, Adc1DataDa0P_i};
	assign  adc1N	= {Adc1DataDb1N_i, Adc1DataDb0N_i, Adc1DataDa1N_i, Adc1DataDa0N_i};
	
	assign  adc2P	= {Adc2DataDb1P_i, Adc2DataDb0P_i, Adc2DataDa1P_i, Adc2DataDa0P_i};
	assign  adc2N	= {Adc2DataDb1N_i, Adc2DataDb0N_i, Adc2DataDa1N_i, Adc2DataDa0N_i};
	
	// assign	Adc1ChT1Data_o	=	adc1DataSyncPipe[2][AdcDataWidth*2-1-:14];
	// assign	Adc1ChR1Data_o	=	adc1DataSyncPipe[2][AdcDataWidth-1-:14];
	// assign	Adc2ChR2Data_o	=	adc2DataSyncPipe[2][AdcDataWidth*2-1-:14];
	// assign	Adc2ChT2Data_o	=	adc2DataSyncPipe[2][AdcDataWidth-1-:14];
	
	assign	Adc1ChT1Data_o	=	adc1ChT1DataSync;
	assign	Adc1ChR1Data_o	=	adc1ChR1DataSync;
	assign	Adc2ChR2Data_o	=	adc2ChR2DataSync;
	assign	Adc2ChT2Data_o	=	adc2ChT2DataSync;
	
	wire	idly_reset_int;
	wire	rx_reset;
	wire	rx2_cmt_locked;
	wire	Adc1RxClk;
	wire	Adc2RxClk;
	
//================================================================================
//  instantiations
//================================================================================

top5x2_7to1_sdr_rx	Adc1Rx
(                  
	.reset		(Rst_i),
	.refclkin	(RefClk_i),
	.Locked_i	(Locked_i),
	.clkin1_p	(Adc1FclkP_i),
	.clkin1_n	(Adc1FclkN_i),	
	.datain1_p	(adc1P),	
	.datain1_n	(adc1N),	
	.clkin2_p	(),	
	.clkin2_n	(),	
	.datain2_p	(),	
	.datain2_n	(),	
	.dummy		(),
	.dout		(adc1Dout),
	.DivClk_o	(Adc1RxClk)
);

top5x2_7to1_sdr_rx	Adc2Rx
(                  
	.reset		(Rst_i),
	.refclkin	(RefClk_i),
	.Locked_i	(Locked_i),
	.clkin1_p	(Adc2FclkP_i),
	.clkin1_n	(Adc2FclkN_i),	
	.datain1_p	(adc2P),	
	.datain1_n	(adc2N),	
	.clkin2_p	(),	
	.clkin2_n	(),	
	.datain2_p	(),	
	.datain2_n	(),	
	.dummy		(),
	.dout		(adc2Dout),
	.DivClk_o	(Adc2RxClk)
);


AdcSync Adc1Sync
(
    .Clk_i	(Clk_i),
	.Rst_i	(Rst_i),
	
    .Data_i	(adc1Dout),
	
	.Data_o	({adc1ChT1DataSync, adc1ChR1DataSync})
);

AdcSync Adc2Sync
(
    .Clk_i	(Clk_i),
	.Rst_i	(Rst_i),
	
    .Data_i	(adc2Dout),
	
	.Data_o	({adc2ChR2DataSync, adc2ChT2DataSync})
);

// AdcSyncFifo	adc1SyncFifo	(
	// .rst		(Rst_i),
	// .wr_clk		(Adc1RxClk),	
	// .rd_clk		(Clk_i),
	// .din		(adc1Dout),
	// .din		({testAdc,testAdc}),
	// .wr_en		(1'b1),
	// .rd_en		(1'b1),
	// .dout		({adc1ChT1DataSync, adc1ChR1DataSync}),
	// .full		(),
	// .empty		()
// );

// AdcSyncFifo	adc2SyncFifo	(
	// .rst		(Rst_i),
	// .wr_clk		(Adc2RxClk),	
	// .rd_clk		(Clk_i),
	// .din		(adc2Dout),
	// .wr_en		(1'b1),
	// .rd_en		(1'b1),
	// .dout		({adc2ChR2DataSync, adc2ChT2DataSync}),
	// .full		(),
	// .empty		()
// );
endmodule






