`timescale 1ns / 1ns
	
module MeasDataFifoWrapper	
#(	
	parameter	DataWidth	=	32,
	parameter	ChNum		=	4
)
(
	input	Clk_i, 
	input	Rst_i,	
	input	PpiBusy_i,	
	input	StartMeasDsp_i,
	input	DspReadyForRx_i,
	input	[DataWidth-1:0]	MeasNum_i,
	
	input	[DataWidth*(ChNum*2)-1:0]	MeasDataBus_i,
	input	MeasDataVal_i,
	
	output	[DataWidth*(ChNum*2)-1:0]	MeasDataBus_o,
	output	MeasDataVal_o
);
//================================================================================
//  REG/WIRE
//================================================================================

	wire	fullFlagExt;
	wire	emptyFlagExt;
	
	wire	fullFlag;
	wire	emptyFlag;
	
	wire	wrEn;
	wire	rdEn;

	reg		startMeasDspReg;
	wire	startMeasDspNeg;
	wire	startMeasDspPos;
	
	reg		ppiBusyReg;
	
	reg		rstFromDsp;
	wire	trueRstFromDsp;
	
	integer	i;
	reg	[0:0]	rstFromDspPipe	[49:0];
	
	reg		[13:0]	rdCnt;
	wire	rstOr;
	
	wire	[DataWidth*(ChNum*2)-1:0]	measDataBus;
	wire	writeEn	=	!(emptyFlagExt|fullFlag);
//================================================================================
//  ASSIGNMENTS
//================================================================================
	assign	rstOr	=	Rst_i|startMeasDspPos;
	assign	MeasDataVal_o		=	rdEn;
	assign	startMeasDspPos		=	(StartMeasDsp_i&(!startMeasDspReg));
//================================================================================
//  CODING
//================================================================================		

always	@(posedge	Clk_i)	begin
	if	(!rstOr)	begin
		if	(rdEn)	begin
			rdCnt	<=	rdCnt+14'd1;
		end	
	end	else	begin
		rdCnt	<=	14'd0;
	end
end

always	@(posedge	Clk_i)	begin
	if	(!Rst_i)	begin
		startMeasDspReg	<=	StartMeasDsp_i;
	end	else	begin
		startMeasDspReg	<=	1'b0;
	end
end

// MeasDataFifoExtender	MeasDataFifoExtender
// (
	// .clk	(Clk_i),
	// .srst	(Rst_i|startMeasDspPos),
	// .din	(MeasDataBus_i),
	// .wr_en	(wrEn),
	// .rd_en	(writeEn),
	// .dout	(measDataBus),
	// .full	(fullFlagExt),
	// .empty	(emptyFlagExt)
// );

MeasDataFifo	MeasDataFifo
(
	.clk	(Clk_i),
	.srst	(Rst_i|startMeasDspPos),
	.din	(MeasDataBus_i),
	.wr_en	(wrEn),
	.rd_en	(rdEn),
	.dout	(MeasDataBus_o),
	.full	(fullFlag),
	.empty	(emptyFlag)
);

  
FifoController	FifoController
(
	.Clk_i				(Clk_i), 
	.Rst_i				(Rst_i|startMeasDspPos),	
	.DspReadyForRx_i	(DspReadyForRx_i),	
	.PpiBusy_i			(PpiBusy_i),	
	.MeasNum_i			(MeasNum_i),	
	.MeasDataVal_i		(MeasDataVal_i),
	.FullFlag_i			(fullFlag),
	.EmptyFlag_i		(emptyFlag),
	
	.MeasDataVal_o		(),
	.WrEn_o				(wrEn),
	.RdEn_o				(rdEn)
);

endmodule
