`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// company: 
// engineer: 
// 
// create date:    16:37:06 07/11/2019 
// design name: 
// module name:    dsp_linkport_interface 
// project name: 
// target devices: 
// tool versions: 
// description: 					
//
// dependencies: 
//
// revision: 
// revision 0.01 - file created
// additional comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module	DecimFilterWrapperTest
#(	
	parameter	InDataWidth		=	14,
	parameter	N	=	1,
	parameter	M	=	1,
	parameter	OutDataWidth	=	15
)
(
	input	Clk_i,
	input	[2:0]	DecimFactor_i,
	input	Rst_i,
	
	input	DataVal_i,
	input	signed	[InDataWidth-1:0]	Data_i,
	
	output	signed	[OutDataWidth-1:0]	Data_o,
	output	DataVal_o
);
//================================================================================
//	REG/WIRE
//================================================================================
	wire	signed	[OutDataWidth-1:0]	decimData;
	wire	decimDataVal;
	
	localparam	extendBitNum	=	OutDataWidth-InDataWidth;
	
	wire	[OutDataWidth-1:0]	adcExtData	=	{{extendBitNum{Data_i[InDataWidth-1]}},Data_i};
	
	wire	[OutDataWidth-1:0]	inData	[N-1:0];
	wire	intDataVal	[N-1:0];
	
	wire	[OutDataWidth-1:0]	cicBlockOutData	[N-1:0];
	wire	cicBlockOutVal	[N-1:0];
	
//================================================================================
//	ASSIGNMENTS
//================================================================================

assign	Data_o	=	cicBlockOutData[N-1];
assign	DataVal_o	=	cicBlockOutVal[N-1];

//================================================================================
//	CODING
//================================================================================

genvar i;
generate 
	for (i=0; i<N; i=i+1)	begin: CicBlockGen
		
		assign	inData	[i]		=	(i==0)?adcExtData:cicBlockOutData[i-1];
		assign	intDataVal[i]	=	(i==0)?DataVal_i:cicBlockOutVal[i-1];
		
		CicBlock 
		#(
			.M (M),	//comb delay
			.InDataWidth	(OutDataWidth),
			.OutDataWidth	(OutDataWidth)
		)
		CicBlock
		(
			.Clk_i			(Clk_i),
			.Rst_i			(Rst_i),
			.Data_i			(inData[i]),
			.DataNd_i		(intDataVal[i]),
			.Data_o			(cicBlockOutData[i]),
			.DataValid_o	(cicBlockOutVal[i])
		);
	end
	
endgenerate


endmodule








