`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:42:08 10/27/2020 
// Design Name: 
// Module Name:    decimBlock 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module RomCtrl
#(	
	parameter	OutWidth	=	9,
	parameter	Offset		=	24,
	parameter [8:0] BaseAddrR2 = 9'd0,
	parameter [8:0] BaseAddrR4 = 9'd64,
	parameter [8:0] BaseAddrR6 = 9'd128,
	parameter [8:0] BaseAddrR7 = 9'd192
)
(
	input Clk_i,
	input Rst_i,
	input OscWind_i,
	output CoefDataVal_o,
	input [2:0]	DecimFactor_i,
	output [OutWidth-1:0] CoefAddr_o
);


//================================================================================
//	REG/WIRE
//================================================================================
reg	[2:0] decimFactor;
reg [OutWidth-1:0] currBaseAddr;
reg [OutWidth-1:0] currMaxAddr;
reg [8:0] coefAddr;

reg	changeFlag;
reg	coefDataVal;

//================================================================================
//	ASSIGNMENTS
//================================================================================
// assign changeFlag = (decimFactor!= DecimFactor_i);
assign CoefAddr_o = coefAddr;
assign CoefDataVal_o = coefDataVal;
	
//================================================================================
//	CODING
//================================================================================
always @(posedge Clk_i) begin
	if (!Rst_i) begin
		decimFactor <= DecimFactor_i;
	end else begin
		decimFactor <= 0;
	end 
end

always @(posedge Clk_i) begin
	if (!Rst_i) begin	
		if (decimFactor!= DecimFactor_i) begin
			changeFlag <= 1'b1;
		end else begin
			changeFlag <= 1'b0;
		end
	end else begin
		changeFlag <= 1'b0;
	end 
end

always @(posedge Clk_i) begin
	if (!Rst_i) begin
		if (changeFlag) begin
			coefDataVal <= 1'b1;
		end 
		// if (coefAddr==currBaseAddr+63) begin
		if (coefAddr==currMaxAddr) begin
			coefDataVal <= 1'b0;
		end
	end else begin
		coefDataVal <= 1'b0;
	end 
end

always @(posedge Clk_i) begin
	if (!Rst_i) begin
		case (DecimFactor_i) 
			2:	begin
					currMaxAddr <= 0+Offset;
				end
			4:	begin
					currMaxAddr <= 0+Offset;
				end
			6:	begin
					currMaxAddr <= 0+Offset;
				end
			7:	begin
					currMaxAddr <= 0+Offset;
				end
		endcase
	end else begin
		currMaxAddr <= 0;
	end 
end 

// always @(posedge Clk_i) begin
	// if (!Rst_i) begin
		// if (changeFlag) begin
			// case (DecimFactor_i) 
				// 1:	begin
						// currBaseAddr <= 9'd0;
					// end
				// 2:	begin
						// currBaseAddr <= 9'd0;
					// end
				// 3:	begin
						// currBaseAddr <= 9'd64;
					// end
				// 4:	begin
						// currBaseAddr <= BaseAddrR4;
					// end
				// 5:	begin
						// currBaseAddr <= BaseAddrR5;
					// end
				// 6:	begin
						// currBaseAddr <= BaseAddrR6;
					// end
				// 7:	begin
						// currBaseAddr <= BaseAddrR7;
					// end
			// endcase
		// end
	// end else begin
		// currBaseAddr <= 0;
	// end 
// end 

always @(posedge Clk_i) begin
	if (!Rst_i) begin
		if (coefDataVal) begin
			coefAddr<=coefAddr+1;
		end else begin
			case (DecimFactor_i) 
				2:	begin
						coefAddr <= BaseAddrR2;
					end
				4:	begin
						coefAddr <= BaseAddrR2;
					end
				6:	begin
						coefAddr <= BaseAddrR2;
					end
				7:	begin
						coefAddr <= BaseAddrR2;
					end
			endcase
		end 
	end else begin
		coefAddr <=0;
	end 
end

endmodule
