module intFilterBlock 
#(	
	parameter	InDataWidth	=	18,
	parameter	OutDataWidth	=	25
)
(
	input Clk_i,
	input Rst_i,
	input [InDataWidth-1:0] Data_i,
	input DataNd_i,
	output [OutDataWidth-1:0] Data_o,
	output DataValid_o
);

	reg [1:0] ndShReg;
	
	always @ (posedge Clk_i)	begin
		if	(!Rst_i)	begin
			ndShReg <= {ndShReg[0:0], DataNd_i};
		end	else	begin
			ndShReg <= 2'h0;
		end
	end
	
	reg signed [InDataWidth-1:0] inReg;
	reg signed [OutDataWidth-1:0] sumResult;
	
	always	@(posedge	Clk_i)	begin
		if (!Rst_i)	begin
			if (DataNd_i)	begin
				inReg <= Data_i;
			end
		end	else	begin
			inReg	<= 0;
		end
	end
	
	always @ (posedge Clk_i)	begin
		if (!Rst_i)	begin
			if (ndShReg[0])	begin
				sumResult <= inReg + sumResult;
			end	else	begin
				sumResult <= 0;
			end
		end	else	begin
			sumResult	<=	0;
		end
	end

	assign Data_o = sumResult;
	assign DataValid_o = ndShReg[1];

endmodule