`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:02:35 04/20/2020 
// Design Name: 
// Module Name:    SimpleMult 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module	SimpleMult	
#(	
	parameter	FactorAWidth	=	14,
	parameter	FactorBWidth	=	14,
	parameter	OutputWidth		=	18
)	
(
	input	Rst_i,
	input	Clk_i,
	input	Val_i,
	input	signed	[FactorAWidth-1:0]	FactorA_i,
	input	signed	[FactorBWidth-1:0]	FactorB_i,
	
	
	output	signed	[OutputWidth-1:0]	Result_o,
	output	ResultVal_o
);

//================================================================================
//  LOCALPARAM
	localparam	ResultWidth	=	FactorAWidth+FactorBWidth;
//================================================================================
//  REG/WIRE
	reg	[ResultWidth-1:0]	resultReg;
	reg	resultValReg;
//================================================================================
//  ASSIGNMENTS
	assign	Result_o	=	(ResultWidth==OutputWidth)?	resultReg:resultReg[ResultWidth-2-:OutputWidth];
	assign	ResultVal_o	=	resultValReg;
//================================================================================
//  CODING
	always	@(posedge	Clk_i)	begin
		if	(!Rst_i)	begin
			if	(Val_i)	begin
				resultReg		<=	FactorA_i*FactorB_i;
				resultValReg	<=	Val_i;
			end	else	begin
				resultReg		<=	{ResultWidth{1'b0}};
				resultValReg	<=	1'b0;
			end
		end	else	begin
			resultReg		<=	{ResultWidth{1'b0}};
			resultValReg	<=	1'b0;
		end
	end
endmodule
