`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:		Churbanov S.
// 
// Create Date:    10:00:14 13/08/2019 
// Design Name: 
// Module Name:    DspPpiOut 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module DitherGenv2
#(	
	parameter	CmdDataRegWith		=	24,
	parameter	FrAmpWordWidth		=	8,
	parameter	RefFreqDiv			=	5
)
(
	input	Rst_i,
	input	Clk_i,	
	
	input	[CmdDataRegWith-1:0]	DitherCmd_i,
	output	DitherCtrlT2R2_o,
	output	DitherCtrlT1R1_o
);
//================================================================================
//  REG/WIRE
//================================================================================
	
	wire	[FrAmpWordWidth-1:0]	ditherFreq	=	DitherCmd_i[CmdDataRegWith-1-:FrAmpWordWidth];
	
	wire	[4-1:0]	ditherAmpT2R2	=	DitherCmd_i[15:12];
	wire	[4-1:0]	ditherAmpT1R1	=	DitherCmd_i[11:8];
	wire	[4-1:0]	rampLimit		=	DitherCmd_i[7:4];
	
	wire	ditherEnT2R2	=	DitherCmd_i[1];
	wire	ditherEnT1R1	=	DitherCmd_i[0];
	
	wire	[3:0]	ncoArray	[15:0];
	
	assign	ncoArray	[0]		=	0;
	assign	ncoArray	[1]		=	1;
	assign	ncoArray	[2]		=	2;
	assign	ncoArray	[3]		=	3;
	assign	ncoArray	[4]		=	4;
	assign	ncoArray	[5]		=	5;
	assign	ncoArray	[6]		=	6;
	assign	ncoArray	[7]		=	7;
	assign	ncoArray	[8]		=	8;
	assign	ncoArray	[9]		=	7;
	assign	ncoArray	[10]	=	6;
	assign	ncoArray	[11]	=	5;
	assign	ncoArray	[12]	=	4;
	assign	ncoArray	[13]	=	3;
	assign	ncoArray	[14]	=	2;
	assign	ncoArray	[15]	=	1;
	
	reg	[3:0]	sawCnt;
	
	reg	[FrAmpWordWidth-1:0]	currStateT2R2;
	reg	[FrAmpWordWidth-1:0]	currStateT1R1;
	
	wire	[3:0]	ncoSignalT2R2	=	ncoArray[currStateT2R2[FrAmpWordWidth-1-:4]];
	wire	[3:0]	ncoSignalT1R1	=	ncoArray[currStateT1R1[FrAmpWordWidth-1-:4]];

	wire	dithGenT2R2	=	((ncoSignalT2R2>>ditherAmpT2R2)>sawCnt)	?	1'b1:1'b0;
	wire	dithGenT1R1	=	((ncoSignalT1R1>>ditherAmpT1R1)>sawCnt)	?	1'b1:1'b0;
//================================================================================
//  ASSIGNMENTS
//================================================================================	
	assign	DitherCtrlT2R2_o	=	(ditherEnT2R2)	?	dithGenT2R2:1'b0;
	assign	DitherCtrlT1R1_o	=	(ditherEnT1R1)	?	dithGenT1R1:1'b0;
//================================================================================
//  CODING
//================================================================================	

always	@(posedge	Clk_i)	begin
	if	(!Rst_i)	begin
		if	(sawCnt	!=	rampLimit)	begin
			sawCnt	<=	sawCnt	+1;
		end	else	begin
			sawCnt	<=	0;
		end
	end	else	begin
		sawCnt	<=	0;
	end
end

wire	Clk5=(sawCnt<=10/2-1)?	1'b1:1'b0;

always	@(posedge	Clk_i)	begin
	if	(!Rst_i)	begin
		if	(sawCnt	==rampLimit)	begin
			currStateT2R2	<=	currStateT2R2+ditherFreq;
			currStateT1R1	<=	currStateT1R1+ditherFreq;
		end
	end	else	begin
		currStateT2R2	<=0;
		currStateT1R1	<=0;
	end
end


endmodule


















