Тестовые изменения.

src/src/FftDataFiltering/DecimFilterWrapper.v

@@ -48,12 +48,13 @@ module	DecimFilterWrapper
 //================================================================================
 //	REG/WIRE
 //================================================================================
-	wire	signed	[FilteredDataWidth-1:0]	decimDataI;
-	wire	signed	[FilteredDataWidth-1:0]	decimDataQ;
-	wire	decimDataValI;
-	reg		decimDataValIR;
-	wire	decimDataValQ;
-	reg		decimDataValQR;
+	wire	signed	[FilteredDataWidth-1:0]	filteredData;
+	wire	signed	[FilteredDataWidth-1:0]	decimData;
+	
+	wire	filteredDataVal;
+	wire	decimDataVal;
+	
+	reg		decimDataValR;
 	
 	wire	signed	[FirOutDataWidth-1:0]	firDataOut;
 	wire	firDataOutVal;
@@ -70,37 +71,21 @@ module	DecimFilterWrapper
 	reg		[24-1:0]	ifFtwHReg;
 	
 	reg		[15:0]	outDataI;
-	reg		[15:0]	outDataQ;
 	
 	localparam	extendBitNum	=	FilteredDataWidth-AdcDataWidth;
 	
-	// localparam	maxWidthForR1	=	10'd16;	//msb for R = 2;
-	// localparam	maxWidthForR2	=	10'd16;	//msb for R = 2;
-	// localparam	maxWidthForR3	=	10'd26;	//msb for R = 3;
-	// localparam	maxWidthForR4	=	10'd30;	//msb for R = 4;
-	// localparam	maxWidthForR5	=	10'd31;	//msb for R = 5;
-	// localparam	maxWidthForR6	=	10'd33;	//msb for R = 6;
-	// localparam	maxWidthForR7	=	10'd34;	//msb for R = 7;
-	// localparam	maxWidthForR8	=	5'd26;	//msb for R = 8;
-	// localparam	maxWidthForR9	=	5'd27;	//msb for R = 9;
-	// localparam	maxWidthForR10	=	5'd28;	//msb for R = 10;
-	
 	wire	[39:0]	firData;
 	wire	firDataVal;
 	wire	bypassData = (DecimFactor_i==3'd0 | DecimFactor_i==3'd1);
+	
+	wire	[17:0]	adcExtData	=	{{extendBitNum{AdcData_i[AdcDataWidth-1]}},AdcData_i};
 //================================================================================
 //	ASSIGNMENTS
 //================================================================================
 
 	assign	FilteredAdcDataI_o	=	outDataI;
-	// assign	FilteredAdcDataI_o	=	(bypassData)?{{2{AdcData_i[AdcDataWidth-1]}},AdcData_i}:firData[33-:16];
-	// assign	FilteredAdcDataI_o	=	(bypassData)?{{2{AdcData_i[AdcDataWidth-1]}},AdcData_i}:firData[33-:16];
 
-	assign	FilteredDataVal_o	=	decimDataValIR;
-	// assign	FilteredDataVal_o	=	(bypassData)?1'b1:firDataVal;
-
-
-// {{14{AdcData_i[AdcDataWidth-1]}},AdcData_i}
+	assign	FilteredDataVal_o	=	decimDataValR;
 
 //================================================================================
 //	CODING
@@ -110,72 +95,97 @@ always	@(posedge	Clk_i)	begin
 	if	(!Rst_i)	begin
 		case(DecimFactor_i)
 			3'd0:	begin
-						outDataI		<=	decimDataI[LsbForR1-1-:16];
-						decimDataValIR	<=	OscWind_i;
+						outDataI		<=	adcExtData[LsbForR1-1-:16];
+						decimDataValR	<=	OscWind_i;
 					end
 			3'd1:	begin
-						outDataI		<=	decimDataI[LsbForR1-1-:16];
-						decimDataValIR	<=	OscWind_i;
+						outDataI		<=	adcExtData[LsbForR1-1-:16];
+						decimDataValR	<=	OscWind_i;
 					end
 			3'd2:	begin
-						outDataI		<=	decimDataI[LsbForR2-1-:16];
-						decimDataValIR	<=	decimDataValI;
+						outDataI		<=	decimData[LsbForR2-1-:16];
+						decimDataValR	<=	decimDataVal;
 					end
 			// 3'd3:	begin
-						// outDataI	<=	decimDataI[maxWidthForR3-1-:16];
-						// decimDataValIR	<=	decimDataValI;
+						// outDataI	<=	decimData[maxWidthForR3-1-:16];
+						// decimDataValR	<=	decimDataVal;
+					// end
+			// 3'd4:	begin
+						// outDataI	<=	decimDataI[LsbForR4-1-:16];
+						// decimDataValR	<=	decimDataVal;
 					// end
-			3'd4:	begin
-						outDataI	<=	decimDataI[LsbForR4-1-:16];
-						decimDataValIR	<=	decimDataValI;
-					end
 			// 3'd5:	begin
 						// outDataI	<=	decimDataI[maxWidthForR5-1-:16];
-						// decimDataValIR	<=	decimDataValI;
+						// decimDataValR	<=	decimDataVal;
 					// end
 			// 3'd6:	begin
 						// outDataI	<=	decimDataI[maxWidthForR6-1-:16];
-						// decimDataValIR	<=	decimDataValI;
+						// decimDataValR	<=	decimDataVal;
 					// end
 			// 3'd7:	begin
 						// outDataI	<=	decimDataI[maxWidthForR7-:16];
-						// decimDataValIR	<=	decimDataValI;
+						// decimDataValR	<=	decimDataVal;
 					// end
 		endcase
 	end	else	begin
 		outDataI	<=	16'd0;
-		decimDataValIR	<=	1'b0;
+		decimDataValR	<=	1'b0;
 	end
 end
 
-cicFilter 
-#(
-	.N (N),	//filter order
-	.M (M),	//comb delay
-	.filteredDataWidth	(FilteredDataWidth),
-	.inOutDataWidth		(FilteredDataWidth),
-	.decimCntWidth		(7)
-)
-cicFilterInstI
-(
-	.Clk_i			(Clk_i),
-	.Rst_i			(Rst_i),
-	.DecimFactor_i	(DecimFactor_i),
-	.Data_i			({{extendBitNum{AdcData_i[AdcDataWidth-1]}},AdcData_i}),
-	.DataNd_i		(OscWind_i),
-	.Data_o			(decimDataI),
-	.DataValid_o	(decimDataValI)
-);
+// cicFilter 
+// #(
+	// .N (N),	//filter order
+	// .M (M),	//comb delay
+	// .filteredDataWidth	(FilteredDataWidth),
+	// .inOutDataWidth		(FilteredDataWidth),
+	// .decimCntWidth		(7)
+// )
+// cicFilterInstI
+// (
+	// .Clk_i			(Clk_i),
+	// .Rst_i			(Rst_i),
+	// .DecimFactor_i	(DecimFactor_i),
+	// .Data_i			({{extendBitNum{AdcData_i[AdcDataWidth-1]}},AdcData_i}),
+	// .DataNd_i		(OscWind_i),
+	// .Data_o			(decimDataI),
+	// .DataValid_o	(decimDataVal)
+// );
 
 // FirFilter FirFilter (
   // .aclk(Clk_i),                              // input wire aclk
-  // .s_axis_data_tvalid(decimDataValI),  // input wire s_axis_data_tvalid
+  // .s_axis_data_tvalid(decimDataVal),  // input wire s_axis_data_tvalid
   // .s_axis_data_tready(),  // output wire s_axis_data_tready
   // .s_axis_data_tdata(outDataI),    // input wire [15 : 0] s_axis_data_tdata
   // .m_axis_data_tvalid(firDataVal),  // output wire m_axis_data_tvalid
   // .m_axis_data_tdata(firData)    // output wire [39 : 0] m_axis_data_tdata
 // );
 
+systolicFilter DataFitler (
+	.Clk_i(Clk_i), 
+	.Rst_i(Rst_i), 
+	.Data_i(adcExtData), 
+	.DataNd_i(OscWind_i), 
+	.Data_o(filteredData), 
+	.DataValid_o(filteredDataVal)
+);
+
+decimBlock
+		#(	
+			// .R	(R),
+			.inOutDataWidth	(18),
+			.decimCntWidth	(7)
+		)
+		decimBlockInst
+		(
+			.Clk_i			(Clk_i),
+			.Rst_i			(Rst_i),
+			.DecimFactor_i	(DecimFactor_i),
+			.Data_i			(filteredData),
+			.DataNd_i		(filteredDataVal),
+			.Data_o			(decimData),
+			.DataValid_o	(decimDataVal)
+		);	
 endmodule
 
 

src/src/Sim/2.fcf

@@ -0,0 +1,41 @@
+ 0.001669973527045805162735692128705977666
+ 0.003822843768714379725226493178524833638
+ 0.001817411213731041658842046970789851912
+-0.008022518245003116069136162025188241387
+-0.019657467724595128338860305916568904649
+-0.019030189485440794638915207315221778117
+-0.001260349664285260497254004263822935172
+ 0.016329483803820474263623907518194755539
+ 0.009997707699713521273254812626873899717
+-0.016748297651786127338002785336357192136
+-0.027779042621074830771155106390324363019
+ 0.001657732400108380757530746052452741424
+ 0.040905392498605634699071487148103187792
+ 0.029301489104951158881640083109232364222
+-0.040239957946682475276034551825432572514
+-0.082553095234012330294603998481761664152
+ 0.001556266751016749383396131634071934968
+ 0.200779997614156435759014129871502518654
+ 0.372646835385944730223428678073105402291
+ 0.372646835385944730223428678073105402291
+ 0.200779997614156435759014129871502518654
+ 0.001556266751016749383396131634071934968
+-0.082553095234012330294603998481761664152
+-0.040239957946682475276034551825432572514
+ 0.029301489104951158881640083109232364222
+ 0.040905392498605634699071487148103187792
+ 0.001657732400108380757530746052452741424
+-0.027779042621074830771155106390324363019
+-0.016748297651786127338002785336357192136
+ 0.009997707699713521273254812626873899717
+ 0.016329483803820474263623907518194755539
+-0.001260349664285260497254004263822935172
+-0.019030189485440794638915207315221778117
+-0.019657467724595128338860305916568904649
+-0.008022518245003116069136162025188241387
+ 0.001817411213731041658842046970789851912
+ 0.003822843768714379725226493178524833638
+ 0.001669973527045805162735692128705977666
+
+                                         
+

src/src/Sim/BitWidthCalc.m

@@ -0,0 +1,28 @@
+N = 2;
+R = 2;
+B = 16;
+M = 1;
+FormatSpecR = '%f';
+FormatSpecW = '%X\n';
+##FormatSpecW = '%h\n';
+
+
+
+Bmax = ceil(log2(((R*M)^N)/R)+B);
+MaxWidthR2 = ceil(log2(((2*M)^N)/2)+B);
+MaxWidthR4 = ceil(log2(((4*M)^N)/4)+B);
+
+ReadFilterCoefsId = fopen('C:\S5243_FFT_REPO\src\src\Sim\2.fcf','r');
+FilterCoefs = fscanf(ReadFilterCoefsId,FormatSpecR);
+fclose(ReadFilterCoefsId);
+
+CorrValue = 2^17;
+
+CorrCoeffs = FilterCoefs*CorrValue;
+CorrCoeffs = dec2hex(int32(CorrCoeffs));
+
+
+WriteFilterCoefsId = fopen('C:\S5243_FFT_REPO\src\src\Sim\untitled.txt','w');
+fprintf(WriteFilterCoefsId, CorrCoeffs);
+fclose(WriteFilterCoefsId);
+

src/src/Sim/DecimFilterWrapperTb.v

@@ -36,28 +36,33 @@ wire	signed	[27:0]	adcDataMixed	=	(ncoSin1*ncoSin2);
 wire	signed	[13:0]	adcDataMixedCut	=	adcDataMixed[26-:14];
 
 // wire	signed	[13:0]	sinAdd	=	(ncoSin1>>>2)+(ncoSin2>>>2)+(ncoSin3>>>2);
-// wire	signed	[13:0]	sinAdd	=	(ncoSin1>>>1)+(ncoSin2>>>1);
-wire	signed	[13:0]	sinAdd	=	(ncoSin1);
+wire	signed	[13:0]	sinAdd	=	(ncoSin1>>>1)+(ncoSin2>>>1);
+// wire	signed	[13:0]	sinAdd	=	ncoSin1;
+wire	signed	[15:0]	sinAddExt16	=	{{2{ncoSin2[14-1]}},ncoSin2};
+wire	signed	[17:0]	sinAddExt18	=	{{4{sinAdd[14-1]}},sinAdd};
 
 reg		signed	[13:0]	currTestData;
 
 wire	signed	[17:0]	wind;
 
 // wire	signed	[13:0]	singlePulse	=	(tbCnt>=4500&tbCnt<=4550)?	14'h1fff:14'h0;
-wire	signed	[13:0]	singlePulse	=	(tbCnt==4500)?	14'h1fff:14'h0;
+wire	signed	[13:0]	singlePulse	=	(tbCnt==4550)?	14'h1fff:14'h0;
+wire	signed	[17:0]	singlePulseExt	=	(tbCnt==4500)?	18'h1ffff:14'h0;
+// wire	signed	[15:0]	singlePulseExt	=	(tbCnt>=4500&tbCnt<=4501)?	16'h7fff:14'h0;
+wire	inglePulseExtVal	=	(tbCnt==4500)?	1:0;
 //==========================================================================================
 //clocks gen
 always	#10 Clk50	=	~Clk50;
 
 //==========================================================================================
-parameter	N	=	1;
+parameter	N	=	4;
 parameter	M	=	1;
 
-parameter	MaxWidth	=	16;
+parameter	MaxWidth	=	18;
 
-parameter	LsbForR1	=	10'd16;
-parameter	LsbForR2	=	10'd16;
-parameter	LsbForR4	=	10'd16;
+parameter	LsbForR1	=	10'd18;
+parameter	LsbForR2	=	10'd18;
+parameter	LsbForR4	=	10'd18;
 	
 parameter	[31:0]	Nco1PhaseInc	=	32'h0f5c28f5;	
 parameter	[31:0]	Nco2PhaseInc	=	32'h428f5c28;	
@@ -261,56 +266,52 @@ always	@(posedge	Clk50)	begin
 	end
 end
 	
-reg	signed	[33:0]	windResult;
-reg	windResultVal;
 
-always	@(posedge	Clk50)	begin
-	if	(!Rst)	begin
-		if	(valReg[1])	begin
-			windResult	<=	wind*filteredDataOut;
-			windResultVal	<=	1'b1;
-		end	else	begin
-			windResultVal	<=	1'b0;
-		end
-	end	else	begin
-		windResult	<=	0;
-		windResultVal	<=	0;
-	end
-end
-
-wire	signed	[15:0]	windResultCut	=	windResult[32-:16];
-
-// Win_calc	WinCalcInst
-// (
-	// .clk_i			(Clk50),
-	// .filterCmd_i	(8'h60),
-	// .reset_i		(Rst),
-	// .WinCtrl_i		(1'b0),
-	// .TukeyCtrl_i	(2'b0),
-	// .MeasWind_i		(resultVal),
-	// .win_value_i	(windArg),
-	// .win_type_i		(3'b0),
-	// .win_o			(wind)
-// );
 
 integer inSignal,filteredData, impResp;
 parameter	PNum	=	5000;
 
+wire	signed	[17:0]	firDataOut;
+wire	signed	[17:0]	firRespout;
+wire	firDataVal;
+wire	firRespVal;
+
+systolicFilter DataFitler (
+	.Clk_i(Clk50), 
+	.Rst_i(Rst), 
+	.Data_i(sinAddExt18), 
+	.DataNd_i(oscWind), 
+	.Data_o(firDataOut), 
+	.DataValid_o(firDataVal)
+);
+
+systolicFilter RespFilter (
+	.Clk_i(Clk50), 
+	.Rst_i(Rst), 
+	.Data_i(singlePulseExt), 
+	.DataNd_i(oscWind), 
+	.Data_o(firRespout), 
+	.DataValid_o(firRespVal)
+);
+
+
+
 always	@(posedge	Clk50)	begin
 	if	(Rst)	begin
 		inSignal = $fopen("C:/S5243_FFT_REPO/src/src/Sim/InputSignal.txt","w");
 	end	else	begin
 		if	(oscWind)	begin
 			// $display("AdcData is %d", sinAdd);
-			$fwrite(inSignal,"%d\n",   sinAdd);
-			// $fwrite(inSignal,"%d\n",   adcDataMixedCut);
+			$fwrite(inSignal,"%d\n",   sinAddExt18);
+			// $fwrite(inSignal,"%d\n",   sinAdd);
 		end	
 	end	
 end
 
 reg	[31:0]	testCnt;
 wire	[10:0]	test = N*2+N*2+decimFactor;
-wire	writeEn	=	(oscWindDelay[N*2+N*2+decimFactor-1]);
+wire	[10:0]	test1 = N*2+N*2+decimFactor-1;
+wire	writeEn	=	(oscWindDelay[N*2+N*2+decimFactor]);
 
 always	@(posedge	Clk50)begin
 	if	(!Rst)	begin
@@ -326,8 +327,9 @@ always	@(posedge	Clk50)	begin
 	if	(Rst)	begin
 		filteredData = $fopen("C:/S5243_FFT_REPO/src/src/Sim/FilteredData.txt","w");
 	end	else	begin
-		if	(writeEn)	begin
-			$fwrite(filteredData,"%d\n",   filteredDataOut);
+		if	(firDataVal)	begin
+			// $fwrite(filteredData,"%d\n",   filteredDataOut);
+			$fwrite(filteredData,"%d\n",   firDataOut);
 		end	
 	end	
 end
@@ -337,8 +339,9 @@ always	@(posedge	Clk50)	begin
 	if	(Rst)	begin
 		impResp = $fopen("C:/S5243_FFT_REPO/src/src/Sim/ImpResp.txt","w");
 	end	else	begin
-		if	(writeEn)	begin
-			$fwrite(impResp,"%d\n",   impResponse);
+		if	(firDataVal)	begin
+			$fwrite(impResp,"%d\n",   firRespout);
+			// $fwrite(impResp,"%d\n",   m_axis_data_tdata_imp);
 		end	
 	end
 end 

src/src/Sim/FFTTest.m

@@ -1,12 +1,11 @@
 FormatSpec = '%d';
 
-N = 2;
+N = 4;
 R = 2;
 B = 16;
 M = 1;
 
 PointsNum = 2000;
-FilteredDataPNum    =   PointsNum/R;
 
 Bmax = ceil(log2(((R*M)^N)/R)+B)
 MaxWidthR2 = ceil(log2(((2*M)^N)/2)+B)
@@ -15,6 +14,8 @@ MaxWidthR4 = ceil(log2(((4*M)^N)/4)+B)
 
 x = 1:1:PointsNum;
 xDecim = 1:1:PointsNum/R;
+
+Fc = 3;
 Fs = 50;
 
 #########################################################################################################################
@@ -44,13 +45,20 @@ InDataFft = abs(fft(InDataSignal+randn(size(InDataSignal)))/PointsNum);
 InDataFftDb = 20*log10(InDataFft);
 
 FilteredDataFft = abs(fft(FilteredData+randn(size(FilteredData)))/PointsNum);
+##FilteredDataFft = abs(fft(FilteredData)/PointsNum);
 FilteredDataFftDb = 20*log10(FilteredDataFft);
+FilteredDataFftDb = FilteredDataFftDb-max(FilteredDataFftDb);
 
 ImpuseRespFft = abs(fft(ImpulseResp));
 ImpuseRespFftDb = 20*log10(ImpuseRespFft);
 ImpuseRespFftDb = ImpuseRespFftDb-max(ImpuseRespFftDb);
 
+Fband = 0:1/PointsNum:1-1/PointsNum;
+##Fband = 0:1/PointsNum:0.5-1/PointsNum;
 
+##InDataFftDb = InDataFftDb(1:length(Fband));
+##FilteredDataFftDb = FilteredDataFftDb(1:length(Fband));
+##ImpuseRespFftDb = ImpuseRespFftDb(1:length(Fband));
 
 #########################################################################################################################
 ##figure('name','In Data Time/Freq', 'Numbertitle', 'off')
@@ -63,7 +71,7 @@ ImpuseRespFftDb = ImpuseRespFftDb-max(ImpuseRespFftDb);
 ##ylabel("Amp")
 ##
 ##subplot(2,1,2)
-##plot(FreqBandOrig,InDataFftDb)
+##plot(Fband,InDataFftDb)
 ##grid on;
 ##grid minor;
 ##title("Single-Sided Amplitude Spectrum of InData")
@@ -72,7 +80,7 @@ ImpuseRespFftDb = ImpuseRespFftDb-max(ImpuseRespFftDb);
 
 figure('name','Frequency compare', 'Numbertitle', 'off')
 subplot(3,1,1)
-plot(FreqBandOrig,InDataFftDb)
+plot(Fband,InDataFftDb)
 grid on;
 grid minor;
 ##axis([0 25 -70 80]);
@@ -81,7 +89,7 @@ xlabel("Time")
 ylabel("Amp")
 
 subplot(3,1,2)
-plot(FreqBandOrig,ImpuseRespFftDb)
+plot(Fband,ImpuseRespFftDb)
 grid on;
 grid minor;
 ##axis([0 50 -60 1]);
@@ -90,7 +98,7 @@ xlabel("f (Hz)")
 ylabel("Amp")
 
 subplot(3,1,3)
-plot(FreqBandOrig,FilteredDataFftDb)
+plot(Fband,FilteredDataFftDb)
 grid on;
 grid minor;
 ##axis([0 25 -70 80]);
@@ -108,7 +116,7 @@ ylabel("Amp")
 ##ylabel("Amp")
 ##
 ##subplot(2,1,2)
-##plot(Freqs,ImpuseRespFftDb)
+##plot(Fband,ImpuseRespFftDb)
 ##grid on;
 ##grid minor;
 ##title("Single-Sided Amplitude Spectrum of InData")

src/src/Sim/KapitanovScriptForCicComp.m

@@ -177,11 +177,11 @@ figure('name','CIC/FIR Frequency Response', 'Numbertitle', 'off')
   plot(ff, HCICdb - max(HCICdb), '-.', 'LineWidth', 2, 'Color',[0 0 1]);
   hold on;
 
-  plot(ff, H_amp, '--', 'LineWidth', 2, 'Color',[0 0.4 0]);
-  hold on;
-
-  plot(ff, H_comp, '-', 'LineWidth', 2, 'Color',[1 0 0]);
-  hold on;
+##  plot(ff, H_amp, '--', 'LineWidth', 2, 'Color',[0 0.4 0]);
+##  hold on;
+##
+##  plot(ff, H_comp, '-', 'LineWidth', 2, 'Color',[1 0 0]);
+##  hold on;
 
   title([{'CIC, Comp. FIR and Result'};{sprintf('Filter Order = %i, Coef. width = %i',NFIR,Bc)}]);
   xlabel ('Freq (\pi x rad / samples)');

src/src/Sim/firFilter/roundSymmetric .v

@@ -0,0 +1,36 @@
+module roundSymmetric #
+( 
+	parameter inDataWidth = 35,
+	parameter outDataWidth = 17
+)
+(
+	input Rst_i,
+	input Clk_i,
+	input [inDataWidth-1 : 0] Data_i,
+	input DataNd_i,
+	output [outDataWidth-1 : 0] Data_o,
+	output DataValid_o
+);
+	
+	parameter [inDataWidth-1 : 0] addPositive = 2**(inDataWidth-outDataWidth-1);
+	parameter [inDataWidth-1 : 0] addNegative = 2**(inDataWidth-outDataWidth-1)-1;
+	
+	reg [inDataWidth-1 : 0] corrData;
+	always @ (posedge Clk_i or posedge Rst_i)
+		if (Rst_i)
+			corrData <= 0;
+		else if (DataNd_i)
+			begin
+				if (Data_i[inDataWidth-1])
+					corrData <= Data_i + addNegative;
+				else 
+					corrData <= Data_i + addPositive;
+			end
+			
+	assign Data_o = corrData[inDataWidth-1 : inDataWidth-outDataWidth];
+	
+	reg outDataValidReg;
+	always @ (posedge Clk_i) outDataValidReg <= DataNd_i;
+	assign DataValid_o = outDataValidReg;
+
+endmodule

src/src/Sim/firFilter/systolicFilter.v

@@ -0,0 +1,48 @@
+module systolicFilter
+#(	parameter	filteredDataWidth	=	38,
+	parameter	inOutDataWidth	=	18,
+	parameter	decimCntWidth	=	7,
+	parameter	CoeffCount		=	38
+)
+(
+	input Clk_i,
+	input Rst_i,
+	input [inOutDataWidth-1:0] Data_i,
+	input DataNd_i,
+	output [inOutDataWidth-1:0] Data_o,
+	output DataValid_o
+);
+
+	wire [47:0] outData;
+	wire outDataValid;
+	systolicFilterBlock # (
+		.CoeffCount(CoeffCount)
+	)
+	systolicFilterBlockInst
+	(
+		.Clk_i(Clk_i),
+		.Rst_i(Rst_i),
+		.Data_i(Data_i),
+		.DataNd_i(DataNd_i),
+		.Data_o(outData),
+		.DataValid_o(outDataValid)
+	);
+	
+	wire dataValid;
+	roundSymmetric #
+	( 
+		.inDataWidth(filteredDataWidth),
+		.outDataWidth(inOutDataWidth)
+	)
+	roundInst
+	(
+		.Rst_i(Rst_i),
+		.Clk_i(Clk_i),
+		.Data_i(outData[37:0]),
+		.DataNd_i(outDataValid),
+		.Data_o(Data_o),
+		.DataValid_o(DataValid_o)
+	);
+
+
+endmodule

src/src/Sim/firFilter/systolicFilterBlock.v

@@ -0,0 +1,126 @@
+module systolicFilterBlock # (
+	parameter CoeffCount = 25
+)
+(
+	input Clk_i,
+	input Rst_i,
+	input [17:0] Data_i,
+	input DataNd_i,
+	output [47:0] Data_o,
+	output DataValid_o
+);
+
+	wire signed [17:0] coeff[0:CoeffCount-1];
+
+	// assign coeff[0] = 18'h3e6c9;
+	// assign coeff[1] = 18'h3c349;
+	// assign coeff[2] = 18'h3cfde;
+	// assign coeff[3] = 18'h3f440;
+	// assign coeff[4] = 18'h05e4b;
+	// assign coeff[5] = 18'h0e79f;
+	// assign coeff[6] = 18'h172aa;
+	// assign coeff[7] = 18'h1c760;
+	// assign coeff[8] = 18'h1c760;
+	// assign coeff[9] = 18'h172aa;
+	// assign coeff[10] = 18'h0e79f;
+	// assign coeff[11] = 18'h05e4b;
+	// assign coeff[12] = 18'h3f440;
+	// assign coeff[13] = 18'h3cfde;
+	// assign coeff[14] = 18'h3c349;
+	// assign coeff[15] = 18'h3e6c9;	
+	
+	assign coeff[0]  = 18'h000db;
+	assign coeff[1]  = 18'h001f5;
+	assign coeff[2]  = 18'h000ee;
+	assign coeff[3]  = 18'h3fbe4;
+	assign coeff[4]  = 18'h3f5ef;
+	assign coeff[5]  = 18'h3f642;
+	assign coeff[6]  = 18'h3ff5b;
+	assign coeff[7]  = 18'h0085c;
+	assign coeff[8]  = 18'h0051e;
+	assign coeff[9]  = 18'h3f76d;
+	assign coeff[10] = 18'h3f1c7;
+	assign coeff[11] = 18'h000d9;
+	assign coeff[12] = 18'h014f2;
+	assign coeff[13] = 18'h00f01;
+	assign coeff[14] = 18'h3eb66;
+	assign coeff[15] = 18'h3d5bc;
+	assign coeff[16] = 18'h000cc;
+	assign coeff[17] = 18'h066cd;
+	assign coeff[18] = 18'h0becc;
+	assign coeff[19] = 18'h0becc;
+	assign coeff[20] = 18'h066cd;
+	assign coeff[21] = 18'h000cc;
+	assign coeff[22] = 18'h3d5bc;
+	assign coeff[23] = 18'h3eb66;
+	assign coeff[24] = 18'h00f01;
+	assign coeff[25] = 18'h014f2;
+	assign coeff[26] = 18'h000d9;
+	assign coeff[27] = 18'h3f1c7;
+	assign coeff[28] = 18'h3f76d;
+	assign coeff[29] = 18'h0051e;
+	assign coeff[30] = 18'h0085c;
+	assign coeff[31] = 18'h3ff5b;
+	assign coeff[32] = 18'h3f642;
+	assign coeff[33] = 18'h3f5ef;
+	assign coeff[34] = 18'h3fbe4;
+	assign coeff[35] = 18'h000ee;
+	assign coeff[36] = 18'h001f5;
+	assign coeff[37] = 18'h000db;
+
+	wire signed [17:0] dataIn = Data_i;
+	reg [3:0] ndShReg;
+	
+	always @ (posedge Clk_i)
+		if (!Rst_i) begin
+			ndShReg <= {ndShReg[2:0], DataNd_i};
+		end else begin
+			ndShReg <= 4'h0;
+		end
+	
+	reg signed [17:0] inReg0[0:CoeffCount-1];
+	reg signed [17:0] inReg1[0:CoeffCount-1];
+	reg signed [34:0] multResult[0:CoeffCount-1];
+	reg signed [47:0] sumResult[0:CoeffCount-1];
+	
+	
+	genvar i;
+	generate
+		for (i = 0; i < CoeffCount; i = i + 1)begin 
+			always @ (posedge Clk_i) begin
+				if (!Rst_i) begin
+					if (DataNd_i) begin
+						if (i == 0) begin
+							inReg0[i] <= 0;
+							inReg1[i] <= dataIn;
+						end else begin
+							inReg0[i] <= inReg1[i-1];
+							inReg1[i] <= inReg0[i];
+						end
+					end
+				
+					if (ndShReg[0]) begin
+						multResult[i] <= inReg1[i] * coeff[i];
+					end
+					
+					if (ndShReg[1]) begin
+						if (i == 0) begin
+							sumResult[i] <= multResult[i];
+						end else begin
+							sumResult[i] <= multResult[i] + sumResult[i-1];
+						end
+					end
+				end else begin
+					sumResult[i] <= 0;
+					multResult[i] <= 0;
+					inReg0[i] <= 0;
+					inReg1[i] <= 0;
+				end
+			end 
+		end
+	endgenerate
+
+	assign Data_o = sumResult[CoeffCount-1];
+	assign DataValid_o = ndShReg[2];
+
+endmodule

src/src/Sim/firFilter/systolicFilterChirp_tb.v

@@ -0,0 +1,61 @@
+`timescale 1ps / 1ps
+module systolicFilterChirp_tb;
+
+	// Inputs
+	reg Clk_i;
+	reg [17:0] Data_i;
+	reg DataNd_i;
+
+	// Outputs
+	wire [17:0] Data_o;
+	wire DataValid_o;
+
+	// Instantiate the Unit Under Test (UUT)
+	systolicFilter uut (
+		.Clk_i(Clk_i), 
+		.Data_i(Data_i), 
+		.DataNd_i(DataNd_i), 
+		.Data_o(Data_o), 
+		.DataValid_o(DataValid_o)
+	);
+
+	initial begin
+		// Initialize Inputs
+		Clk_i = 0;
+		Data_i = 0;
+		DataNd_i = 0;
+
+		// Wait 100 ns for global reset to finish
+		#100;
+	end
+	
+	parameter period = 5000;
+	always # (period / 2) Clk_i <= ~Clk_i;
+	
+	integer simCnt = 0;
+	always @ (posedge Clk_i) simCnt <= simCnt + 1;
+	
+	real pi = 3.14159265358;
+	real phase = 0;
+	real phaseInc = 0.001;
+	real signal;
+	always @ (posedge Clk_i)
+		begin
+			DataNd_i <= 1;
+			if (simCnt >= 1000)
+				begin
+					phase = phase + phaseInc;
+					phaseInc <= phaseInc + 0.0005;
+					signal = $sin(2*pi*phase);
+					Data_i = 2**16 * signal;
+				end
+			else
+				Data_i = 0;
+		end
+			
+	reg [17:0] dataOutTest;
+	always @ (posedge Clk_i)
+		if (DataValid_o)
+			dataOutTest <= Data_o;		
+      
+endmodule

src/src/Sim/src/cicFilter/cicFilter.v

@@ -0,0 +1,93 @@
+module cicFilter 
+#(
+	parameter N = 4,	//filter order
+	parameter M = 1,	//comb delay
+	parameter R = 4,	//decim fartor
+	parameter	filteredDataWidth	=	26,
+	parameter	inOutDataWidth	=	18,
+	parameter	decimCntWidth	=	7
+)
+(
+	input Clk_i,
+	input [inOutDataWidth-1:0] Data_i,
+	input DataNd_i,
+	output [filteredDataWidth-1:0] Data_o,
+	output DataValid_o
+);
+	
+wire	[inOutDataWidth-1:0]	inData	[N-1:0];
+
+wire	[filteredDataWidth-1:0]	intFilteredData	[N-1:0];
+wire	intFilteredDataValid	[N-1:0];
+wire	intDataVal	[N-1:0];
+
+wire	[filteredDataWidth-1:0]	decimIntData;
+wire	decimIntDataValid;
+
+wire	[filteredDataWidth-1:0]	combFilteredData	[N-1:0];
+wire	[filteredDataWidth-1:0]	combInData	[N-1:0];
+wire	combDataVal	[N-1:0];
+wire	combFilteredDataVal	[N-1:0];
+
+genvar i,j;
+generate 
+	for (i=0; i<N; i=i+1)	begin: IntFilterGen
+	
+		assign	inData	[i]		=	(i==0)?Data_i:intFilteredData[i-1][filteredDataWidth-1-:inOutDataWidth];
+		assign	intDataVal[i]	=	(i==0)?DataNd_i:intFilteredDataValid[i-1];
+		
+		intFilterWrapper
+		#(
+			.filteredDataWidth	(filteredDataWidth),
+			.inOutDataWidth		(inOutDataWidth)
+		)
+		intFilterWrapperInst
+		(
+			.Clk_i		(Clk_i),
+			.Data_i		(inData[i]),
+			.DataNd_i	(intDataVal[i]),
+			.Data_o		(intFilteredData[i]),
+			.DataValid_o(intFilteredDataValid[i])
+		);
+	end
+	
+		decimBlock
+		#(	.R	(R),
+			.inOutDataWidth	(filteredDataWidth),
+			.decimCntWidth	(decimCntWidth)
+		)
+		decimBlockInst
+		(
+			.Clk_i			(Clk_i),
+			.Data_i			(intFilteredData[N-1]),
+			.DataNd_i		(intFilteredDataValid[N-1]),
+			.Data_o			(decimIntData),
+			.DataValid_o	(decimIntDataValid)
+		);	
+
+	
+	for (j=0; j<N; j=j+1)	begin: CombFilterGen
+	
+		assign	combInData	[j]	=	(j==0)?decimIntData:combFilteredData[j-1];
+		assign	combDataVal	[j]	=	(j==0)?decimIntDataValid:combFilteredDataVal[j-1];
+		
+		combFilterWrapper
+		#(
+			.M (M),
+			.filteredDataWidth	(filteredDataWidth),
+			.inOutDataWidth		(inOutDataWidth)
+		)
+		combFilterWrapperInst
+		(
+			.Clk_i		(Clk_i),
+			.Data_i		(combInData[j]),
+			.DataNd_i	(combDataVal[j]),
+			.Data_o		(combFilteredData[j]),
+			.DataValid_o(combFilteredDataVal[j])
+		);
+	end
+endgenerate
+
+assign	Data_o	=	combFilteredData[N-1];
+assign	DataValid_o	=	combFilteredDataVal[N-1];
+endmodule

src/src/Sim/src/cicFilter/cicFilterChirp_tb.v

@@ -0,0 +1,61 @@
+`timescale 1ps / 1ps
+
+module cicFilterChirp_tb;
+
+	// Inputs
+	reg Clk_i;
+	reg [17:0] Data_i;
+	reg DataNd_i;
+
+	// Outputs
+	wire [17:0] Data_o;
+	wire DataValid_o;
+
+	// Instantiate the Unit Under Test (UUT)
+	cicFilter uut (
+		.Clk_i(Clk_i), 
+		.Data_i(Data_i), 
+		.DataNd_i(DataNd_i), 
+		.Data_o(Data_o), 
+		.DataValid_o(DataValid_o)
+	);
+
+	initial begin
+		// Initialize Inputs
+		Clk_i = 0;
+		Data_i = 0;
+		DataNd_i = 0;
+		// Wait 100 ns for global reset to finish
+		#100;
+	end
+	
+	parameter period = 5000;
+	always # (period / 2) Clk_i <= ~Clk_i;
+	
+	integer simCnt = 0;
+	always @ (posedge Clk_i) simCnt <= simCnt + 1;
+	
+	real pi = 3.14159265358;
+	real phase = 0;
+	real phaseInc = 0.01;
+	real signal;
+	always @ (posedge Clk_i)
+		begin
+			DataNd_i <= 1;
+			if (simCnt >= 1000)
+				begin
+					phase = phase + phaseInc;
+					phaseInc <= phaseInc;
+					signal = $sin(2*pi*phase);
+					Data_i = 2**16 * signal;
+				end
+			else
+				Data_i = 0;
+		end
+			
+	reg [17:0] dataOutTest;
+	always @ (posedge Clk_i)
+		if (DataValid_o)
+			dataOutTest <= Data_o;	
+      
+endmodule

src/src/Sim/src/cicFilter/combFilterBlock.v

@@ -0,0 +1,52 @@
+module combFilterBlock 
+#(
+	parameter	M=4,
+	parameter	inOutDataWidth	=	18,
+	parameter	filteredDataWidth	=	25
+)
+(
+	input Clk_i,
+	input [filteredDataWidth-1:0] Data_i,
+	input DataNd_i,
+	output [inOutDataWidth-1:0] Data_o,
+	output DataValid_o
+);
+
+reg ndReg;
+reg	signed	[filteredDataWidth-1:0]	inReg;
+reg signed	[inOutDataWidth-1:0]	sumResult;
+reg	dataValid;
+reg	signed	[filteredDataWidth-1:0] delData	[M-1:0];
+
+	always	@(posedge Clk_i)	begin
+		ndReg <= DataNd_i;
+		if	(DataNd_i)	begin
+			inReg	<=	Data_i;
+		end
+	end
+
+genvar i;
+generate 
+	for (i=0; i<M; i=i+1)	begin:combGen
+		always	@(posedge	Clk_i)	begin
+			if	(i==0)	begin
+				delData	[i]	<=	inReg;
+			end	else	begin
+				delData	[i]	<=	delData[i-1];
+			end
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(ndReg)	begin
+			sumResult	<=	inReg+-delData[M-1];
+			dataValid	<=	1'b1;
+		end	else	begin
+			dataValid	<=	1'b0;
+		end
+	end
+endgenerate
+
+assign	Data_o	=	sumResult;
+assign	DataValid_o	=	dataValid;
+endmodule

src/src/Sim/src/cicFilter/combFilterWrapper.v

@@ -0,0 +1,67 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    16:47:07 10/26/2020 
+// Design Name: 
+// Module Name:    intFilterWrapper 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module combFilterWrapper
+#(
+	parameter	M = 4,
+	parameter	filteredDataWidth	=	25,
+	parameter	inOutDataWidth	=	18
+)
+(
+	input Clk_i,
+	input [filteredDataWidth-1:0] Data_i,
+	input DataNd_i,
+	output [filteredDataWidth-1:0] Data_o,
+	output DataValid_o
+);
+
+	wire [filteredDataWidth-1:0] combOutData;
+	wire combOutDataValid;
+	
+	combFilterBlock 
+	#(	.M(M),
+		.filteredDataWidth	(filteredDataWidth),
+		.inOutDataWidth	(filteredDataWidth)
+	)
+	combFilterBlockInst
+	(
+		.Clk_i(Clk_i),
+		.Data_i(Data_i),
+		.DataNd_i(DataNd_i),
+		.Data_o(combOutData),
+		.DataValid_o(combOutDataValid)
+	);
+	
+	
+	roundSymmetric 
+	#( 
+		.inDataWidth(filteredDataWidth),
+		.outDataWidth(filteredDataWidth)
+	)
+	combRoundInst
+	(
+		.Rst_i(1'b0),
+		.Clk_i(Clk_i),
+		.Data_i(combOutData),
+		.DataNd_i(combOutDataValid),
+		.Data_o(Data_o),
+		.DataValid_o(DataValid_o)
+	);
+endmodule

src/src/Sim/src/cicFilter/decimBlock.v

@@ -0,0 +1,59 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    12:42:08 10/27/2020 
+// Design Name: 
+// Module Name:    decimBlock 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module decimBlock
+#(	parameter	R	=	2,
+	parameter	inOutDataWidth	=	18,
+	parameter	decimCntWidth	=	7
+)
+(
+	input Clk_i,
+	input [inOutDataWidth-1:0] Data_i,
+	input DataNd_i,
+	output [inOutDataWidth-1:0] Data_o,
+	output DataValid_o
+);
+
+reg	[decimCntWidth-1:0]	decimCnt;
+reg	[inOutDataWidth-1:0]	dataReg;
+reg	valReg;
+
+always	@(posedge	Clk_i)	begin
+	if	(DataNd_i)	begin
+		if	(decimCnt	==	R-1)	begin
+			decimCnt	<=	{decimCntWidth{1'b0}};
+			valReg		<=	1'b1;
+		end	else	begin
+			decimCnt	<=	decimCnt+7'd1;
+			valReg		<=	1'b0;
+		end
+	end	else	begin
+		decimCnt	<=	{decimCntWidth{1'b0}};
+		valReg		<=	1'b0;
+	end
+	
+	if	(decimCnt	==	R-1)	begin
+		dataReg	<=	Data_i;
+	end	
+end
+
+assign	Data_o	=	dataReg;
+assign	DataValid_o	=	valReg;
+endmodule

src/src/Sim/src/cicFilter/intFilterBlock.v

@@ -0,0 +1,38 @@
+module intFilterBlock 
+#(	parameter	inOutDataWidth	=	18,
+	parameter	filteredDataWidth	=	25
+)
+(
+	input Clk_i,
+	input [inOutDataWidth-1:0] Data_i,
+	input DataNd_i,
+	output [filteredDataWidth-1:0] Data_o,
+	output DataValid_o
+);
+
+	reg [1:0] ndShReg;
+	
+	always @ (posedge Clk_i)
+		ndShReg <= {ndShReg[0:0], DataNd_i};
+	
+	reg signed [inOutDataWidth-1:0] inReg;
+	reg signed [filteredDataWidth-1:0] sumResult;
+	
+	always	@(posedge	Clk_i)	begin
+		if (DataNd_i)	begin
+			inReg <= Data_i;
+		end
+	end
+	
+	always @ (posedge Clk_i)	begin
+		if (ndShReg[0])	begin
+			sumResult <= inReg + sumResult;
+		end	else	begin
+			sumResult <= 0;
+		end
+	end
+
+	assign Data_o = sumResult;
+	assign DataValid_o = ndShReg[1];
+
+endmodule

src/src/Sim/src/cicFilter/intFilterWrapper.v

@@ -0,0 +1,63 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    16:47:07 10/26/2020 
+// Design Name: 
+// Module Name:    intFilterWrapper 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module intFilterWrapper
+#(	parameter	filteredDataWidth	=	25,
+	parameter	inOutDataWidth	=	18
+)
+(
+	input Clk_i,
+	input [inOutDataWidth-1:0] Data_i,
+	input DataNd_i,
+	output [filteredDataWidth-1:0] Data_o,
+	output DataValid_o
+);
+
+	wire [filteredDataWidth-1:0] intOutData;
+	wire intOutDataValid;
+	
+	intFilterBlock 
+	#(	.inOutDataWidth	(inOutDataWidth),
+		.filteredDataWidth	(filteredDataWidth)
+	)
+	intFilterBlockInst
+	(
+		.Clk_i(Clk_i),
+		.Data_i(Data_i),
+		.DataNd_i(DataNd_i),
+		.Data_o(intOutData),
+		.DataValid_o(intOutDataValid)
+	);
+	
+	roundSymmetric 
+	#( 
+		.inDataWidth(filteredDataWidth),
+		.outDataWidth(filteredDataWidth)
+	)
+	intRoundInst
+	(
+		.Rst_i(1'b0),
+		.Clk_i(Clk_i),
+		.Data_i(intOutData),
+		.DataNd_i(intOutDataValid),
+		.Data_o(Data_o),
+		.DataValid_o(DataValid_o)
+	);	
+endmodule

src/src/Sim/src/cicFilter/roundSymmetric.v

@@ -0,0 +1,36 @@
+module roundSymmetric 
+#( 
+	parameter inDataWidth = 35,
+	parameter outDataWidth = 17
+)
+(
+	input Rst_i,
+	input Clk_i,
+	input [inDataWidth-1 : 0] Data_i,
+	input DataNd_i,
+	output [outDataWidth-1 : 0] Data_o,
+	output DataValid_o
+);
+	
+	parameter [inDataWidth-1 : 0] addPositive = 2**(inDataWidth-outDataWidth-1);
+	parameter [inDataWidth-1 : 0] addNegative = 2**(inDataWidth-outDataWidth-1)-1;
+	
+	reg [inDataWidth-1 : 0] corrData;
+	always @ (posedge Clk_i or posedge Rst_i)
+		if (Rst_i)
+			corrData <= 0;
+		else if (DataNd_i)
+			begin
+				if (Data_i[inDataWidth-1])
+					corrData <= Data_i + addNegative;
+				else 
+					corrData <= Data_i + addPositive;
+			end
+			
+	assign Data_o = corrData[inDataWidth-1 : inDataWidth-outDataWidth];
+	
+	reg outDataValidReg;
+	always @ (posedge Clk_i) outDataValidReg <= DataNd_i;
+	assign DataValid_o = outDataValidReg;
+
+endmodule

src/src/Sim/src/cicFilter/singleMaccFilterImpulse_tb.v

@@ -0,0 +1,51 @@
+`timescale 1ps / 1ps
+module transposedFilterImpulse_tb;
+
+	// Inputs
+	reg Clk_i;
+	reg [17:0] Data_i;
+	reg DataNd_i;
+
+	// Outputs
+	wire [17:0] Data_o;
+	wire DataValid_o;
+
+	// Instantiate the Unit Under Test (UUT)
+	cicFilter uut (
+		.Clk_i(Clk_i), 
+		.Data_i(Data_i), 
+		.DataNd_i(DataNd_i), 
+		.Data_o(Data_o), 
+		.DataValid_o(DataValid_o)
+	);
+
+	initial begin
+		// Initialize Inputs
+		Clk_i = 0;
+		Data_i = 0;
+		DataNd_i = 0;
+		// Wait 100 ns for global reset to finish
+		#100;
+	end
+	
+	parameter period = 5000;
+	always # (period / 2) Clk_i <= ~Clk_i;
+	
+	integer simCnt = 0;
+	always @ (posedge Clk_i) simCnt <= simCnt + 1;
+	
+	always @ (posedge Clk_i)
+		begin
+			DataNd_i <= 1;
+			if (simCnt == 160)
+				Data_i <= 18'h1FFFF;
+			else
+				Data_i = 0;
+		end
+			
+	reg [17:0] dataOutTest;
+	always @ (posedge Clk_i)
+		if (DataValid_o)
+			dataOutTest <= Data_o;	
+      
+endmodule

src/src/Sim/src/cicFilter/singleMaccFilterStep_tb.v

@@ -0,0 +1,63 @@
+`timescale 1ps / 1ps
+module singleMaccFilterStep_tb;
+
+	// Inputs
+	reg Rst_i;
+	reg CoeffClk_i;
+	reg [3:0] CoeffAddr_i;
+	reg [17:0] CoeffData_i;
+	reg CoeffWr_i;
+	reg Clk_i;
+	reg [17:0] Data_i;
+	reg DataNd_i;
+
+	// Outputs
+	wire [17:0] Data_o;
+	wire DataValid_o;
+
+	// Instantiate the Unit Under Test (UUT)
+	cicFilter uut (
+		.Clk_i(Clk_i), 
+		.Data_i(Data_i), 
+		.DataNd_i(DataNd_i), 
+		.Data_o(Data_o), 
+		.DataValid_o(DataValid_o)
+	);
+
+	initial begin
+		Rst_i = 1;
+		CoeffClk_i = 0;
+		CoeffAddr_i = 0;
+		CoeffData_i = 0;
+		CoeffWr_i = 0;
+		Clk_i = 0;
+		Data_i = 0;
+		DataNd_i = 0;
+		#100;
+		Rst_i <= 0;
+	end
+      
+	parameter period = 5000;
+	always # (period / 2) Clk_i <= ~Clk_i;
+	
+	integer simCnt = 0;
+	always @ (posedge Clk_i) simCnt <= simCnt + 1;
+	
+	always @ (posedge Clk_i)
+		if (simCnt % 32 == 0)
+			begin
+				DataNd_i <= 1;
+				if (simCnt >= 1000)
+					Data_i <= 18'h1FFFF;
+				else
+					Data_i = 1;
+			end
+		else
+			DataNd_i <= 1;
+			
+	reg [17:0] dataOutTest;
+	always @ (posedge Clk_i)
+		if (DataValid_o)
+			dataOutTest <= Data_o;
+		
+endmodule

src/src/Sim/src/cicFirFilterTop.v

@@ -0,0 +1,86 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    16:16:47 11/03/2020 
+// Design Name: 
+// Module Name:    cicFirFilterTop 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//FilteredDataWidth==ceil(log2((R*M)^N)/R)+inOutDataWidth;
+//
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	cicFirFilterTop	
+#(
+	parameter	N =	3,	//filter order
+	parameter	M =	2,	//comb delay	
+	parameter	R = 2,	//decim fartor
+	parameter	filteredDataWidth	=	20,
+	parameter	inOutDataWidth	=	18,
+	parameter	decimCntWidth	=	7,
+	parameter	CoeffCount		=	16
+)
+(
+	input	Clk_i,
+	input	[inOutDataWidth-1:0] Data_i,
+	input	DataNd_i,
+	output	[inOutDataWidth-1:0] Data_o,
+	output	DataValid_o
+);
+
+wire	[filteredDataWidth-1:0]	cicFilteredData;
+wire	DataNd;
+
+cicFilter 
+#(
+	.N (N),	//filter order
+	.M (M),	//comb delay
+	.R (R),	//decim fartor
+	.filteredDataWidth	(filteredDataWidth),
+	.inOutDataWidth		(inOutDataWidth),
+	.decimCntWidth		(decimCntWidth)
+)
+cicFilterInst
+(
+	.Clk_i			(Clk_i),
+	.Data_i			(Data_i),
+	.DataNd_i		(DataNd_i),
+	.Data_o			(cicFilteredData),
+	.DataValid_o	(DataNd)
+);
+
+
+
+systolicFilter
+#(
+	.CoeffCount 		(CoeffCount),
+	.filteredDataWidth	(38),
+	.inOutDataWidth		(filteredDataWidth),
+	.decimCntWidth		(decimCntWidth)
+)
+systolicFilterInst
+(
+	.Clk_i			(Clk_i),
+	.Data_i			(cicFilteredData),
+	.DataNd_i		(DataNd),
+	.Data_o			(Data_o),
+	.DataValid_o	(DataValid_o)
+);
+endmodule
+
+
+
+
+
+

src/src/Sim/src/cicFirFilterTopTb.v

@@ -0,0 +1,61 @@
+`timescale 1ps / 1ps
+module cicFirFilterTopTb;
+
+	// Inputs
+	reg Clk_i;
+	reg [17:0] Data_i;
+	reg DataNd_i;
+
+	// Outputs
+	wire [17:0] Data_o;
+	wire DataValid_o;
+
+	// Instantiate the Unit Under Test (UUT)
+	cicFirFilterTop uut (
+		.Clk_i(Clk_i), 
+		.Data_i(Data_i), 
+		.DataNd_i(DataNd_i), 
+		.Data_o(Data_o), 
+		.DataValid_o(DataValid_o)
+	);
+
+	initial begin
+		// Initialize Inputs
+		Clk_i = 0;
+		Data_i = 0;
+		DataNd_i = 0;
+
+		// Wait 100 ns for global reset to finish
+		#100;
+	end
+	
+	parameter period = 5000;
+	always # (period / 2) Clk_i <= ~Clk_i;
+	
+	integer simCnt = 0;
+	always @ (posedge Clk_i) simCnt <= simCnt + 1;
+	
+	real pi = 3.14159265358;
+	real phase = 0;
+	real phaseInc = 0.001;
+	real signal;
+	always @ (posedge Clk_i)
+		begin
+			DataNd_i <= 1;
+			if (simCnt >= 150)
+				begin
+					phase = phase + phaseInc;
+					phaseInc <= phaseInc + 0;
+					signal = $sin(2*pi+phase);
+					Data_i = 2**16 * signal;
+				end
+			else
+				Data_i = 0;
+		end
+			
+	reg [17:0] dataOutTest;
+	always @ (posedge Clk_i)
+		if (DataValid_o)
+			dataOutTest <= Data_o;		
+      
+endmodule

src/src/Sim/src/firFilter/roundSymmetric .v

@@ -0,0 +1,36 @@
+module roundSymmetric #
+( 
+	parameter inDataWidth = 35,
+	parameter outDataWidth = 17
+)
+(
+	input Rst_i,
+	input Clk_i,
+	input [inDataWidth-1 : 0] Data_i,
+	input DataNd_i,
+	output [outDataWidth-1 : 0] Data_o,
+	output DataValid_o
+);
+	
+	parameter [inDataWidth-1 : 0] addPositive = 2**(inDataWidth-outDataWidth-1);
+	parameter [inDataWidth-1 : 0] addNegative = 2**(inDataWidth-outDataWidth-1)-1;
+	
+	reg [inDataWidth-1 : 0] corrData;
+	always @ (posedge Clk_i or posedge Rst_i)
+		if (Rst_i)
+			corrData <= 0;
+		else if (DataNd_i)
+			begin
+				if (Data_i[inDataWidth-1])
+					corrData <= Data_i + addNegative;
+				else 
+					corrData <= Data_i + addPositive;
+			end
+			
+	assign Data_o = corrData[inDataWidth-1 : inDataWidth-outDataWidth];
+	
+	reg outDataValidReg;
+	always @ (posedge Clk_i) outDataValidReg <= DataNd_i;
+	assign DataValid_o = outDataValidReg;
+
+endmodule

src/src/Sim/src/firFilter/systolicFilter.v

@@ -0,0 +1,46 @@
+module systolicFilter
+#(	parameter	filteredDataWidth	=	26,
+	parameter	inOutDataWidth	=	18,
+	parameter	decimCntWidth	=	7,
+	parameter	CoeffCount		=	16
+)
+(
+	input Clk_i,
+	input [inOutDataWidth-1:0] Data_i,
+	input DataNd_i,
+	output [18-1:0] Data_o,
+	output DataValid_o
+);
+
+	wire [47:0] outData;
+	wire outDataValid;
+	systolicFilterBlock # (
+		.CoeffCount(CoeffCount)
+	)
+	systolicFilterBlockInst
+	(
+		.Clk_i(Clk_i),
+		.Data_i(Data_i),
+		.DataNd_i(DataNd_i),
+		.Data_o(outData),
+		.DataValid_o(outDataValid)
+	);
+	
+	wire dataValid;
+	roundSymmetric #
+	( 
+		.inDataWidth(filteredDataWidth),
+		.outDataWidth(18)
+	)
+	roundInst
+	(
+		.Rst_i(Rst_i),
+		.Clk_i(Clk_i),
+		.Data_i(outData[37:0]),
+		.DataNd_i(outDataValid),
+		.Data_o(Data_o),
+		.DataValid_o(DataValid_o)
+	);
+
+
+endmodule

src/src/Sim/src/firFilter/systolicFilterBlock.v

@@ -0,0 +1,80 @@
+module systolicFilterBlock # (
+	parameter CoeffCount = 16
+)
+(
+	input Clk_i,
+	input [19:0] Data_i,
+	input DataNd_i,
+	output [47:0] Data_o,
+	output DataValid_o
+);
+
+	wire signed [17:0] coeff[0:CoeffCount-1];
+
+	assign coeff[0] = 18'h3e6c9;
+	assign coeff[1] = 18'h3c349;
+	assign coeff[2] = 18'h3cfde;
+	assign coeff[3] = 18'h3f440;
+	assign coeff[4] = 18'h05e4b;
+	assign coeff[5] = 18'h0e79f;
+	assign coeff[6] = 18'h172aa;
+	assign coeff[7] = 18'h1c760;
+	assign coeff[8] = 18'h1c760;
+	assign coeff[9] = 18'h172aa;
+	assign coeff[10] = 18'h0e79f;
+	assign coeff[11] = 18'h05e4b;
+	assign coeff[12] = 18'h3f440;
+	assign coeff[13] = 18'h3cfde;
+	assign coeff[14] = 18'h3c349;
+	assign coeff[15] = 18'h3e6c9;	
+
+	wire signed [17:0] dataIn = Data_i;
+	reg [3:0] ndShReg;
+	
+	always @ (posedge Clk_i)
+		ndShReg <= {ndShReg[2:0], DataNd_i};
+	
+	reg signed [17:0] inReg0[0:CoeffCount-1];
+	reg signed [17:0] inReg1[0:CoeffCount-1];
+	reg signed [34:0] multResult[0:CoeffCount-1];
+	reg signed [47:0] sumResult[0:CoeffCount-1];
+	
+	
+	genvar i;
+	generate
+		for (i = 0; i < CoeffCount; i = i + 1)
+			begin 
+				always @ (posedge Clk_i)
+					begin
+						if (DataNd_i)
+							begin
+								if (i == 0)
+									begin
+										inReg0[i] <= 0;
+										inReg1[i] <= dataIn;
+									end
+								else
+									begin
+										inReg0[i] <= inReg1[i-1];
+										inReg1[i] <= inReg0[i];
+									end
+							end
+						
+						if (ndShReg[0])
+							multResult[i] <= inReg1[i] * coeff[i];
+						
+						if (ndShReg[1])
+							begin
+								if (i == 0)
+									sumResult[i] <= multResult[i];
+								else
+									sumResult[i] <= multResult[i] + sumResult[i-1];
+							end
+					end
+			end
+	endgenerate
+
+	assign Data_o = sumResult[CoeffCount-1];
+	assign DataValid_o = ndShReg[2];
+
+endmodule

src/src/Sim/src/firFilter/systolicFilterChirp_tb.v

@@ -0,0 +1,61 @@
+`timescale 1ps / 1ps
+module systolicFilterChirp_tb;
+
+	// Inputs
+	reg Clk_i;
+	reg [17:0] Data_i;
+	reg DataNd_i;
+
+	// Outputs
+	wire [17:0] Data_o;
+	wire DataValid_o;
+
+	// Instantiate the Unit Under Test (UUT)
+	systolicFilter uut (
+		.Clk_i(Clk_i), 
+		.Data_i(Data_i), 
+		.DataNd_i(DataNd_i), 
+		.Data_o(Data_o), 
+		.DataValid_o(DataValid_o)
+	);
+
+	initial begin
+		// Initialize Inputs
+		Clk_i = 0;
+		Data_i = 0;
+		DataNd_i = 0;
+
+		// Wait 100 ns for global reset to finish
+		#100;
+	end
+	
+	parameter period = 5000;
+	always # (period / 2) Clk_i <= ~Clk_i;
+	
+	integer simCnt = 0;
+	always @ (posedge Clk_i) simCnt <= simCnt + 1;
+	
+	real pi = 3.14159265358;
+	real phase = 0;
+	real phaseInc = 0.001;
+	real signal;
+	always @ (posedge Clk_i)
+		begin
+			DataNd_i <= 1;
+			if (simCnt >= 1000)
+				begin
+					phase = phase + phaseInc;
+					phaseInc <= phaseInc + 0.0005;
+					signal = $sin(2*pi*phase);
+					Data_i = 2**16 * signal;
+				end
+			else
+				Data_i = 0;
+		end
+			
+	reg [17:0] dataOutTest;
+	always @ (posedge Clk_i)
+		if (DataValid_o)
+			dataOutTest <= Data_o;		
+      
+endmodule

src/src/Sim/src/systolicFilterImpulse_tb.v

@@ -0,0 +1,52 @@
+`timescale 1ps / 1ps
+module systolicFilterImpulse_tb;
+
+	// Inputs
+	reg Clk_i;
+	reg [17:0] Data_i;
+	reg DataNd_i;
+
+	// Outputs
+	wire [17:0] Data_o;
+	wire DataValid_o;
+
+	// Instantiate the Unit Under Test (UUT)
+	cicFirFilterTop uut (
+		.Clk_i(Clk_i), 
+		.Data_i(Data_i), 
+		.DataNd_i(DataNd_i), 
+		.Data_o(Data_o), 
+		.DataValid_o(DataValid_o)
+	);
+
+	initial begin
+		// Initialize Inputs
+		Clk_i = 0;
+		Data_i = 0;
+		DataNd_i = 0;
+
+		// Wait 100 ns for global reset to finish
+		#100;
+	end
+	
+	parameter period = 5000;
+	always # (period / 2) Clk_i <= ~Clk_i;
+	
+	integer simCnt = 0;
+	always @ (posedge Clk_i) simCnt <= simCnt + 1;
+	
+	always @ (posedge Clk_i)
+		begin
+			DataNd_i <= 1;
+			if (simCnt == 160)
+				Data_i <= 18'h1FFFF;
+			else
+				Data_i = 0;
+		end
+			
+	reg [17:0] dataOutTest;
+	always @ (posedge Clk_i)
+		if (DataValid_o)
+			dataOutTest <= Data_o;	
+      
+endmodule

src/src/Sim/untitled.txt

@@ -0,0 +1 @@
+000000DB