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src/src/FftDataFiltering/DecimFilterWrapper.v

@@ -72,7 +72,7 @@ module	DecimFilterWrapper
 //================================================================================
 //	ASSIGNMENTS
 //================================================================================
-	assign oscWindVal = DataVal_i;
+	assign oscWindVal = DataVal_i&(!coefDataVal);
 
 	assign Data_o	=	(bypassFlag)? adcExtData[LsbForR1-1-:16]:decimData[17-:16];
 	assign DataVal_o	=	(bypassFlag)? DataVal_i:decimDataVal;
@@ -81,15 +81,15 @@ module	DecimFilterWrapper
 //	CODING
 //================================================================================
 
-// RomCtrl	RomCtrl
-// (
-	// .Clk_i		(Clk_i),
-	// .Rst_i		(Rst_i),
-	// .DataVal_i	(DataVal_i),
-	// .CoefDataVal_o	(coefDataVal),
-	// .DecimFactor_i	(DecimFactor_i),
-	// .CoefAddr_o	(coefAddr)
-// );
+RomCtrl	RomCtrl
+(
+	.Clk_i		(Clk_i),
+	.Rst_i		(Rst_i),
+	.OscWind_i	(DataVal_i),
+	.CoefDataVal_o	(coefDataVal),
+	.DecimFactor_i	(DecimFactor_i),
+	.CoefAddr_o	(coefAddr)
+);
 
 CoefROM CoefRom (
   .a(coefAddr),      // input wire [8 : 0] a

src/src/FftDataFiltering/RomCtrl.v

@@ -21,12 +21,12 @@
 module RomCtrl
 #(	
 	parameter	OutWidth	=	9,
-	parameter [8:0] BaseAddrR2 = 0,
-	parameter [8:0] BaseAddrR3 = 35,
-	parameter [8:0] BaseAddrR4 = 70,
-	parameter [8:0] BaseAddrR5 = 105,
-	parameter [8:0] BaseAddrR6 = 140,
-	parameter [8:0] BaseAddrR7 = 175
+	parameter BaseAddrR2 = 0,
+	parameter BaseAddrR3 = 64,
+	parameter BaseAddrR4 = 70,
+	parameter BaseAddrR5 = 105,
+	parameter BaseAddrR6 = 140,
+	parameter BaseAddrR7 = 175
 )
 (
 	input Clk_i,
@@ -43,18 +43,18 @@ module RomCtrl
 //================================================================================
 reg	[2:0] decimFactor;
 reg [OutWidth-1:0] currBaseAddr;
+reg [OutWidth-1:0] currMaxAddr;
 reg [8:0] coefAddr;
 
 reg	changeFlag;
 reg	coefDataVal;
-reg	coefDataValReg;
 
 //================================================================================
 //	ASSIGNMENTS
 //================================================================================
 // assign changeFlag = (decimFactor!= DecimFactor_i);
 assign CoefAddr_o = coefAddr;
-assign CoefDataVal_o = coefDataValReg;
+assign CoefDataVal_o = coefDataVal;
 	
 //================================================================================
 //	CODING
@@ -84,7 +84,8 @@ always @(posedge Clk_i) begin
 		if (changeFlag) begin
 			coefDataVal <= 1'b1;
 		end 
-		if (coefAddr==currBaseAddr+34) begin
+		// if (coefAddr==currBaseAddr+63) begin
+		if (coefAddr==currMaxAddr) begin
 			coefDataVal <= 1'b0;
 		end
 	end else begin
@@ -94,54 +95,70 @@ end
 
 always @(posedge Clk_i) begin
 	if (!Rst_i) begin
-		coefDataValReg <= coefDataVal;
+		case (DecimFactor_i) 
+			1:	begin
+					currMaxAddr <= 9'd63;
+				end
+			2:	begin
+					currMaxAddr <= 9'd63;
+				end
+			3:	begin
+					currMaxAddr <= 9'd127;
+				end
+		endcase
 	end else begin
-		coefDataValReg <= 0;
+		currMaxAddr <= 0;
 	end 
-end
+end 
 
+// always @(posedge Clk_i) begin
+	// if (!Rst_i) begin
+		// if (changeFlag) begin
+			// case (DecimFactor_i) 
+				// 1:	begin
+						// currBaseAddr <= 9'd0;
+					// end
+				// 2:	begin
+						// currBaseAddr <= 9'd0;
+					// end
+				// 3:	begin
+						// currBaseAddr <= 9'd64;
+					// end
+				// 4:	begin
+						// currBaseAddr <= BaseAddrR4;
+					// end
+				// 5:	begin
+						// currBaseAddr <= BaseAddrR5;
+					// end
+				// 6:	begin
+						// currBaseAddr <= BaseAddrR6;
+					// end
+				// 7:	begin
+						// currBaseAddr <= BaseAddrR7;
+					// end
+			// endcase
+		// end
+	// end else begin
+		// currBaseAddr <= 0;
+	// end 
+// end 
 
 always @(posedge Clk_i) begin
 	if (!Rst_i) begin
-		if (changeFlag) begin
+		if (coefDataVal) begin
+			coefAddr<=coefAddr+1;
+		end else begin
 			case (DecimFactor_i) 
-				0:	begin
-						currBaseAddr <= BaseAddrR2;
-					end
 				1:	begin
-						currBaseAddr <= BaseAddrR2;
+						coefAddr <= 9'd0;
 					end
 				2:	begin
-						currBaseAddr <= BaseAddrR2;
+						coefAddr <= 9'd0;
 					end
 				3:	begin
-						currBaseAddr <= BaseAddrR3;
-					end
-				4:	begin
-						currBaseAddr <= BaseAddrR4;
-					end
-				5:	begin
-						currBaseAddr <= BaseAddrR5;
-					end
-				6:	begin
-						currBaseAddr <= BaseAddrR6;
-					end
-				7:	begin
-						currBaseAddr <= BaseAddrR7;
+						coefAddr <= 9'd64;
 					end
 			endcase
-		end
-	end else begin
-		currBaseAddr <= 0;
-	end 
-end 
-
-always @(posedge Clk_i) begin
-	if (!Rst_i) begin
-		if (coefDataValReg) begin
-			coefAddr<=coefAddr+1;
-		end else begin
-			coefAddr <= currBaseAddr;
 		end 
 	end else begin
 		coefAddr <=0;

src/src/Sim/DecimFilterWrapperTb.v

@@ -129,13 +129,7 @@ always	@(posedge	Clk50)	begin
 			decimFactor	<= 2;
 		end else if (tbCnt == 6400) begin
 			decimFactor	<= 3;
-		end else if (tbCnt == 7400) begin
-			decimFactor	<= 5;
-		end else if (tbCnt == 8400) begin
-			decimFactor	<= 6;
-		end else if (tbCnt == 9400) begin
-			decimFactor	<= 7;
-		end 
+		end
 	end else begin
 	 decimFactor <= 2;
 	end 

src/src/Sim/FiltersCoeffs.coe

@@ -1,391 +1,325 @@
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+MEMORY_INITIALIZATION_RADIX =10;
+MEMORY_INITIALIZATION_VECTOR =282,
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src/src/Sim/firFilter/systolicFilter.v

@@ -22,7 +22,22 @@ module systolicFilter
 	wire	[17:0]	test2 = outData[35-:18];
 	
 	
-	systolicFilterBlockTest # (
+	// systolicFilterBlockTest # (
+		// .CoeffCount(CoeffCount)
+	// )
+	// systolicFilterBlockInst
+	// (
+		// .Clk_i(Clk_i),
+		// .Rst_i(Rst_i),
+		// .Data_i(Data_i),
+		// .DecimFactor_i(DecimFactor_i),
+		// .DataNd_i(DataNd_i),
+		// .DataNd_i(1'b1),
+		// .Data_o(outData),
+		// .DataValid_o(outDataValid)
+	// );
+	
+	systolicFilterBlock # (
 		.CoeffCount(CoeffCount)
 	)
 	systolicFilterBlockInst
@@ -30,9 +45,9 @@ module systolicFilter
 		.Clk_i(Clk_i),
 		.Rst_i(Rst_i),
 		.Data_i(Data_i),
-		.DecimFactor_i(DecimFactor_i),
+		.CoefData_i(CoefData_i),
+		.CoefDataVal_i(CoefDataVal_i),
 		.DataNd_i(DataNd_i),
-		// .DataNd_i(1'b1),
 		.Data_o(outData),
 		.DataValid_o(outDataValid)
 	);

src/src/Sim/firFilter/systolicFilterBlock.v

@@ -13,17 +13,17 @@ module systolicFilterBlock # (
 );
 
 	reg signed [17:0] coeff[0:CoeffCount-1];
-
-
-
+	
 	wire signed [17:0] dataIn = Data_i;
-	reg [3:0] ndShReg;
+	reg [CoeffCount-1:0] ndShReg;
+	
+	wire comRst = (Rst_i|!(DataNd_i|DataValid_o));
 	
 	always @ (posedge Clk_i)
 		if (!Rst_i) begin
-			ndShReg <= {ndShReg[2:0], DataNd_i};
+			ndShReg <= {ndShReg[CoeffCount-2:0], DataNd_i};
 		end else begin
-			ndShReg <= 4'h0;
+			ndShReg <= 0;
 		end
 	
 	reg signed [17:0] inReg0[0:CoeffCount-1];
@@ -46,55 +46,19 @@ module systolicFilterBlock # (
 		end 
 	end
 	
-	always @(*) begin
+	always @(posedge Clk_i) begin
 		if (!Rst_i) begin
 			if (CoefDataVal_i) begin
-				coeff[addrCnt] = CoefData_i;
+				coeff[addrCnt] <= CoefData_i;
 			end
-		end else begin
-			coeff[0]  = 18'h002fd;
-			coeff[1]  = 18'h00f3e;
-			coeff[2]  = 18'h013ef;
-			coeff[3]  = 18'h006f0;
-			coeff[4]  = 18'h3f248;
-			coeff[5]  = 18'h3f30a;
-			coeff[6]  = 18'h00bcc;
-			coeff[7]  = 18'h01664;
-			coeff[8]  = 18'h3fa36;
-			coeff[9]  = 18'h3de4b;
-			coeff[10] = 18'h3f843;
-			coeff[11] = 18'h02d1e;
-			coeff[12] = 18'h021a2;
-			coeff[13] = 18'h3c919;
-			coeff[14] = 18'h3a7f7;
-			coeff[15] = 18'h03d7b;
-			coeff[16] = 18'h13ec9;
-			coeff[17] = 18'h1c034;
-			coeff[18] = 18'h13ec9;
-			coeff[19] = 18'h03d7b;
-			coeff[20] = 18'h3a7f7;
-			coeff[21] = 18'h3c919;
-			coeff[22] = 18'h021a2;
-			coeff[23] = 18'h02d1e;
-			coeff[24] = 18'h3f843;
-			coeff[25] = 18'h3de4b;
-			coeff[26] = 18'h3fa36;
-			coeff[27] = 18'h01664;
-			coeff[28] = 18'h00bcc;
-			coeff[29] = 18'h3f30a;
-			coeff[30] = 18'h3f248;
-			coeff[31] = 18'h006f0;
-			coeff[32] = 18'h013ef;
-			coeff[33] = 18'h00f3e;
-			coeff[34] = 18'h002fd;
-		end                 
+		end 
 	end
 	
 	genvar i;
 	generate
 		for (i = 0; i < CoeffCount; i = i + 1)begin 
 			always @ (posedge Clk_i) begin
-				if (!Rst_i) begin
+				if (!comRst) begin
 					if (DataNd_i) begin
 						if (i == 0) begin
 							inReg0[i] <= 0;
@@ -105,11 +69,11 @@ module systolicFilterBlock # (
 						end
 					end
 				
-					if (ndShReg[0]) begin
+					if (ndShReg[0]|ndShReg[CoeffCount-2]) begin
 						multResult[i] <= inReg1[i] * coeff[i];
 					end
 					
-					if (ndShReg[1]) begin
+					if (ndShReg[1]|ndShReg[CoeffCount-1]) begin
 						if (i == 0) begin
 							sumResult[i] <= multResult[i];
 						end else begin
@@ -127,6 +91,6 @@ module systolicFilterBlock # (
 	endgenerate
 
 	assign Data_o = sumResult[CoeffCount-1];
-	assign DataValid_o = ndShReg[2];
+	assign DataValid_o = ndShReg[CoeffCount-1];
 
 endmodule