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@@ -62,12 +62,40 @@ module DecimFilterWrapper
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wire adcSinVal;
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wire [AdcDataWidth-1:0] adcCosResult;
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wire adcCosVal;
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+
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+ wire axiReloadReady;
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+ wire axiReloadLast;
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+
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+ wire axiReloadValid;
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+ wire axiDataValid;
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+ wire axiConfigReady;
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+ wire axiConfigValid;
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+ wire [7:0] axiConfigData;
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+ wire [15:0] axiReloadDataRam;
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+
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+ reg axiDataValidReg;
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+ reg axiReloadValidReg;
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+ reg [15:0] axiReloadData;
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+ reg axiReloadLastReg;
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+ reg axiConfigValidReg;
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+ reg [7:0] axiConfigDataReg;
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+
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+
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reg [24-1:0] ifFtwLReg;
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reg [24-1:0] ifFtwHReg;
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reg [15:0] outDataI;
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reg [15:0] outDataQ;
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+
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+ reg [1:0] currState;
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+ reg [1:0] nextState;
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+
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+ reg [2:0] decimFactorReg;
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+
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+ reg [3:0] coeffCnt;
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+ reg [4:0] delayCnt;
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+ reg [1:0] configCnt;
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localparam extendBitNum = FilteredDataWidth-AdcDataWidth;
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@@ -81,6 +109,14 @@ module DecimFilterWrapper
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// localparam maxWidthForR8 = 5'd26; //msb for R = 8;
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// localparam maxWidthForR9 = 5'd27; //msb for R = 9;
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// localparam maxWidthForR10 = 5'd28; //msb for R = 10;
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+
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+ localparam IDLE = 2'd0;
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+ localparam RECONFIG = 2'd1;
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+ localparam WAIT_READY = 2'd2;
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+ localparam CONFIG_STATE = 2'd3;
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+
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+
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+ localparam DELAY_VALUE = 2*8-1;
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wire [39:0] firData;
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wire firDataVal;
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@@ -95,12 +131,25 @@ module DecimFilterWrapper
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assign FilteredDataVal_o = firDataVal;
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+ assign axiDataValid = axiDataValidReg;
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+ assign axiReloadValid = axiReloadValidReg;
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+ assign axiReloadLast = axiReloadLastReg;
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+ assign axiConfigValid = axiConfigValidReg;
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+ assign axiConfigData = axiConfigDataReg;
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+
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+
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// {{14{AdcData_i[AdcDataWidth-1]}},AdcData_i}
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//================================================================================
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// CODING
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//================================================================================
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+always @(posedge Clk_i) begin
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+ decimFactorReg <= DecimFactor_i;
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+ end
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+
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+
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+
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always @(posedge Clk_i) begin
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if (!Rst_i) begin
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case(DecimFactor_i)
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@@ -161,6 +210,167 @@ always @(posedge Clk_i) begin
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end
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end
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+
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+always @(posedge Clk_i) begin
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+ if (Rst_i) begin
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+ currState <= IDLE;
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+ end
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+ else begin
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+ currState <= nextState;
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+ end
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+end
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+
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+
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+
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+always @(*) begin
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+ case (currState)
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+ IDLE : begin
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+ axiDataValidReg = decimDataValI;
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+ axiReloadData = 16'h0;
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+ axiReloadLastReg = 1'b0;
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+ axiConfigValidReg = 1'b0;
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+ end
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+ RECONFIG : begin
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+ axiDataValidReg = 1'b0;
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+ axiReloadValidReg = 1'b1;
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+ axiConfigValidReg = 1'b0;
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+ axiConfigDataReg = 8'h0;
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+ axiReloadData = axiReloadDataRam;
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+ if (coeffCnt == 4'd7) begin
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+ axiReloadLastReg = 1'b1;
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+ end
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+ else begin
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+ axiReloadLastReg = 1'b0;
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+ end
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+ end
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+ WAIT_READY : begin
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+ axiDataValidReg = 1'b0;
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+ axiReloadLastReg = 1'b0;
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+ axiReloadValidReg = 1'b0;
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+ axiReloadData = 16'h0;
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+ axiConfigValidReg = 1'b0;
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+ axiConfigDataReg = 8'h0;
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+ end
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+ CONFIG_STATE : begin
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+ axiConfigValidReg = 1'b1;
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+ if (configCnt == 1) begin
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+ axiConfigDataReg = 8'h0;
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+ end
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+ else if (configCnt == 2) begin
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+ axiConfigDataReg = 8'h0;
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+ end
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+ end
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+ endcase
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+end
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+
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+
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+
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+
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+
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+
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+
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+
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+always @(posedge Clk_i) begin
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+ if (Rst_i) begin
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+ coeffCnt <= 4'd0;
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+ end
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+ else begin
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+ if (currState == RECONFIG) begin
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+ coeffCnt <= coeffCnt + 1;
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+ end
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+ else begin
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+ coeffCnt <= 4'd0;
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+ end
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+ end
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+end
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+
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+always @(posedge Clk_i) begin
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+ if (Rst_i) begin
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+ delayCnt <= 5'd0;
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+ end
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+ else begin
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+ if (currState == WAIT_READY) begin
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+ delayCnt <= delayCnt +1;
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+ end
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+ else begin
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+ delayCnt <= 5'd0;
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+ end
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+ end
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+end
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+
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+always @(posedge Clk_i) begin
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+ if (Rst_i) begin
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+ configCnt <= 2'b0;
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+ end
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+ else begin
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+ if (currState == CONFIG_STATE) begin
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+ configCnt <= configCnt +1;
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+ end
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+ else begin
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+ configCnt <= 2'b0;
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+ end
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+ end
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+end
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+
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+
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+
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+
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+
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+always @(*) begin
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+ if (Rst_i) begin
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+ nextState = IDLE;
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+ end
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+ else begin
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+ case (currState)
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+ IDLE: begin
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+ if (decimFactorReg != DecimFactor_i && axiReloadReady) begin
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+ nextState = RECONFIG;
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+ end
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+ end
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+ RECONFIG: begin
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+ if (coeffCnt == 4'd7) begin
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+ nextState = WAIT_READY;
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+ end
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+ end
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+ WAIT_READY: begin
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+ if (delayCnt == DELAY_VALUE) begin
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+ nextState = CONFIG_STATE;
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+ end
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+ end
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+ CONFIG_STATE: begin
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+ if (configCnt == 2) begin
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+ nextState = IDLE;
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+ end
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+ end
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+ default: begin
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+ nextState = IDLE;
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+ end
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+ endcase
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+ end
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+end
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+ReloadCoeffRam ReloadCoeffRam (
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+ .Clk_i (Clk_i),
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+ .Rst_i (Rst_i),
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+ .ReadEn_i (axiReloadValid),
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+ .Data_o (axiReloadDataRam)
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+
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+
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+);
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+
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+
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+
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cicFilter
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#(
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.N (N), //filter order
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@@ -180,13 +390,29 @@ cicFilterInstI
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.DataValid_o (decimDataValI)
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);
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+// FirFilter FirFilter (
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+// .aclk(Clk_i), // input wire aclk
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+// .s_axis_data_tvalid(decimDataValI), // input wire s_axis_data_tvalid
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+// .s_axis_data_tready(), // output wire s_axis_data_tready
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+// .s_axis_data_tdata(outDataI), // input wire [15 : 0] s_axis_data_tdata
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+// .m_axis_data_tvalid(firDataVal), // output wire m_axis_data_tvalid
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+// .m_axis_data_tdata(firData) // output wire [39 : 0] m_axis_data_tdata
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+// );
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+
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FirFilter FirFilter (
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- .aclk(Clk_i), // input wire aclk
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- .s_axis_data_tvalid(decimDataValI), // input wire s_axis_data_tvalid
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- .s_axis_data_tready(), // output wire s_axis_data_tready
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- .s_axis_data_tdata(outDataI), // input wire [15 : 0] s_axis_data_tdata
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- .m_axis_data_tvalid(firDataVal), // output wire m_axis_data_tvalid
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- .m_axis_data_tdata(firData) // output wire [39 : 0] m_axis_data_tdata
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+ .aclk(Clk_i), // input wire aclk
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+ .s_axis_data_tvalid(axiDataValid), // input wire s_axis_data_tvalid
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+ .s_axis_data_tready(), // output wire s_axis_data_tready
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+ .s_axis_data_tdata(outDataI), // input wire [15 : 0] s_axis_data_tdata
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+ .s_axis_config_tvalid(axiConfigValid), // input wire s_axis_config_tvalid
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+ .s_axis_config_tready(axiConfigReady), // output wire s_axis_config_tready
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+ .s_axis_config_tdata(axiConfigDataReg), // input wire [7 : 0] s_axis_config_tdata
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+ .s_axis_reload_tvalid(axiReloadValid), // input wire s_axis_reload_tvalid
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+ .s_axis_reload_tready(axiReloadReady), // output wire s_axis_reload_tready
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+ .s_axis_reload_tlast(axiReloadLast), // input wire s_axis_reload_tlast
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+ .s_axis_reload_tdata(axiReloadData), // input wire [15 : 0] s_axis_reload_tdata
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+ .m_axis_data_tvalid(firDataVal), // output wire m_axis_data_tvalid
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+ .m_axis_data_tdata(firData) // output wire [39 : 0] m_axis_data_tdata
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);
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endmodule
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