Тестирую новый вариант CIC-фильтра

src/src/ExtDspInterface/DspInterface.v

@@ -229,19 +229,32 @@ DspSlaveSpi
 	.Miso_o		(Miso_o)
 );
 
-DecimFilterWrapperTest	DecimFilter
+// DecimFilterWrapperTest	DecimFilter
+// (
+// 	.Clk_i			(Clk_i),
+// 	.Rst_i			(Rst_i),
+// 	.DataVal_i		(OscWind_i),
+// 	.DecimFactor_i	(DecimFactor_i),
+	
+	
+// 	.Data_i		(currDataChannel),
+// 	// .TestData_o		(testData),
+	
+// 	.Data_o	(filteredDecimData),
+// 	.DataVal_o	(filteredDecimDataVal)
+// );
+
+CicFilterNewWrapperNoIntDiff DecimFilter 
 (
 	.Clk_i			(Clk_i),
 	.Rst_i			(Rst_i),
 	.DataVal_i		(OscWind_i),
 	.DecimFactor_i	(DecimFactor_i),
-	
-	
-	.Data_i		(currDataChannel),
-	// .TestData_o		(testData),
-	
-	.Data_o	(filteredDecimData),
-	.DataVal_o	(filteredDecimDataVal)
+
+	.Data_i			(currDataChannel),
+
+	.Data_o			(filteredDecimData),
+	.DataVal_o		(filteredDecimDataVal)
 );
 
 reg [15:0] currDecimFactor;

src/src/FftDataFiltering/DecimFilterWrapperTest2.sv

@@ -0,0 +1,130 @@
+module DecimFilterWrapperTest2 #(
+    parameter InDataWidth = 14,
+    parameter N = 6, // Number of stages
+    parameter M = 4, // Differential delay
+    parameter OutDataWidth = 17
+)
+(
+    input logic 								Clk_i,
+    input logic 			[2:0]               DecimFactor_i, // Decimation factor (1, 2, 4, 8)
+	input logic                     			Rst_i,
+
+    input logic                     			DataVal_i,
+    input logic 	signed	[InDataWidth-1:0]   Data_i,
+
+    output logic 								DataVal_o,
+    output logic 	signed	[OutDataWidth-1:0] 	Data_o
+);
+//================================================================================
+//								REG/WIRE
+//================================================================================
+/* LocalParams */
+localparam extendBitNum = OutDataWidth - InDataWidth;
+
+/* Integrator Block */
+wire signed					[OutDataWidth-1:0] 	integratedDataIn 	[N-1:0];
+wire 											adcExtData				   ;
+wire signed										integratedDataValIn [N-1:0];
+wire signed					[OutDataWidth-1:0] 	integratedDataOut 	[N-1:0];
+wire 											integratedValOut 	[N-1:0];
+
+/* Decim Block */
+wire signed 				[OutDataWidth-1:0] 	decimDataOut;
+wire 											decimDataValOut;
+
+/* Comb Filter Block */
+wire signed					[OutDataWidth-1:0] 	combDataIn			[N-1:0];
+wire 											combDataValIn		[N-1:0];
+wire signed					[OutDataWidth-1:0] 	combDataOut			[N-1:0];
+wire 											combDataValOut		[N-1:0];
+
+wire signed					[InDataWidth-1:0] 	shTest;
+
+
+//================================================================================
+//								ASSIGNMENTS
+//================================================================================
+assign shTest = combDataOut[N-1] >>> 14;
+
+assign Data_o 		= shTest;
+assign DataVal_o 	= combDataValOut[N-1];
+
+
+//================================================================================
+//								CODING
+//================================================================================
+genvar i;
+
+/* Integrators */
+generate 
+	for (i = 0; i < N; i++) begin : gen_integrators
+
+		assign integratedDataIn[i] = (i == 0) ? Data_i : integratedDataOut[i-1];
+		assign integratedDataValIn[i] = (i == 0) ? DataVal_i : integratedValOut[i-1];
+
+		intFilterBlock
+		#(
+			.InDataWidth	(OutDataWidth),
+			.OutDataWidth	(OutDataWidth)
+		)
+		inFilterBlockInst 
+		(
+			.Clk_i			(Clk_i),
+			.Rst_i			(Rst_i),
+			.Data_i			(integratedDataIn[i]),
+			.DataNd_i		(integratedDataValIn[i]),
+			.Data_o			(integratedDataOut[i]),
+			.DataValid_o	(integratedValOut[i])
+		);
+	end
+
+endgenerate
+
+/* Decimator */
+decimBlock 
+#(
+	.InDataWidth	(OutDataWidth)
+)
+decimBlock_inst (
+	.Clk_i			(Clk_i),
+	.Rst_i			(Rst_i),
+	.DecimFactor_i	(DecimFactor_i),
+	.Data_i			(integratedDataOut[N-1]),
+	.DataNd_i		(integratedValOut[N-1]),
+	.Data_o			(decimDataOut),
+	.DataValid_o	(decimDataValOut)
+
+);
+
+/* Cascade of Combs */
+genvar j;
+generate 
+	for (j = 0; j < N; j++) begin : gen_combs
+
+	assign combDataIn[j] 	= (j == 0) ? decimDataOut 		: combDataOut[j-1];
+	assign combDataValIn[j] = (j == 0) ? decimDataValOut 	: combDataValOut[j-1];
+
+		combFilterBlock
+		#(
+			.InOutDataWidth	(OutDataWidth),
+			.M(M)
+		)
+		combFilterBlockInst 
+		(
+			.Clk_i			(Clk_i),
+			.Rst_i			(Rst_i),
+			.Data_i			(combDataIn[j]),
+			.DataNd_i		(combDataValIn[j]),
+			.Data_o			(combDataOut[j]),
+			.DataValid_o	(combDataValOut[j])
+		);
+	end
+
+endgenerate
+
+
+
+
+endmodule
+
+  

src/src/FftDataFiltering/DecimFilterWrapperTest3.sv

@@ -0,0 +1,130 @@
+module DecimFilterWrapperTest3 #(
+    parameter InDataWidth = 14,
+    parameter N = 6, // Number of stages
+    parameter M = 4, // Differential delay
+    parameter OutDataWidth = 17
+)
+(
+    input logic 								Clk_i,
+    input logic 			[2:0]               DecimFactor_i, // Decimation factor (1, 2, 4, 8)
+	input logic                     			Rst_i,
+
+    input logic                     			DataVal_i,
+    input logic 	signed	[InDataWidth-1:0]   Data_i,
+
+    output logic 								DataVal_o,
+    output logic 	signed	[OutDataWidth-1:0] 	Data_o
+);
+//================================================================================
+//								REG/WIRE
+//================================================================================
+/* LocalParams */
+localparam extendBitNum = OutDataWidth - InDataWidth;
+
+/* Integrator Block */
+wire signed					[OutDataWidth-1:0] 	integratedDataIn 	[N-1:0];
+wire 											adcExtData = (InDataWidth<OutDataWidth)? {{extendBitNum{Data_i[InDataWidth-1]}},Data_i}:Data_i;				   ;
+wire signed										integratedDataValIn [N-1:0];
+wire signed					[OutDataWidth-1:0] 	integratedDataOut 	[N-1:0];
+wire 											integratedValOut 	[N-1:0];
+
+/* Decim Block */
+wire signed 				[OutDataWidth-1:0] 	decimDataOut;
+wire 											decimDataValOut;
+
+/* Comb Filter Block */
+wire signed					[OutDataWidth-1:0] 	combDataIn			[N-1:0];
+wire 											combDataValIn		[N-1:0];
+wire signed					[OutDataWidth-1:0] 	combDataOut			[N-1:0];
+wire 											combDataValOut		[N-1:0];
+
+wire signed					[InDataWidth-1:0] 	shTest;
+
+
+//================================================================================
+//								ASSIGNMENTS
+//================================================================================
+assign shTest = combDataOut[N-1] >>> 14;
+
+assign Data_o 		= decimDataOut;
+assign DataVal_o 	= decimDataValOut;
+
+
+//================================================================================
+//								CODING
+//================================================================================
+genvar i;
+
+/* Integrators */
+generate 
+	for (i = 0; i < N; i++) begin : gen_integrators
+
+		assign integratedDataIn[i] = (i == 0) ? Data_i : integratedDataOut[i-1];
+		assign integratedDataValIn[i] = (i == 0) ? DataVal_i : integratedValOut[i-1];
+
+		intFilterBlock
+		#(
+			.InDataWidth	(OutDataWidth),
+			.OutDataWidth	(OutDataWidth)
+		)
+		inFilterBlockInst 
+		(
+			.Clk_i			(Clk_i),
+			.Rst_i			(Rst_i),
+			.Data_i			(integratedDataIn[i]),
+			.DataNd_i		(integratedDataValIn[i]),
+			.Data_o			(integratedDataOut[i]),
+			.DataValid_o	(integratedValOut[i])
+		);
+	end
+
+endgenerate
+
+/* Decimator */
+decimBlock 
+#(
+	.InDataWidth	(OutDataWidth)
+)
+decimBlock_inst (
+	.Clk_i			(Clk_i),
+	.Rst_i			(Rst_i),
+	.DecimFactor_i	(DecimFactor_i),
+	.Data_i			(combDataOut[N-1]),
+	.DataNd_i		(combDataValOut[N-1]),
+	.Data_o			(decimDataOut),
+	.DataValid_o	(decimDataValOut)
+
+);
+
+/* Cascade of Combs */
+genvar j;
+generate 
+	for (j = 0; j < N; j++) begin : gen_combs
+
+	assign combDataIn[j] 	= (j == 0) ? integratedDataOut[N-1] : combDataOut[j-1];
+	assign combDataValIn[j] = (j == 0) ? integratedValOut[N-1] 	: combDataValOut[j-1];
+
+		combFilterBlock
+		#(
+			.InOutDataWidth	(OutDataWidth),
+			.M(M)
+		)
+		combFilterBlockInst 
+		(
+			.Clk_i			(Clk_i),
+			.Rst_i			(Rst_i),
+			.Data_i			(combDataIn[j]),
+			.DataNd_i		(combDataValIn[j]),
+			.Data_o			(combDataOut[j]),
+			.DataValid_o	(combDataValOut[j])
+		);
+	end
+
+endgenerate
+
+
+
+
+endmodule
+
+  

src/src/FftDataFiltering/TestCicFilter/CicCombFilter.sv

@@ -0,0 +1,85 @@
+module CicCombFilter # (
+    parameter M = 4, // Differential delay
+    parameter InOutDataWidth = 18 // Input and output data width
+)
+(
+    input logic                                 Clk_i,
+    input logic                                 Rst_i,
+    input logic     signed [InOutDataWidth-1:0] Data_i,
+    input logic                                 DataVal_i,
+
+    output logic    signed [InOutDataWidth-1:0] Data_o,
+    output logic                                DataVal_o
+);
+
+//================================================================================
+//								REG/WIRE
+//================================================================================
+logic signed [InOutDataWidth-1:0] combDataReg;
+logic combDataValReg;
+
+logic signed [InOutDataWidth-1:0] delayedDataReg [0:M-1];
+
+logic dataValReg;
+
+//================================================================================
+//								ASSIGNMENTS
+//================================================================================
+assign Data_o = combDataReg;
+assign DataVal_o = combDataValReg;
+
+//================================================================================
+//								CODING
+//================================================================================
+genvar i;
+generate
+    for (i = 0; i < M; i++) begin : comb_stage
+        always_ff @(posedge Clk_i) begin 
+            if (Rst_i) begin
+                delayedDataReg[i] <= 0;
+            end 
+            else begin
+                if (DataVal_i) begin
+                    if (i == 0) begin
+                        delayedDataReg[i] <= Data_i;
+                    end 
+                    else begin
+                        delayedDataReg[i] <= delayedDataReg[i-1];
+                    end
+                end
+            end
+        end
+    end
+endgenerate
+
+always_ff @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        dataValReg <= 0;
+    end
+    else begin 
+        if (DataVal_i) begin
+            dataValReg <= 1;
+        end  
+        else begin
+            dataValReg <= 0;
+        end
+    end
+end
+
+always_ff @(posedge Clk_i) begin 
+    if (Rst_i) begin
+        combDataReg <= 0;
+        combDataValReg <= 0;
+    end 
+    else begin
+        if (DataVal_i) begin
+            combDataReg <= Data_i - delayedDataReg[M-1]; // y[n] = x[n-M] - x[n]
+            combDataValReg <= 1;
+        end 
+        else begin
+            combDataValReg <= 0;
+        end
+    end
+end
+
+endmodule

src/src/FftDataFiltering/TestCicFilter/CicDecimator.sv

@@ -0,0 +1,71 @@
+module CicDecimator #
+(
+    parameter InDataWidth = 18
+)
+(
+    input logic                                 Clk_i,
+    input logic                                 Rst_i,
+    input logic     [2:0]                       DecimFactor_i, // Decimation factor (1, 2, 4, 8)
+    input logic     signed [InDataWidth-1:0]    Data_i,
+    input logic                                 DataVal_i,
+
+    output logic    signed [InDataWidth-1:0]    Data_o,
+    output logic                                DataVal_o
+);
+
+//================================================================================
+//								REG/WIRE
+//================================================================================
+logic           [3:0]                   decimCnt;
+logic           [2:0]                   decimFactor;
+
+logic signed    [InDataWidth - 1 : 0]   decimDataReg;
+logic                                   decimDataValReg;
+
+//================================================================================
+//								ASSIGNMENTS
+//================================================================================
+assign Data_o = decimDataReg;
+assign DataVal_o = decimDataValReg;
+
+//================================================================================
+//								CODING
+//================================================================================
+always_ff @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        decimCnt <= 0;
+    end
+    else begin 
+        if (DataVal_i) begin
+            if (decimCnt == DecimFactor_i - 1) begin
+                decimCnt <= 0;
+            end
+            else begin
+                decimCnt <= decimCnt + 1;
+            end
+        end  
+    end
+end
+
+always_ff @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        decimDataReg <= 0;
+        decimDataValReg <= 0;
+    end
+    else begin 
+        if (DataVal_i) begin
+            if (decimCnt == DecimFactor_i - 1) begin
+                decimDataReg <= Data_i;
+                decimDataValReg <= 1;
+            end
+            else begin
+                decimDataValReg <= 0;
+            end
+        end
+        else begin
+            decimDataValReg <= 0; 
+        end
+    end
+end
+
+endmodule

src/src/FftDataFiltering/TestCicFilter/CicFilterNewWrapper.sv

@@ -0,0 +1,88 @@
+module CicFilterNewWrapper #(
+    parameter InDataWidth = 14,
+    parameter N = 6, // Number of stages
+    parameter M = 4, // Differential delay
+    parameter OutDataWidth = 17
+)
+(
+    input logic 								    Clk_i,
+    input logic 			[2:0]                   DecimFactor_i, // Decimation factor (1, 2, 4, 8)
+	input logic                     			    Rst_i,
+
+    input logic                     			    DataVal_i,
+    input logic 	signed	[InDataWidth-1:0]       Data_i,
+
+    output logic 								    DataVal_o,
+    output logic 	signed	[OutDataWidth-1:0] 	    Data_o
+);
+
+//================================================================================
+//								REG/WIRE
+//================================================================================
+/* Integrator Block */
+logic signed					[OutDataWidth-1:0] 	integratedDataIn 	[N-1:0];
+logic 										        integratedDataValIn [N-1:0];
+logic signed					[OutDataWidth-1:0] 	integratedDataOut 	[N-1:0];
+logic 											    integratedValOut 	[N-1:0];
+/* Decim Block */
+logic signed 				    [OutDataWidth-1:0] 	decimDataOut;
+logic 											    decimDataValOut;
+/* Comb Filter Block */
+logic signed					[OutDataWidth-1:0] 	combDataIn			[N-1:0];
+logic 											    combDataValIn		[N-1:0];
+logic signed					[OutDataWidth-1:0] 	combDataOut			[N-1:0];
+logic 											    combDataValOut		[N-1:0];
+
+/* ShTest */
+logic signed					[InDataWidth-1:0] 	shTest;
+
+//================================================================================
+//								ASSIGNMENTS
+//================================================================================
+assign Data_o 		= decimDataOut;
+assign DataVal_o 	= decimDataValOut;
+
+assign shTest 		= decimDataOut>>> 14;
+//================================================================================
+//								CODING
+//================================================================================
+genvar i;
+/* Integrators */
+generate
+    for (i = 0; i < N; i++) begin : gen_integrators
+    
+        assign integratedDataIn[i] = (i == 0) ? Data_i : combDataOut[i-1];
+        assign integratedDataValIn[i] = (i == 0) ? DataVal_i : combDataValOut[i-1];
+
+		CicIntDiffBlock #(
+			.M              (M),
+			.InDataWidth	(OutDataWidth),
+			.OutDataWidth   (OutDataWidth)
+		) CicIntDiff (
+			.Clk_i          (Clk_i),
+			.Rst_i          (Rst_i),
+			.Data_i         (integratedDataIn[i]),
+			.DataVal_i      (integratedDataValIn[i]),
+			.Data_o         (combDataOut[i]),
+			.DataVal_o      (combDataValOut[i])
+		);
+        
+    end
+endgenerate
+
+/* Decimation */
+CicDecimator #(
+    .InDataWidth			(OutDataWidth)
+) decimator_inst (
+    .Clk_i          		(Clk_i),
+    .Rst_i          		(Rst_i),
+    .DecimFactor_i  		(DecimFactor_i),
+    .DataVal_i      		(combDataValOut[N-1]),
+    .Data_i         		(combDataOut[N-1]),
+    .DataVal_o      		(decimDataValOut),
+    .Data_o         		(decimDataOut)
+);
+
+
+
+endmodule

src/src/FftDataFiltering/TestCicFilter/CicFilterNewWrapperNoIntDiff.sv

@@ -0,0 +1,106 @@
+module CicFilterNewWrapperNoIntDiff #(
+    parameter InDataWidth = 14,
+    parameter N = 6, // Number of stages
+    parameter M = 4, // Differential delay
+    parameter OutDataWidth = 17
+)
+(
+    input logic 								    Clk_i,
+    input logic 			[2:0]                   DecimFactor_i, // Decimation factor (1, 2, 4, 8)
+	input logic                     			    Rst_i,
+
+    input logic                     			    DataVal_i,
+    input logic 	signed	[InDataWidth-1:0]       Data_i,
+
+    output logic 								    DataVal_o,
+    output logic 	signed	[OutDataWidth-1:0] 	    Data_o
+);
+
+//================================================================================
+//								REG/WIRE
+//================================================================================
+/* Integrator Block */
+logic signed					[OutDataWidth-1:0] 	integratedDataIn 	[N-1:0];
+logic 										        integratedDataValIn [N-1:0];
+logic signed					[OutDataWidth-1:0] 	integratedDataOut 	[N-1:0];
+logic 											    integratedValOut 	[N-1:0];
+/* Decim Block */
+logic signed 				    [OutDataWidth-1:0] 	decimDataOut;
+logic 											    decimDataValOut;
+/* Comb Filter Block */
+logic signed					[OutDataWidth-1:0] 	combDataIn			[N-1:0];
+logic 											    combDataValIn		[N-1:0];
+logic signed					[OutDataWidth-1:0] 	combDataOut			[N-1:0];
+logic 											    combDataValOut		[N-1:0];
+
+/* ShTest */
+logic signed					[InDataWidth-1:0] 	shTest;
+
+//================================================================================
+//								ASSIGNMENTS
+//================================================================================
+assign Data_o 		= combDataOut[N-1];
+assign DataVal_o 	= combDataValOut[N-1];
+
+assign shTest 		= combDataOut[N-1]>>> 14;
+//================================================================================
+//								CODING
+//================================================================================
+genvar i;
+/* Integrators */
+generate
+    for (i = 0; i < N; i++) begin : gen_integrators
+    
+        assign integratedDataIn[i] = (i == 0) ? Data_i : integratedDataOut[i-1];
+        assign integratedDataValIn[i] = (i == 0) ? DataVal_i : integratedValOut[i-1];
+
+        CicIntegrator #(
+            .InDataWidth    (OutDataWidth),
+            .OutDataWidth   (OutDataWidth)
+        ) integrator_inst (
+            .Clk_i          (Clk_i),
+            .Rst_i          (Rst_i),
+            .Data_i         (integratedDataIn[i]),
+            .DataVal_i      (integratedDataValIn[i]),
+            .Data_o         (integratedDataOut[i]),
+            .DataVal_o      (integratedValOut[i])
+        );
+    end
+endgenerate
+
+/* Decimation */
+CicDecimator #(
+    .InDataWidth			(OutDataWidth)
+) decimator_inst (
+    .Clk_i          		(Clk_i),
+    .Rst_i          		(Rst_i),
+    .DecimFactor_i  		(DecimFactor_i),
+    .DataVal_i      		(integratedValOut[N-1]),
+    .Data_i         		(integratedDataOut[N-1]),
+    .DataVal_o      		(decimDataValOut),
+    .Data_o         		(decimDataOut)
+);
+
+genvar j;
+/* Comb Filters */
+generate
+    for (j = 0; j < N; j++) begin : gen_comb_filters
+
+        assign combDataIn[j] = (j == 0) ? decimDataOut : combDataOut[j-1];
+        assign combDataValIn[j] = (j == 0) ? decimDataValOut : combDataValOut[j-1];
+
+        CicCombFilter #(
+            .InOutDataWidth (OutDataWidth),
+            .M              (M)
+        ) comb_filter_inst (
+            .Clk_i          (Clk_i),
+            .Rst_i          (Rst_i),
+            .DataVal_i      (combDataValIn[j]),
+            .Data_i         (combDataIn[j]),
+            .DataVal_o      (combDataValOut[j]),
+            .Data_o         (combDataOut[j])
+        );
+    end
+endgenerate
+
+endmodule

src/src/FftDataFiltering/TestCicFilter/CicIntDiffBlock.sv

@@ -0,0 +1,63 @@
+module CicIntDiffBlock #(
+    parameter M = 4, // Differential delay
+    parameter InDataWidth = 14,
+    parameter OutDataWidth = 17
+)
+(
+    input logic                                 Clk_i,
+    input logic                                 Rst_i,
+    input logic     signed [InDataWidth-1:0]    Data_i,
+    input logic                                 DataVal_i,
+
+    output logic    signed [OutDataWidth-1:0]   Data_o,
+    output logic                                DataVal_o
+
+);
+//================================================================================
+//								REG/WIRE
+//================================================================================
+/* Integrator Block */
+logic signed                  [OutDataWidth-1:0]    integratedDataOut;
+logic                                               integratedValOut;
+
+/* Comb Filter Block */
+logic signed                  [OutDataWidth-1:0]    combDataOut;
+logic                                               combDataValOut;
+
+//================================================================================
+//								ASSIGNMENTS
+//================================================================================
+assign Data_o      = combDataOut;
+assign DataVal_o   = combDataValOut;
+
+//================================================================================
+//								CODING
+//================================================================================
+/* Integrator */
+CicIntegrator #(
+    .InDataWidth    (InDataWidth),
+    .OutDataWidth   (OutDataWidth)
+) integrator_inst (
+    .Clk_i          (Clk_i),
+    .Rst_i          (Rst_i),
+    .DataVal_i      (DataVal_i),
+    .Data_i         (Data_i),
+    .DataVal_o      (integratedValOut),
+    .Data_o         (integratedDataOut)
+);
+
+/* Comb Filter */
+CicCombFilter #(
+    .InOutDataWidth (OutDataWidth),
+    .M              (M)
+) comb_filter_inst (
+    .Clk_i          (Clk_i),
+    .Rst_i          (Rst_i),
+    .DataVal_i      (integratedValOut),
+    .Data_i         (integratedDataOut),
+    .DataVal_o      (combDataValOut),
+    .Data_o         (combDataOut)
+);
+
+
+endmodule

src/src/FftDataFiltering/TestCicFilter/CicIntegrator.sv

@@ -0,0 +1,43 @@
+module CicIntegrator #(
+    parameter InDataWidth = 18, // Input data width
+    parameter OutDataWidth = 18 // Output data width
+)
+(
+    input logic                                 Clk_i,
+    input logic                                 Rst_i,
+    input logic     signed [InDataWidth-1:0]    Data_i,
+    input logic                                 DataVal_i,
+
+    output logic    signed [OutDataWidth-1:0]   Data_o,
+    output logic                                DataVal_o
+);
+//================================================================================
+//								REG/WIRE
+//================================================================================
+logic signed [OutDataWidth-1:0] accumulatorDataOut; 
+logic accumulatorValOut;
+//================================================================================
+//								ASSIGNMENTS
+//================================================================================
+assign Data_o = accumulatorDataOut;
+assign DataVal_o = accumulatorValOut;
+//================================================================================
+//								CODING
+//================================================================================
+always_ff @(posedge Clk_i) begin 
+    if (Rst_i) begin
+        accumulatorDataOut <= 0;
+        accumulatorValOut <= 0;
+    end 
+    else begin
+        if (DataVal_i) begin
+            accumulatorDataOut <= Data_i + accumulatorDataOut;
+            accumulatorValOut <= 1;
+        end 
+        else begin
+            accumulatorValOut <= 0;
+        end
+    end
+end
+
+endmodule

src/src/Sim/DecimFilterWrapperTb.v

@@ -6,16 +6,17 @@ module DecimFilterWrapperTb	();
 //	PARAMETERS
 //================================================================================
 
-parameter	N	=	8;
-parameter	M	=	4;
+parameter	N	=   6; // Order of the filter
+parameter	M	=	8;// Delay in CIC filter
 parameter	InDataWidth	=	14;
 
 parameter	K = N*20*($log10(M));
 parameter	BitGworth = $ceil(2**(K/20));
-parameter	integer MaxWidth = InDataWidth+BitGworth;
+parameter	integer MaxWidth = InDataWidth+BitGworth + 15;
 
-parameter	[31:0]	Nco1PhaseInc	=	32'h40000000;
-parameter	[31:0]	Nco2PhaseInc	=	32'h0F5C28F6;
+// parameter	[31:0]	Nco1PhaseInc	=	32'h40000000;//12.5 MHz 
+parameter	[31:0]	Nco1PhaseInc	=	32'h23d70a3d;//7 MHz 
+parameter	[31:0]	Nco2PhaseInc	=	32'h0f5c28f6;// 3 MHz
 
 
 
@@ -31,7 +32,7 @@ reg		[2:0]	decimFactor;
 
 reg		[31:0]	tbCnt;
 
-wire	oscWind	=	(tbCnt>=100&tbCnt<=199)?	1'b1:1'b0;
+wire	oscWind	=	(tbCnt>=100&tbCnt<=299)?	1'b1:1'b0;
 
 wire	resultVal;
 wire	impResponseVal;
@@ -41,13 +42,15 @@ wire	signed	[InDataWidth-1:0]	ncoSin1;
 wire	signed	[InDataWidth-1:0]	ncoSin2;
 wire	signed	[InDataWidth-1:0]	ncoSin3;
 
-wire	signed	[InDataWidth-1:0]	filteredDataOut;
-wire	signed	[InDataWidth-1:0]	impResponse;
+wire	signed	[MaxWidth-1:0]		filteredDataOut;
+wire	signed	[MaxWidth-1:0]		impResponse;
 
 wire	signed	[InDataWidth*2-1:0]	adcDataMixed	=	(ncoSin1*ncoSin2);
 wire	signed	[InDataWidth-1:0]	adcDataMixedCut	=	adcDataMixed[26-:14];
 
-wire	signed	[InDataWidth-1:0]	sinAdd	=	(ncoSin1>>>1)+(ncoSin2>>>1);
+// wire	signed	[InDataWidth-1:0]	sinAdd	=	(ncoSin1>>>1)+(ncoSin2>>>1);
+wire    signed  [2*InDataWidth-1:0] sinMultFull = (ncoSin2*ncoSin1);
+wire	signed	[InDataWidth-1:0]	sinMult =	sinMultFull[(2*InDataWidth-1)-:InDataWidth];
 
 wire	signed	[InDataWidth-1:0]	singlePulse	=	(tbCnt==100)?	14'h1fff:14'h0;
 
@@ -81,7 +84,7 @@ end
 always	@(posedge	Clk50)	begin
 	if	(!Rst)	begin
 		if (tbCnt == 100) begin
-			decimFactor	<= 2;
+			decimFactor	<= 4;
 		end
 		// end else if (tbCnt == 5400) begin
 			// decimFactor	<= 1;
@@ -99,7 +102,7 @@ always	@(posedge	Clk50)	begin
 			// decimFactor	<= 7;
 		// end
 	end else begin
-	 decimFactor <= 2;
+	 decimFactor <= 4;
 	end 
 end
 
@@ -145,7 +148,7 @@ ncoInst2
 	.Val_o		()
 );
 
-DecimFilterWrapperTest	
+CicFilterNewWrapperNoIntDiff	
 #(	
 	.InDataWidth	(InDataWidth),
 	.N	(N),
@@ -159,13 +162,13 @@ DecimFilter
 	.Rst_i			(Rst),
 	.DataVal_i		(oscWind),
 
-	.Data_i		(sinAdd),
+	.Data_i		(sinMult),
 	
 	.Data_o	(filteredDataOut),
 	.DataVal_o	(resultVal)
 );
 
-DecimFilterWrapperTest	
+CicFilterNewWrapperNoIntDiff	
 #(	
 	.InDataWidth	(InDataWidth),
 	.N	(N),
@@ -175,14 +178,32 @@ DecimFilterWrapperTest
 ImpulseResponseFilter
 (
 	.Clk_i			(Clk50),
-	.DecimFactor_i	(1),
+	.DecimFactor_i	(decimFactor),
 	.Rst_i			(Rst),
 	.DataVal_i		(oscWind),
 
-	.Data_i		(singlePulse),
+	.Data_i			(singlePulse),
 	
-	.Data_o	(impResponse),
-	.DataVal_o	(impResponseVal)
+	.Data_o			(impResponse),
+	.DataVal_o		(impResponseVal)
+);
+
+CicFilterNewWrapperNoIntDiff
+#(
+	.InDataWidth	(InDataWidth),
+	.N	(N),
+	.M	(M),
+	.OutDataWidth	(MaxWidth)
+)
+CicFilterInst
+(
+	.Clk_i				(Clk50),
+	.DecimFactor_i		(decimFactor),
+	.Rst_i				(Rst),
+	.DataVal_i			(oscWind),
+	.Data_i				(sinMult),
+	.Data_o				(),
+	.DataVal_o			()
 );
 	
 always	@(posedge	Clk50)	begin
@@ -193,7 +214,7 @@ always	@(posedge	Clk50)	begin
 			// $display("AdcData is %d", sinAdd);
 			// $fwrite(inSignal,"%d\n",   sinAddExt18);
 			// $fwrite(inSignal,"%d\n",   adcDataMixedCut);
-			$fwrite(inSignal,"%d\n",   sinAdd);
+			$fwrite(inSignal,"%d\n",   sinMult);
 		end	
 	end	
 end
@@ -221,6 +242,15 @@ always	@(posedge	Clk50)	begin
 	end
 end 
 
+always @(posedge Clk50) begin
+	if (tbCnt == 32'd1000) begin 
+		$fclose(inSignal);
+		$fclose(filteredData);
+		$fclose(impResp);
+		$finish;
+	end
+end
+
 endmodule
 
 

src/src/Sim/FilteredData.txt

@@ -1,100 +1,50 @@
-    -1
-     0
-     1
-     8
-    31
-    92
-   227
-   480
-   889
-  1458
-  2138
-  2811
-  3303
-  3426
-  3035
-  2082
-   645
- -1082
- -2824
- -4287
- -5220
- -5456
- -4942
- -3739
- -2012
-    -4
-  2005
-  3731
-  4933
-  5442
-  5186
-  4201
-  2626
-   682
- -1358
- -3208
- -4607
- -5360
- -5360
- -4607
- -3208
- -1358
-   682
-  2626
-  4201
-  5186
-  5442
-  4934
-  3732
-  2005
-    -3
- -2012
- -3738
- -4940
- -5448
- -5192
- -4208
- -2633
-  -689
-  1351
-  3201
-  4600
-  5352
-  5352
-  4600
-  3201
-  1351
-  -689
- -2633
- -4208
- -5193
- -5449
- -4940
- -3738
- -2012
-    -4
-  2005
-  3731
-  4933
-  5442
-  5186
-  4201
-  2626
-   682
- -1358
- -3208
- -4607
- -5360
- -5360
- -4607
- -3208
- -1358
-   682
-  2626
-  4201
-  5186
-  5442
-  4934
-  3732
-  2005
+                 134360
+                2151862
+               12043849
+               41287865
+              108183306
+              240485089
+              476834120
+              867907764
+             1478200296
+             2378782480
+             3632538722
+             5289192107
+             7379143406
+             9898575315
+            12803212041
+            16003478878
+            19351857136
+            22657402578
+            25721380807
+            28341869354
+            30324623273
+            31519546794
+            31829025993
+            31214535370
+            29730112438
+            27505456142
+            24696458040
+            21494999216
+            18119539691
+            14762904617
+            11595819356
+             8765878008
+             6346713166
+             4356035544
+             2801272577
+             1647003314
+              822409860
+              272783678
+              -66585542
+             -274557327
+             -390179550
+             -438893908
+             -463164144
+             -474885280
+             -470418460
+             -470466854
+             -476101743
+             -471325369
+             -469768178
+             -475852480

src/src/Sim/FreqDomainCicFilt.py

@@ -4,7 +4,7 @@ import sys
 import numpy as np
 import matplotlib.pyplot as plt
 
-
+R = 4 # Decimation factor
 
 # Open the input file and read the impulse response data
 def read_impulse_response(file_path):
@@ -67,7 +67,9 @@ def main():
     freq_axis = np.fft.fftfreq(len(input_signal_time_domain), 1/fs) / 1e6
     
     plt.figure(figsize=(10, 6))
-    half_len = len(freq_axis) // 2
+    half_R = R // 2
+    Denominator = R if R > 1 else 2  
+    half_len = len(freq_axis) // Denominator
     plt.plot(freq_axis[:half_len], np.abs(input_signal_frequency_response[:half_len]), label='Input Signal Frequency Response')
     plt.title('Input Signal Frequency Response')
     plt.xlabel('Frequency (MHz)')
@@ -79,8 +81,19 @@ def main():
 
     cic_filter_impulse_response = read_impulse_response('C:\S5243_FFT_REPO\src\src\Sim\ImpResp.txt')
     cic_filter_frequency_response = convert_to_frequency_domain(cic_filter_impulse_response)
-    plot_frequency_response(cic_filter_frequency_response, cic_filter_impulse_response)
-    print("CIC filter frequency response conversion completed successfully.")
+    # plot the frequency response of the CIC filter in dB
+    plt.figure(figsize=(10, 6))
+    plt.plot(freq_axis[:half_len], 20 * np.log10(np.abs(cic_filter_frequency_response[:half_len])), label='CIC Filter Frequency Response (dB)')
+    plt.title('CIC Filter Frequency Response')
+    plt.xlabel('Frequency (MHz)')
+    plt.ylabel('Magnitude (dB)')
+    plt.ylim(-300, 10) 
+    plt.grid()
+    plt.legend()
+    plt.xlim(0, fs/(2*R*1e6))
+    plt.show()
+
+    
     
 if __name__ == "__main__":
     main()

src/src/Sim/ImpResp.txt

@@ -1,100 +1,50 @@
-     0
-     3
-    17
-    59
-   160
-   363
-   713
-  1235
-  1911
-  2663
-  3363
-  3863
-  4045
-  3863
-  3363
-  2663
-  1911
-  1235
-   713
-   363
-   160
-    59
-    17
-     3
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
-     0
+                 458696
+                6487272
+               35778288
+              126993264
+              348150264
+              805011480
+             1649470816
+             3087941472
+             5386991352
+             8856567896
+            13810812336
+            20526121776
+            29199211272
+            39905175912
+            52555552896
+            66856383616
+            82273156176
+            98051774352
+           113295552992
+           127049093856
+           138382161456
+           146473558896
+           150695003712
+           150695003712
+           146473558896
+           138382161456
+           127049093856
+           113295552992
+            98051774352
+            82273156176
+            66856383616
+            52555552896
+            39905175912
+            29199211272
+            20526121776
+            13810812336
+             8856567896
+             5386991352
+             3087941472
+             1649470816
+              805011480
+              348150264
+              126993264
+               35778288
+                6487272
+                 458696
+                      0
+                      0
+                      0
+                      0

src/src/Sim/InputSignal.txt

@@ -1,100 +1,200 @@
-   -52
-  2766
-  5195
-  1654
- -2119
-  -355
-  1463
- -2172
- -5499
- -2813
-   270
- -1931
- -3857
-    -2
-  3856
-  1929
-  -270
-  2811
-  5498
-  2170
- -1463
-   353
-  2119
- -1657
- -5196
- -2769
-    51
- -2378
- -4475
-  -701
-  3173
-  1355
-  -648
-  2678
-  5631
-  2548
-  -889
-  1036
-  2819
- -1039
- -4749
- -2550
-     7
- -2681
- -4990
- -1357
-  2465
-   699
- -1164
-  2375
-  5586
-  2766
-  -443
-  1654
-  3519
-  -355
- -4175
- -2172
-   139
- -2813
- -5368
- -1931
-  1781
-    -2
- -1782
-  1929
-  5368
-  2811
-  -140
-  2170
-  4175
-   353
- -3519
- -1657
-   442
- -2769
- -5587
- -2378
-  1163
-  -701
- -2465
-  1355
-  4990
-  2678
-    -7
-  2548
-  4749
-  1036
- -2819
- -1039
-   889
- -2550
- -5631
- -2681
-   648
- -1357
- -3173
-   699
-  4474
-  2375
+  1722
+  1722
+   406
+  -670
+  -481
+   166
+  -118
+ -1260
+ -1753
+  -713
+   843
+  1304
+   549
+    -1
+   549
+  1304
+   843
+  -713
+ -1753
+ -1260
+  -118
+   166
+  -481
+  -670
+   406
+  1722
+  1722
+   406
+  -670
+  -481
+   166
+  -118
+ -1260
+ -1753
+  -713
+   843
+  1304
+   549
+    -1
+   549
+  1304
+   843
+  -713
+ -1753
+ -1260
+  -118
+   166
+  -481
+  -670
+   406
+  1722
+  1722
+   406
+  -670
+  -481
+   166
+  -118
+ -1260
+ -1753
+  -713
+   843
+  1304
+   549
+    -1
+   549
+  1304
+   843
+  -713
+ -1753
+ -1260
+  -118
+   166
+  -481
+  -670
+   406
+  1722
+  1722
+   406
+  -670
+  -481
+   166
+  -118
+ -1260
+ -1753
+  -713
+   843
+  1304
+   549
+    -1
+   549
+  1304
+   843
+  -713
+ -1753
+ -1260
+  -118
+   166
+  -481
+  -670
+   406
+  1722
+  1722
+   406
+  -670
+  -481
+   166
+  -118
+ -1260
+ -1753
+  -713
+   843
+  1304
+   549
+    -1
+   549
+  1304
+   843
+  -713
+ -1753
+ -1260
+  -118
+   166
+  -481
+  -670
+   406
+  1722
+  1722
+   406
+  -670
+  -481
+   166
+  -118
+ -1260
+ -1753
+  -713
+   843
+  1304
+   549
+    -1
+   549
+  1304
+   843
+  -713
+ -1753
+ -1260
+  -118
+   166
+  -481
+  -670
+   406
+  1722
+  1722
+   406
+  -670
+  -481
+   166
+  -118
+ -1260
+ -1753
+  -713
+   843
+  1304
+   549
+    -1
+   549
+  1304
+   843
+  -713
+ -1753
+ -1260
+  -118
+   166
+  -481
+  -670
+   406
+  1722
+  1722
+   406
+  -670
+  -481
+   166
+  -118
+ -1260
+ -1753
+  -713
+   843
+  1304
+   549
+    -1
+   549
+  1304
+   843
+  -713
+ -1753
+ -1260
+  -118
+   166
+  -481
+  -670
+   406

src/src/Sim/СicFilter.py

@@ -0,0 +1,109 @@
+import numpy as np
+import matplotlib.pyplot as plt
+
+
+
+class CICFilter:
+    def __init__(self, decimation_factor, delay, order):
+        self.decimation_factor = decimation_factor
+        self.delay = delay
+        self.order = order
+
+    def integrate(self, input_signal):
+      output = np.copy(input_signal)
+      for _ in range(self.order):
+          output = np.cumsum(output)
+      return output
+
+    def comb(self, decimated_signal):
+        output = np.copy(decimated_signal)
+        for _ in range(self.order):
+            delayed = np.zeros_like(output)
+            delayed[self.delay:] = output[:-self.delay]
+            output = output - delayed
+        return output
+    
+    def decimate(self, integrated_signal):
+        # Децимация: выбираем каждый N-й элемент
+        return integrated_signal[::self.decimation_factor]
+    
+
+    def filter(self, input_signal):
+        # 1. Каскад интеграторов
+        integrated_signal = self.integrate(input_signal)
+
+        # 2. Децимация
+        decimated_signal = self.decimate(integrated_signal)
+
+        # 3. Каскад comb-фильтров
+        output_signal = self.comb(decimated_signal)
+
+        return output_signal
+    
+    def get_filter_freq_resp(self, num_points=1024):
+        # Подаём дельта-функцию на вход фильтру
+        impulse = np.zeros(num_points)
+        impulse[0] = 1.0  # Дельта-функция
+        output_signal = self.filter(impulse)
+        # Вычисляем частотную характеристику с помощью БПФ
+        freq_response = np.fft.fft(output_signal, num_points)
+        # Нормализуем частотную характеристику
+        freq_response /= np.max(np.abs(freq_response))
+        # Создаем массив частот
+        freq = np.fft.fftfreq(num_points, d=1/(50e6/self.decimation_factor))
+        # Возвращаем частоты и амплитуду частотной характеристики
+        return freq, np.abs(freq_response)
+    
+    # # Calculate coefficients for the FIR filter to compensate the CIC frequency response
+    # def get_compensation_coefficients(self, cic_freq_response, target_freq_response):
+
+
+def main():
+    decimation_factor = 4
+    delay = 8
+    order = 6
+    num_samples = 100000
+    # Input signal - multiplication of a 3 MHz sine and 6 MHz sine
+    fs = 50e6  # Sampling frequency
+    f1 = 7e6  # Frequency of first sine wave
+    f2 = 3e6  # Frequency of second sine wave
+    t = np.arange(num_samples) / fs
+    input_signal = np.sin(2 * np.pi * f1 * t) * np.sin(2 * np.pi * f2 * t)
+    # Plot the input signal in the frequency domain
+    plt.figure(figsize=(10, 6))
+    plt.magnitude_spectrum(input_signal, Fs=fs, scale='dB', color='C0')
+    plt.title('Input Signal in Frequency Domain')
+    plt.xlabel('Frequency [Hz]')
+    plt.ylabel('Magnitude [dB]')
+    plt.grid()
+    plt.tight_layout()
+    plt.show()
+    # Create CIC filter instance
+    cic_filter = CICFilter(decimation_factor, delay, order)
+    # Filter the input signal
+    output_signal = cic_filter.filter(input_signal)
+    # Plot the output signal in the frequency domain
+    plt.magnitude_spectrum(output_signal, Fs=fs/decimation_factor, scale='dB', color='C1')
+    plt.title('Output Signal in Frequency Domain')
+    plt.xlabel('Frequency [Hz]')
+    plt.ylabel('Magnitude [dB]')
+    plt.grid()
+    plt.tight_layout()
+    plt.show()
+    # Get frequency response of the CIC filter
+    freq, freq_response = cic_filter.get_filter_freq_resp()
+    # Plot the frequency response
+    plt.figure(figsize=(10, 6))
+    # Normalize frequency axis to 1
+    freq_normalized = freq[:len(freq)//2]
+    plt.plot(freq_normalized, 20 * np.log10(freq_response[:len(freq)//2]), label='CIC Filter Frequency Response (Normalized)')
+    plt.title('CIC Filter Frequency Response')
+    plt.xlabel('Frequency [Hz]')
+    plt.ylabel('Magnitude [dB]')
+    plt.grid()
+    plt.legend()
+    plt.tight_layout()
+    plt.show()
+    
+if __name__ == "__main__":
+    main()