Тестовые изменения фильтров.

src/src/FftDataFiltering/combFilterBlock.v

@@ -13,52 +13,38 @@ module combFilterBlock
 	output DataValid_o
 );
 
-reg ndReg;
-reg	signed	[inOutDataWidth-1:0]	inReg;
-reg signed	[inOutDataWidth-1:0]	sumResult;
+
+	
+reg signed	[inOutDataWidth-1:0] sumResult;
 reg	dataValid;
-reg	signed	[inOutDataWidth-1:0] delData	[M-1:0];
+reg	signed	[inOutDataWidth-1:0] delData;
 
-	always	@(posedge Clk_i)	begin
-		if	(!Rst_i)	begin
-			ndReg <= DataNd_i;
-			if	(DataNd_i)	begin
-				inReg	<=	Data_i;
-			end
-		end	else	begin
-			ndReg	<=	0;
-			inReg	<=	0;
+assign Data_o = sumResult;
+assign DataValid_o = dataValid;
+	
+always @(posedge Clk_i) begin
+	if (Rst_i) begin
+		delData <= 0;
+	end else begin
+		if (DataNd_i) begin
+			delData	<= Data_i;
 		end
 	end
+end
 
-genvar i;
-generate 
-	for (i=0; i<M; i=i+1)	begin:combGen
-		always	@(posedge	Clk_i)	begin
-			if	(i==0)	begin
-				delData	[i]	<=	inReg;
-			end	else	begin
-				delData	[i]	<=	delData[i-1];
-			end
+always @(posedge Clk_i or posedge Rst_i) begin
+	if (Rst_i) begin
+		sumResult <= 0;
+		dataValid <= 1'b0;
+	end else begin
+		if (DataNd_i) begin
+			sumResult <= Data_i-delData;
+			dataValid <= 1'b1;
+		end else begin
+			dataValid <= 1'b0;
 		end
 	end
-	
-	always	@(posedge	Clk_i)	begin
-		if	(!Rst_i)	begin
-			if	(ndReg)	begin
-				sumResult	<=	inReg+-delData[M-1];
-				dataValid	<=	1'b1;
-			end	else	begin
-				dataValid	<=	1'b0;
-				// sumResult	<=	0;
-			end
-		end	else	begin
-			sumResult	<=	0;
-			dataValid	<=	1'b0;
-		end
-	end
-endgenerate
+end
+
 
-assign	Data_o	=	sumResult;
-assign	DataValid_o	=	dataValid;
 endmodule

src/src/FftDataFiltering/decimBlock.v

@@ -58,39 +58,21 @@ always	@(posedge	Clk_i)	begin
 		if	(DataNd_i)	begin
 			if	(decimCnt	==	decimFactor-1)	begin
 				decimCnt	<=	{decimCntWidth{1'b0}};
-				// valReg		<=	DataNd_i;
-				// dataReg		<=	Data_i;
+				// valReg		<=	1'b1;
 			end	else	begin
 				decimCnt	<=	decimCnt+7'd1;
 				// valReg		<=	1'b0;
 			end
-			// valReg		<=	DataNd_i;
 		end	else	begin
 			decimCnt	<=	{decimCntWidth{1'b0}};
 			// valReg		<=	1'b0;
 		end
 	end	else	begin
-		decimCnt	<=	{decimCntWidth{1'b0}};
 		// valReg		<=	1'b0;
-		// dataReg	<=	Data_i;
-	end
-end
-	
-always	@(posedge	Clk_i)	begin
-	if	(!Rst_i)	begin
-		// if	(decimCnt	==	decimFactor-1)	begin
-		if	(decimCnt	==	0)	begin
-			dataReg		<=	Data_i;
-			valReg		<=	DataNd_i;
-		end	else begin
-			valReg		<=	1'b0;
-		end
-	end	else	begin
-		dataReg	<=	0;
-		valReg	<=	1'b0;
+		decimCnt	<=	{decimCntWidth{1'b0}};
 	end
 end
 
-assign	Data_o	=	dataReg;
-assign	DataValid_o	=	valReg;
+assign	Data_o	=	Data_i;
+assign	DataValid_o	=	DataNd_i? (decimCnt	==	0):1'b0;
 endmodule

src/src/FftDataFiltering/intFilterBlock.v

@@ -1,5 +1,6 @@
 module intFilterBlock 
-#(	parameter	inOutDataWidth	=	18,
+#(	
+	parameter	inOutDataWidth	=	18,
 	parameter	filteredDataWidth	=	25
 )
 (
@@ -11,42 +12,25 @@ module intFilterBlock
 	output DataValid_o
 );
 
-	reg [1:0] ndShReg;
+	reg [filteredDataWidth-1:0] outAcc;
+	reg outVal;
 	
-	always @ (posedge Clk_i)	begin
-		if	(!Rst_i)	begin
-			ndShReg <= {ndShReg[0:0], DataNd_i};
-		end	else	begin
-			ndShReg <= 2'h0;
-		end
-	end
+	assign Data_o = outAcc;
+	assign DataValid_o = outVal;
 	
-	reg signed [inOutDataWidth-1:0] inReg;
-	reg signed [filteredDataWidth-1:0] sumResult;
-	
-	always	@(posedge	Clk_i)	begin
-		if (!Rst_i)	begin
-			if (DataNd_i)	begin
-				inReg <= Data_i;
-			end
-		end	else	begin
-			inReg	<= 0;
+	always @(posedge Clk_i or posedge Rst_i) begin
+		if (Rst_i) begin
+			outAcc <= 0;
+		end else begin
+			if (DataNd_i) begin
+				outAcc <= outAcc+Data_i;
+				outVal <= 1'b1;
+			end else begin
+				outAcc <= 0;
+				outVal <= 1'b0;
+			end 
 		end
 	end
 	
-	always @ (posedge Clk_i)	begin
-		if (!Rst_i)	begin
-			if (ndShReg[0])	begin
-				sumResult <= inReg + sumResult;
-			end	else	begin
-				sumResult <= 0;
-			end
-		end	else	begin
-			sumResult	<=	0;
-		end
-	end
-
-	assign Data_o = sumResult;
-	assign DataValid_o = ndShReg[1];
-
+	
 endmodule

src/src/Sim/DecimFilterWrapperTb.v

@@ -44,14 +44,15 @@ wire	signed	[13:0]	sinAdd	=	(ncoSin1>>>1)+(ncoSin2>>>1);
 // wire	signed	[13:0]	sinAdd	=	ncoSin1;
 
 
-wire	signed	[13:0]	singlePulse	=	(tbCnt==10)?	14'h1fff:14'h0;
+// wire	signed	[13:0]	singlePulse	=	(tbCnt==10)?	14'h1fff:14'h0;
+wire	signed	[13:0]	singlePulse	=	(tbCnt==10)?	14'h1:14'h0;
 // wire	signed	[13:0]	singlePulse	=	(tbCnt>=10&tbCnt<=12)?	14'h1fff:14'h0;
 //==========================================================================================
 //clocks gen
 always	#10 Clk50	=	~Clk50;
 
 //==========================================================================================
-parameter	N	=	2;
+parameter	N	=	3;
 parameter	M	=	1;
 
 always	@(posedge	Clk50)	begin
@@ -227,7 +228,7 @@ reg	[31:0]	testCnt;
 wire	[10:0]	test = N*2+N*2+decimFactor;
 wire	[10:0]	test1 = N*2+N*2+decimFactor-1;
 // wire	writeEn	=	(oscWindDelay[N*2+N*2+decimFactor-2]);
-wire	writeEn	=	(tbCnt>= (startValue+(N*2*2)+decimFactor-6) & tbCnt <= (stopValue+(N*2*2)+decimFactor-6));
+wire	writeEn	=	(tbCnt>= (startValue+(N*2)+1) & tbCnt <= (stopValue+(N*2)+1));
 
 always	@(posedge	Clk50)begin
 	if	(!Rst)	begin

src/src/Sim/FilteredData.txt

@@ -1,5 +1,5 @@
           0
           0
-          0
-          0
-          0
+       4334
+      27027
+       4327

src/src/Sim/ImpResp.m

@@ -5,8 +5,8 @@ R = 2;
 B = 16;
 M = 1;
 
-PointsNum = 500;
-
+PointsNum = 1000;
+Fband = 0:1/PointsNum:1-1/PointsNum;
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
 ReadImpulseRestId = fopen('C:\S5243_FFT_REPO\src\src\Sim\ImpResp.txt','r');
@@ -22,7 +22,7 @@ ImpuseRespFftDb = ImpuseRespFftDb-max(ImpuseRespFftDb);
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
 subplot(2,1,1)
-plot(ImpulseResp)
+plot(Fband,ImpulseResp)
 grid on;
 grid minor;
 title('Cic Frequency response')
@@ -30,7 +30,7 @@ xlabel('f (Hz)')
 ylabel('Amp')
 
 subplot(2,1,2)
-plot(ImpuseRespFftDb)
+plot(Fband,ImpuseRespFftDb)
 grid on;
 grid minor;
 title('Cic Frequency response')

src/src/Sim/ImpResp.txt

@@ -1,6 +1,6 @@
-          0
-          0
-          0
+          1
+          3
+          3
           0
           0
           0

src/src/Sim/main.py

@@ -0,0 +1,54 @@
+N = 1
+R = 2
+M = 1
+Pnum = 10
+
+a = [0] * Pnum
+a[0] = 1
+# a[1] = 1
+
+
+#####
+# integrators
+#####
+intAcc0 = [0] * Pnum
+intAcc1 = [0] * Pnum
+intAcc2 = [0] * Pnum
+
+for i in range(Pnum):
+    intAcc0[i] = intAcc0[i-1] + a[i]
+    intAcc1[i] = intAcc1[i-1] + intAcc0[i]
+    intAcc2[i] = intAcc2[i-1] + intAcc1[i]
+
+#####
+# decimator
+#####
+
+decimSignal = intAcc2[::R]
+decimPnum = int(Pnum/R)
+#####
+# comb sections
+#####
+combSum0 = [0] * decimPnum
+combSum1 = [0] * decimPnum
+combSum2 = [0] * decimPnum
+
+for i in range(decimPnum):
+    if i == 0:
+        combSum0[i] = decimSignal[i] - 0
+        combSum1[i] = combSum0[i] - 0
+        combSum2[i] = combSum1[i] - 0
+    else:
+        combSum0[i] = decimSignal[i] - decimSignal[i-1]
+        combSum1[i] = combSum0[i] - combSum0[i-1]
+        combSum2[i] = combSum1[i] - combSum1[i-1]
+
+
+print(a)
+print(intAcc0)
+print(intAcc1)
+print(intAcc2)
+print(decimSignal)
+print(combSum0)
+print(combSum1)
+print(combSum2)