Инициализация репозитория

.gitignore

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+*cores

script/recreate.tcl

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+#*****************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# recreate.tcl: Tcl script for re-creating project 'S5243_FFT'
+#
+# Generated by Vivado on Wed Dec 13 16:38:43 +0300 2023
+# IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
+#
+# This file contains the Vivado Tcl commands for re-creating the project to the state*
+# when this script was generated. In order to re-create the project, please source this
+# file in the Vivado Tcl Shell.
+#
+# * Note that the runs in the created project will be configured the same way as the
+#   original project, however they will not be launched automatically. To regenerate the
+#   run results please launch the synthesis/implementation runs as needed.
+#
+#*****************************************************************************************
+# NOTE: In order to use this script for source control purposes, please make sure that the
+#       following files are added to the source control system:-
+#
+# 1. This project restoration tcl script (recreate.tcl) that was generated.
+#
+# 2. The following source(s) files that were local or imported into the original project.
+#    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
+#
+#    "D:/S5243_FFT_PROJ/S5243_FFT/S5243_FFT.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo.xci"
+#    "D:/S5243_FFT_PROJ/S5243_FFT/S5243_FFT.srcs/sources_1/ip/MeasDataFifoExtender/MeasDataFifoExtender.xci"
+#
+# 3. The following remote source files that were added to the original project:-
+#
+#    "D:/S5243_FFT_REPO/src/src/PulseMeas/ActivePortSelector.v"
+#    "D:/S5243_FFT_REPO/src/src/InternalDsp/AdcCalibration.v"
+#    "D:/S5243_FFT_REPO/src/src/AdcDataRx/AdcDataInterface.v"
+#    "D:/S5243_FFT_REPO/src/src/AdcDataRx/AdcSync.v"
+#    "D:/S5243_FFT_REPO/src/src/ClkGen/Clk200Gen.v"
+#    "D:/S5243_FFT_REPO/src/src/InternalDsp/ComplPrng.v"
+#    "D:/S5243_FFT_REPO/src/src/InternalDsp/CordicNco.v"
+#    "D:/S5243_FFT_REPO/src/src/InternalDsp/CordicRotation.v"
+#    "D:/S5243_FFT_REPO/src/src/FftDataFiltering/DecimFilterWrapper.v"
+#    "D:/S5243_FFT_REPO/src/src/DitherGen/DitherGenv2.v"
+#    "D:/S5243_FFT_REPO/src/src/ExtDspInterface/DspInterface.v"
+#    "D:/S5243_FFT_REPO/src/src/InternalDsp/DspPipeline.v"
+#    "D:/S5243_FFT_REPO/src/src/ExtDspInterface/DspPpiOut.v"
+#    "D:/S5243_FFT_REPO/src/src/MeasDataFifo/FifoController.v"
+#    "D:/S5243_FFT_REPO/src/src/Math/FpCustomMultiplier.v"
+#    "D:/S5243_FFT_REPO/src/src/GainOverloadControl/GainControl.v"
+#    "D:/S5243_FFT_REPO/src/src/GainOverloadControl/GainControlWrapper.v"
+#    "D:/S5243_FFT_REPO/src/src/InitRst/InitRst.v"
+#    "D:/S5243_FFT_REPO/src/src/InternalDsp/InternalDsp.v"
+#    "D:/S5243_FFT_REPO/src/src/InternalDsp/MeasCtrlModule.v"
+#    "D:/S5243_FFT_REPO/src/src/MeasDataFifo/MeasDataFifoWrapper.v"
+#    "D:/S5243_FFT_REPO/src/src/PulseMeas/MeasStartEventGen.v"
+#    "D:/S5243_FFT_REPO/src/src/Math/MultModule.v"
+#    "D:/S5243_FFT_REPO/src/src/PulseMeas/Mux.v"
+#    "D:/S5243_FFT_REPO/src/src/Math/MyIntToFp.v"
+#    "D:/S5243_FFT_REPO/src/src/InternalDsp/NcoRstGen.v"
+#    "D:/S5243_FFT_REPO/src/src/MeasDataFifo/OscDataFormer.v"
+#    "D:/S5243_FFT_REPO/src/src/GainOverloadControl/OverloadDetect.v"
+#    "D:/S5243_FFT_REPO/src/src/PulseMeas/PGenRstGenerator.v"
+#    "D:/S5243_FFT_REPO/src/src/PulseMeas/PulseGen.v"
+#    "D:/S5243_FFT_REPO/src/src/RegMap/RegMap.v"
+#    "D:/S5243_FFT_REPO/src/src/PulseMeas/SampleStrobeGenRstDemux.v"
+#    "D:/S5243_FFT_REPO/src/src/Math/SimpleMult.v"
+#    "D:/S5243_FFT_REPO/src/src/ExtDspInterface/SlaveSpi.v"
+#    "D:/S5243_FFT_REPO/src/src/PulseMeas/StartAfterGainSel.v"
+#    "D:/S5243_FFT_REPO/src/src/Math/SumAcc.v"
+#    "D:/S5243_FFT_REPO/src/src/PulseMeas/TrigInt2Mux.v"
+#    "D:/S5243_FFT_REPO/src/src/InternalDsp/WinParameters.v"
+#    "D:/S5243_FFT_REPO/src/src/InternalDsp/Win_calc.v"
+#    "D:/S5243_FFT_REPO/src/src/FftDataFiltering/cicFilter.v"
+#    "D:/S5243_FFT_REPO/src/src/FftDataFiltering/combFilterBlock.v"
+#    "D:/S5243_FFT_REPO/src/src/FftDataFiltering/combFilterWrapper.v"
+#    "D:/S5243_FFT_REPO/src/src/FftDataFiltering/decimBlock.v"
+#    "D:/S5243_FFT_REPO/src/src/AdcDataRx/delay_controller_wrap.v"
+#    "D:/S5243_FFT_REPO/src/src/FftDataFiltering/intFilterBlock.v"
+#    "D:/S5243_FFT_REPO/src/src/FftDataFiltering/intFilterWrapper.v"
+#    "D:/S5243_FFT_REPO/src/src/AdcDataRx/n_x_serdes_1_to_7_mmcm_idelay_sdr.v"
+#    "D:/S5243_FFT_REPO/src/src/AdcDataRx/serdes_1_to_7_mmcm_idelay_sdr.v"
+#    "D:/S5243_FFT_REPO/src/src/AdcDataRx/serdes_1_to_7_slave_idelay_sdr.v"
+#    "D:/S5243_FFT_REPO/src/src/AdcDataRx/top5x2_7to1_sdr_rx.v"
+#    "D:/S5243_FFT_REPO/src/src/Top/S5243Top.v"
+#    "D:/S5243_FFT_REPO/src/src/MeasDataFifo/FftDataFormer.v"
+#    "D:/S5243_FFT_REPO/src/src/PulseMeas/PulseGenV2.v"
+#    "D:/S5243_FFT_REPO/src/constrs/S5243Top.xdc"
+#    "D:/S5243_FFT_REPO/src/src/Sim/S5243TopSpectrumTb.v"
+#    "D:/S5243_FFT_REPO/src/src/Sim/S5243TopPulseProfileTb.v"
+#
+#*****************************************************************************************
+
+# Check file required for this script exists
+proc checkRequiredFiles { origin_dir} {
+  set status true
+  foreach ifile $files {
+    if { ![file isfile $ifile] } {
+      puts " Could not find local file $ifile "
+      set status false
+    }
+  }
+
+  set files [list \
+   "D:/S5243_FFT_REPO/src/src/PulseMeas/ActivePortSelector.v" \
+   "D:/S5243_FFT_REPO/src/src/InternalDsp/AdcCalibration.v" \
+   "D:/S5243_FFT_REPO/src/src/AdcDataRx/AdcDataInterface.v" \
+   "D:/S5243_FFT_REPO/src/src/AdcDataRx/AdcSync.v" \
+   "D:/S5243_FFT_REPO/src/src/ClkGen/Clk200Gen.v" \
+   "D:/S5243_FFT_REPO/src/src/InternalDsp/ComplPrng.v" \
+   "D:/S5243_FFT_REPO/src/src/InternalDsp/CordicNco.v" \
+   "D:/S5243_FFT_REPO/src/src/InternalDsp/CordicRotation.v" \
+   "D:/S5243_FFT_REPO/src/src/FftDataFiltering/DecimFilterWrapper.v" \
+   "D:/S5243_FFT_REPO/src/src/DitherGen/DitherGenv2.v" \
+   "D:/S5243_FFT_REPO/src/src/ExtDspInterface/DspInterface.v" \
+   "D:/S5243_FFT_REPO/src/src/InternalDsp/DspPipeline.v" \
+   "D:/S5243_FFT_REPO/src/src/ExtDspInterface/DspPpiOut.v" \
+   "D:/S5243_FFT_REPO/src/src/MeasDataFifo/FifoController.v" \
+   "D:/S5243_FFT_REPO/src/src/Math/FpCustomMultiplier.v" \
+   "D:/S5243_FFT_REPO/src/src/GainOverloadControl/GainControl.v" \
+   "D:/S5243_FFT_REPO/src/src/GainOverloadControl/GainControlWrapper.v" \
+   "D:/S5243_FFT_REPO/src/src/InitRst/InitRst.v" \
+   "D:/S5243_FFT_REPO/src/src/InternalDsp/InternalDsp.v" \
+   "D:/S5243_FFT_REPO/src/src/InternalDsp/MeasCtrlModule.v" \
+   "D:/S5243_FFT_REPO/src/src/MeasDataFifo/MeasDataFifoWrapper.v" \
+   "D:/S5243_FFT_REPO/src/src/PulseMeas/MeasStartEventGen.v" \
+   "D:/S5243_FFT_REPO/src/src/Math/MultModule.v" \
+   "D:/S5243_FFT_REPO/src/src/PulseMeas/Mux.v" \
+   "D:/S5243_FFT_REPO/src/src/Math/MyIntToFp.v" \
+   "D:/S5243_FFT_REPO/src/src/InternalDsp/NcoRstGen.v" \
+   "D:/S5243_FFT_REPO/src/src/MeasDataFifo/OscDataFormer.v" \
+   "D:/S5243_FFT_REPO/src/src/GainOverloadControl/OverloadDetect.v" \
+   "D:/S5243_FFT_REPO/src/src/PulseMeas/PGenRstGenerator.v" \
+   "D:/S5243_FFT_REPO/src/src/PulseMeas/PulseGen.v" \
+   "D:/S5243_FFT_REPO/src/src/RegMap/RegMap.v" \
+   "D:/S5243_FFT_REPO/src/src/PulseMeas/SampleStrobeGenRstDemux.v" \
+   "D:/S5243_FFT_REPO/src/src/Math/SimpleMult.v" \
+   "D:/S5243_FFT_REPO/src/src/ExtDspInterface/SlaveSpi.v" \
+   "D:/S5243_FFT_REPO/src/src/PulseMeas/StartAfterGainSel.v" \
+   "D:/S5243_FFT_REPO/src/src/Math/SumAcc.v" \
+   "D:/S5243_FFT_REPO/src/src/PulseMeas/TrigInt2Mux.v" \
+   "D:/S5243_FFT_REPO/src/src/InternalDsp/WinParameters.v" \
+   "D:/S5243_FFT_REPO/src/src/InternalDsp/Win_calc.v" \
+   "D:/S5243_FFT_REPO/src/src/FftDataFiltering/cicFilter.v" \
+   "D:/S5243_FFT_REPO/src/src/FftDataFiltering/combFilterBlock.v" \
+   "D:/S5243_FFT_REPO/src/src/FftDataFiltering/combFilterWrapper.v" \
+   "D:/S5243_FFT_REPO/src/src/FftDataFiltering/decimBlock.v" \
+   "D:/S5243_FFT_REPO/src/src/AdcDataRx/delay_controller_wrap.v" \
+   "D:/S5243_FFT_REPO/src/src/FftDataFiltering/intFilterBlock.v" \
+   "D:/S5243_FFT_REPO/src/src/FftDataFiltering/intFilterWrapper.v" \
+   "D:/S5243_FFT_REPO/src/src/AdcDataRx/n_x_serdes_1_to_7_mmcm_idelay_sdr.v" \
+   "D:/S5243_FFT_REPO/src/src/AdcDataRx/serdes_1_to_7_mmcm_idelay_sdr.v" \
+   "D:/S5243_FFT_REPO/src/src/AdcDataRx/serdes_1_to_7_slave_idelay_sdr.v" \
+   "D:/S5243_FFT_REPO/src/src/AdcDataRx/top5x2_7to1_sdr_rx.v" \
+   "D:/S5243_FFT_REPO/src/src/Top/S5243Top.v" \
+   "D:/S5243_FFT_REPO/src/src/MeasDataFifo/FftDataFormer.v" \
+   "D:/S5243_FFT_REPO/src/src/PulseMeas/PulseGenV2.v" \
+   "D:/S5243_FFT_REPO/src/constrs/S5243Top.xdc" \
+   "D:/S5243_FFT_REPO/src/src/Sim/S5243TopSpectrumTb.v" \
+   "D:/S5243_FFT_REPO/src/src/Sim/S5243TopPulseProfileTb.v" \
+  ]
+  foreach ifile $files {
+    if { ![file isfile $ifile] } {
+      puts " Could not find remote file $ifile "
+      set status false
+    }
+  }
+
+  return $status
+}
+# Set the reference directory for source file relative paths (by default the value is script directory path)
+set origin_dir "D:/recreate.tcl"
+
+# Use origin directory path location variable, if specified in the tcl shell
+if { [info exists ::origin_dir_loc] } {
+  set origin_dir $::origin_dir_loc
+}
+
+# Set the project name
+set _xil_proj_name_ "S5243_FFT"
+
+# Use project name variable, if specified in the tcl shell
+if { [info exists ::user_project_name] } {
+  set _xil_proj_name_ $::user_project_name
+}
+
+variable script_file
+set script_file "recreate.tcl"
+
+# Help information for this script
+proc print_help {} {
+  variable script_file
+  puts "\nDescription:"
+  puts "Recreate a Vivado project from this script. The created project will be"
+  puts "functionally equivalent to the original project for which this script was"
+  puts "generated. The script contains commands for creating a project, filesets,"
+  puts "runs, adding/importing sources and setting properties on various objects.\n"
+  puts "Syntax:"
+  puts "$script_file"
+  puts "$script_file -tclargs \[--origin_dir <path>\]"
+  puts "$script_file -tclargs \[--project_name <name>\]"
+  puts "$script_file -tclargs \[--help\]\n"
+  puts "Usage:"
+  puts "Name                   Description"
+  puts "-------------------------------------------------------------------------"
+  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
+  puts "                       origin_dir path value is \".\", otherwise, the value"
+  puts "                       that was set with the \"-paths_relative_to\" switch"
+  puts "                       when this script was generated.\n"
+  puts "\[--project_name <name>\] Create project with the specified name. Default"
+  puts "                       name is the name of the project from where this"
+  puts "                       script was generated.\n"
+  puts "\[--help\]               Print help information for this script"
+  puts "-------------------------------------------------------------------------\n"
+  exit 0
+}
+
+if { $::argc > 0 } {
+  for {set i 0} {$i < $::argc} {incr i} {
+    set option [string trim [lindex $::argv $i]]
+    switch -regexp -- $option {
+      "--origin_dir"   { incr i; set origin_dir [lindex $::argv $i] }
+      "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
+      "--help"         { print_help }
+      default {
+        if { [regexp {^-} $option] } {
+          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
+          return 1
+        }
+      }
+    }
+  }
+}
+
+# Set the directory path for the original project from where this script was exported
+set orig_proj_dir "[file normalize "$origin_dir/"]"
+
+# Check for paths and files needed for project creation
+set validate_required 0
+if { $validate_required } {
+  if { [checkRequiredFiles $origin_dir] } {
+    puts "Tcl file $script_file is valid. All files required for project creation is accesable. "
+  } else {
+    puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. "
+    return
+  }
+}
+
+# Create project
+create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7s25csga324-2
+
+# Set the directory path for the new project
+set proj_dir [get_property directory [current_project]]
+
+# Set project properties
+set obj [current_project]
+set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
+set_property -name "enable_vhdl_2008" -value "1" -objects $obj
+set_property -name "ip_cache_permissions" -value "read write" -objects $obj
+set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
+set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
+set_property -name "part" -value "xc7s25csga324-2" -objects $obj
+set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
+set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
+set_property -name "simulator_language" -value "Mixed" -objects $obj
+set_property -name "webtalk.activehdl_export_sim" -value "2" -objects $obj
+set_property -name "webtalk.ies_export_sim" -value "2" -objects $obj
+set_property -name "webtalk.modelsim_export_sim" -value "2" -objects $obj
+set_property -name "webtalk.questa_export_sim" -value "2" -objects $obj
+set_property -name "webtalk.riviera_export_sim" -value "2" -objects $obj
+set_property -name "webtalk.vcs_export_sim" -value "2" -objects $obj
+set_property -name "webtalk.xsim_export_sim" -value "2" -objects $obj
+set_property -name "webtalk.xsim_launch_sim" -value "32" -objects $obj
+set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
+
+# Create 'sources_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sources_1] ""]} {
+  create_fileset -srcset sources_1
+}
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+set files [list \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/PulseMeas/ActivePortSelector.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/InternalDsp/AdcCalibration.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/AdcDataRx/AdcDataInterface.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/AdcDataRx/AdcSync.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/ClkGen/Clk200Gen.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/InternalDsp/ComplPrng.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/InternalDsp/CordicNco.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/InternalDsp/CordicRotation.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/FftDataFiltering/DecimFilterWrapper.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/DitherGen/DitherGenv2.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/ExtDspInterface/DspInterface.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/InternalDsp/DspPipeline.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/ExtDspInterface/DspPpiOut.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/MeasDataFifo/FifoController.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/Math/FpCustomMultiplier.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/GainOverloadControl/GainControl.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/GainOverloadControl/GainControlWrapper.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/InitRst/InitRst.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/InternalDsp/InternalDsp.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/InternalDsp/MeasCtrlModule.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/MeasDataFifo/MeasDataFifoWrapper.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/PulseMeas/MeasStartEventGen.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/Math/MultModule.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/PulseMeas/Mux.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/Math/MyIntToFp.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/InternalDsp/NcoRstGen.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/MeasDataFifo/OscDataFormer.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/GainOverloadControl/OverloadDetect.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/PulseMeas/PGenRstGenerator.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/PulseMeas/PulseGen.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/RegMap/RegMap.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/PulseMeas/SampleStrobeGenRstDemux.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/Math/SimpleMult.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/ExtDspInterface/SlaveSpi.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/PulseMeas/StartAfterGainSel.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/Math/SumAcc.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/PulseMeas/TrigInt2Mux.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/InternalDsp/WinParameters.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/InternalDsp/Win_calc.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/FftDataFiltering/cicFilter.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/FftDataFiltering/combFilterBlock.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/FftDataFiltering/combFilterWrapper.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/FftDataFiltering/decimBlock.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/AdcDataRx/delay_controller_wrap.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/FftDataFiltering/intFilterBlock.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/FftDataFiltering/intFilterWrapper.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/AdcDataRx/n_x_serdes_1_to_7_mmcm_idelay_sdr.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/AdcDataRx/serdes_1_to_7_mmcm_idelay_sdr.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/AdcDataRx/serdes_1_to_7_slave_idelay_sdr.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/AdcDataRx/top5x2_7to1_sdr_rx.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/Top/S5243Top.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/MeasDataFifo/FftDataFormer.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/PulseMeas/PulseGenV2.v"] \
+]
+add_files -norecurse -fileset $obj $files
+
+# Set 'sources_1' fileset file properties for remote files
+# None
+
+# Set 'sources_1' fileset file properties for local files
+# None
+
+# Set 'sources_1' fileset properties
+set obj [get_filesets sources_1]
+set_property -name "top" -value "S5243Top" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+# Create 'constrs_1' fileset (if not found)
+if {[string equal [get_filesets -quiet constrs_1] ""]} {
+  create_fileset -constrset constrs_1
+}
+
+# Set 'constrs_1' fileset object
+set obj [get_filesets constrs_1]
+
+# Add/Import constrs file and set constrs file properties
+set file "[file normalize "$origin_dir/../../S5243_FFT_REPO/src/constrs/S5243Top.xdc"]"
+set file_added [add_files -norecurse -fileset $obj [list $file]]
+set file "$origin_dir/../../S5243_FFT_REPO/src/constrs/S5243Top.xdc"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
+set_property -name "file_type" -value "XDC" -objects $file_obj
+
+# Set 'constrs_1' fileset properties
+set obj [get_filesets constrs_1]
+set_property -name "target_part" -value "xc7s25csga324-2" -objects $obj
+
+# Create 'sim_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sim_1] ""]} {
+  create_fileset -simset sim_1
+}
+
+# Set 'sim_1' fileset object
+set obj [get_filesets sim_1]
+set files [list \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/Sim/S5243TopSpectrumTb.v"] \
+ [file normalize "${origin_dir}/../../S5243_FFT_REPO/src/src/Sim/S5243TopPulseProfileTb.v"] \
+]
+add_files -norecurse -fileset $obj $files
+
+# Set 'sim_1' fileset file properties for remote files
+# None
+
+# Set 'sim_1' fileset file properties for local files
+# None
+
+# Set 'sim_1' fileset properties
+set obj [get_filesets sim_1]
+set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
+set_property -name "top" -value "S5243TopSpectrumTb" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
+
+# Set 'utils_1' fileset object
+set obj [get_filesets utils_1]
+# Empty (no sources present)
+
+# Set 'utils_1' fileset properties
+set obj [get_filesets utils_1]
+
+# Create 'synth_1' run (if not found)
+if {[string equal [get_runs -quiet synth_1] ""]} {
+    create_run -name synth_1 -part xc7s25csga324-2 -flow {Vivado Synthesis 2020} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
+} else {
+  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
+  set_property flow "Vivado Synthesis 2020" [get_runs synth_1]
+}
+set obj [get_runs synth_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Synthesis Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'synth_1_synth_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
+  create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
+}
+set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
+if { $obj != "" } {
+
+}
+set obj [get_runs synth_1]
+set_property -name "needs_refresh" -value "1" -objects $obj
+set_property -name "part" -value "xc7s25csga324-2" -objects $obj
+set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
+
+# set the current synth run
+current_run -synthesis [get_runs synth_1]
+
+# Create 'impl_1' run (if not found)
+if {[string equal [get_runs -quiet impl_1] ""]} {
+    create_run -name impl_1 -part xc7s25csga324-2 -flow {Vivado Implementation 2020} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
+} else {
+  set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
+  set_property flow "Vivado Implementation 2020" [get_runs impl_1]
+}
+set obj [get_runs impl_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Implementation Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'impl_1_init_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_opt_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_place_report_io_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_control_sets_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
+if { $obj != "" } {
+set_property -name "options.verbose" -value "1" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_methodology_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_power_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_route_status_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+set obj [get_runs impl_1]
+set_property -name "needs_refresh" -value "1" -objects $obj
+set_property -name "part" -value "xc7s25csga324-2" -objects $obj
+set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
+set_property -name "steps.write_bitstream.args.bin_file" -value "1" -objects $obj
+set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
+
+# set the current impl run
+current_run -implementation [get_runs impl_1]
+
+puts "INFO: Project created:${_xil_proj_name_}"
+# Create 'drc_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "drc_1" ] ] ""]} {
+create_dashboard_gadget -name {drc_1} -type drc
+}
+set obj [get_dashboard_gadgets [ list "drc_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
+
+# Create 'methodology_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "methodology_1" ] ] ""]} {
+create_dashboard_gadget -name {methodology_1} -type methodology
+}
+set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
+
+# Create 'power_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "power_1" ] ] ""]} {
+create_dashboard_gadget -name {power_1} -type power
+}
+set obj [get_dashboard_gadgets [ list "power_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
+
+# Create 'timing_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "timing_1" ] ] ""]} {
+create_dashboard_gadget -name {timing_1} -type timing
+}
+set obj [get_dashboard_gadgets [ list "timing_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
+
+# Create 'utilization_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_1" ] ] ""]} {
+create_dashboard_gadget -name {utilization_1} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
+set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
+set_property -name "run.step" -value "synth_design" -objects $obj
+set_property -name "run.type" -value "synthesis" -objects $obj
+
+# Create 'utilization_2' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_2" ] ] ""]} {
+create_dashboard_gadget -name {utilization_2} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
+set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
+
+move_dashboard_gadget -name {utilization_1} -row 0 -col 0
+move_dashboard_gadget -name {power_1} -row 1 -col 0
+move_dashboard_gadget -name {drc_1} -row 2 -col 0
+move_dashboard_gadget -name {timing_1} -row 0 -col 1
+move_dashboard_gadget -name {utilization_2} -row 1 -col 1
+move_dashboard_gadget -name {methodology_1} -row 2 -col 1
+
+##################################################################
+# CHECK VIVADO VERSION
+##################################################################
+
+set scripts_vivado_version 2020.2
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+  catch {common::send_msg_id "IPS_TCL-100" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_ip_tcl to create an updated script."}
+  return 1
+}
+
+##################################################################
+# START
+##################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source recreateIp.tcl
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./S5243_FFT/S5243_FFT.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+  create_project S5243_FFT S5243_FFT -part xc7s25csga324-2
+  set_property target_language Verilog [current_project]
+  set_property simulator_language Mixed [current_project]
+}
+
+##################################################################
+# CHECK IPs
+##################################################################
+
+set bCheckIPs 1
+set bCheckIPsPassed 1
+if { $bCheckIPs == 1 } {
+  set list_check_ips { xilinx.com:ip:fifo_generator:13.2 }
+  set list_ips_missing ""
+  common::send_msg_id "IPS_TCL-1001" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+  foreach ip_vlnv $list_check_ips {
+  set ip_obj [get_ipdefs -all $ip_vlnv]
+  if { $ip_obj eq "" } {
+    lappend list_ips_missing $ip_vlnv
+    }
+  }
+
+  if { $list_ips_missing ne "" } {
+    catch {common::send_msg_id "IPS_TCL-105" "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+    set bCheckIPsPassed 0
+  }
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_msg_id "IPS_TCL-102" "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 1
+}
+
+##################################################################
+# CREATE IP MeasDataFifo
+##################################################################
+
+set MeasDataFifo [create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name MeasDataFifo]
+
+set_property -dict { 
+  CONFIG.Input_Data_Width {256}
+  CONFIG.Input_Depth {4096}
+  CONFIG.Output_Data_Width {256}
+  CONFIG.Output_Depth {4096}
+  CONFIG.Data_Count_Width {12}
+  CONFIG.Write_Data_Count_Width {12}
+  CONFIG.Read_Data_Count_Width {12}
+  CONFIG.Full_Threshold_Assert_Value {4094}
+  CONFIG.Full_Threshold_Negate_Value {4093}
+} [get_ips MeasDataFifo]
+
+set_property -dict { 
+  GENERATE_SYNTH_CHECKPOINT {1}
+} $MeasDataFifo
+
+##################################################################
+
+##################################################################
+# CREATE IP MeasDataFifoExtender
+##################################################################
+
+set MeasDataFifoExtender [create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name MeasDataFifoExtender]
+
+set_property -dict { 
+  CONFIG.Performance_Options {First_Word_Fall_Through}
+  CONFIG.Input_Data_Width {256}
+  CONFIG.Input_Depth {32}
+  CONFIG.Output_Data_Width {256}
+  CONFIG.Output_Depth {32}
+  CONFIG.Use_Extra_Logic {true}
+  CONFIG.Data_Count_Width {6}
+  CONFIG.Write_Data_Count_Width {6}
+  CONFIG.Read_Data_Count_Width {6}
+  CONFIG.Full_Threshold_Assert_Value {31}
+  CONFIG.Full_Threshold_Negate_Value {30}
+  CONFIG.Empty_Threshold_Assert_Value {4}
+  CONFIG.Empty_Threshold_Negate_Value {5}
+} [get_ips MeasDataFifoExtender]
+
+set_property -dict { 
+  GENERATE_SYNTH_CHECKPOINT {1}
+} $MeasDataFifoExtender
+
+##################################################################
+

src/constrs/S5243Top.xdc

@@ -0,0 +1,279 @@
+# set_property PACKAGE_PIN U17 [get_ports Adc1DataDa0P_i]
+# set_property PACKAGE_PIN R18 [get_ports Adc1DataDa1P_i]
+# set_property PACKAGE_PIN M18 [get_ports Adc1DataDb0P_i]
+# set_property PACKAGE_PIN L17 [get_ports Adc1DataDb1P_i]
+
+# set_property PACKAGE_PIN H18 [get_ports Adc2DataDa0P_i]
+# set_property PACKAGE_PIN F18 [get_ports Adc2DataDa1P_i]
+# set_property PACKAGE_PIN C17 [get_ports Adc2DataDb0P_i]
+# set_property PACKAGE_PIN B17 [get_ports Adc2DataDb1P_i]
+
+
+set_property PACKAGE_PIN H18 [get_ports Adc1DataDa0P_i]
+set_property PACKAGE_PIN F18 [get_ports Adc1DataDa1P_i]
+set_property PACKAGE_PIN C17 [get_ports Adc1DataDb0P_i]
+set_property PACKAGE_PIN B17 [get_ports Adc1DataDb1P_i]
+
+set_property PACKAGE_PIN U17 [get_ports Adc2DataDa0P_i]
+set_property PACKAGE_PIN R18 [get_ports Adc2DataDa1P_i]
+set_property PACKAGE_PIN M18 [get_ports Adc2DataDb0P_i]
+set_property PACKAGE_PIN L17 [get_ports Adc2DataDb1P_i]
+
+#==========================================================================
+#   TIMING CONSTRAINTS
+
+
+#==========================================================================
+#	INPUT CLOCKS
+set_property PACKAGE_PIN P2 [get_ports ClkP_i]
+set_property IOSTANDARD LVDS_25 [get_ports ClkP_i]
+set_property IOSTANDARD LVDS_25 [get_ports ClkN_i]
+
+create_clock -period 20.000 [get_ports ClkP_i]
+
+#==========================================================================
+#	ADC1
+
+set_property PACKAGE_PIN D18 [get_ports Adc1FclkP_i]
+set_property IOSTANDARD LVDS_25 [get_ports Adc1FclkP_i]
+set_property IOSTANDARD LVDS_25 [get_ports Adc1FclkN_i]
+
+set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDa0P_i]
+set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDa0N_i]
+
+set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDa1P_i]
+set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDa1N_i]
+
+set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDb0P_i]
+set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDb0N_i]
+
+set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDb1P_i]
+set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDb1N_i]
+
+#==========================================================================
+#	ADC2
+
+set_property PACKAGE_PIN R16 [get_ports Adc2FclkP_i]
+set_property IOSTANDARD LVDS_25 [get_ports Adc2FclkP_i]
+set_property IOSTANDARD LVDS_25 [get_ports Adc2FclkN_i]
+
+set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDa0P_i]
+set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDa0N_i]
+
+set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDa1P_i]
+set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDa1N_i]
+
+set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDb0P_i]
+set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDb0N_i]
+
+set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDb1P_i]
+set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDb1N_i]
+
+#==========================================================================
+# DSP interface
+
+set_property PACKAGE_PIN K17 [get_ports Miso_o]
+set_property IOSTANDARD LVCMOS25 [get_ports Miso_o]
+
+set_property PACKAGE_PIN K18 [get_ports Mosi_i]
+set_property IOSTANDARD LVCMOS25 [get_ports Mosi_i]
+
+set_property PACKAGE_PIN V12 [get_ports Ss_i]
+set_property IOSTANDARD LVCMOS25 [get_ports Ss_i]
+
+set_property PACKAGE_PIN T14 [get_ports Sck_i]
+set_property IOSTANDARD LVCMOS25 [get_ports Sck_i]
+#create_clock -period 24.000 [get_ports Sck_i]
+create_clock -period 16.000 [get_ports Sck_i]
+
+set_property PACKAGE_PIN R1 [get_ports LpOutClk_o]
+set_property IOSTANDARD LVCMOS33 [get_ports LpOutClk_o]
+
+set_property PACKAGE_PIN N1 [get_ports LpOutFs_o]
+set_property IOSTANDARD LVCMOS33 [get_ports LpOutFs_o]
+
+set_property PACKAGE_PIN V7 [get_ports {LpOutData_o[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[0]}]
+set_property PACKAGE_PIN U7 [get_ports {LpOutData_o[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[1]}]
+set_property PACKAGE_PIN V6 [get_ports {LpOutData_o[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[2]}]
+set_property PACKAGE_PIN U6 [get_ports {LpOutData_o[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[3]}]
+set_property PACKAGE_PIN V5 [get_ports {LpOutData_o[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[4]}]
+set_property PACKAGE_PIN T5 [get_ports {LpOutData_o[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[5]}]
+set_property PACKAGE_PIN T4 [get_ports {LpOutData_o[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[6]}]
+set_property PACKAGE_PIN V4 [get_ports {LpOutData_o[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[7]}]
+set_property PACKAGE_PIN U3 [get_ports {LpOutData_o[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[8]}]
+set_property PACKAGE_PIN V3 [get_ports {LpOutData_o[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[9]}]
+set_property PACKAGE_PIN U2 [get_ports {LpOutData_o[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[10]}]
+set_property PACKAGE_PIN V2 [get_ports {LpOutData_o[11]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[11]}]
+set_property PACKAGE_PIN T2 [get_ports {LpOutData_o[12]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[12]}]
+set_property PACKAGE_PIN U1 [get_ports {LpOutData_o[13]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[13]}]
+set_property PACKAGE_PIN R2 [get_ports {LpOutData_o[14]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[14]}]
+set_property PACKAGE_PIN T1 [get_ports {LpOutData_o[15]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[15]}]
+
+#==========================================================================
+#  ADC SPI
+
+set_property PACKAGE_PIN E15 [get_ports Adc1InitMosi_o]
+set_property IOSTANDARD LVCMOS25 [get_ports Adc1InitMosi_o]
+set_property PACKAGE_PIN N15 [get_ports Adc2InitMosi_o]
+set_property IOSTANDARD LVCMOS25 [get_ports Adc2InitMosi_o]
+
+set_property PACKAGE_PIN F15 [get_ports Adc1InitClk_o]
+set_property IOSTANDARD LVCMOS25 [get_ports Adc1InitClk_o]
+set_property PACKAGE_PIN P16 [get_ports Adc2InitClk_o]
+set_property IOSTANDARD LVCMOS25 [get_ports Adc2InitClk_o]
+
+set_property PACKAGE_PIN G15 [get_ports Adc1InitCs_o]
+set_property IOSTANDARD LVCMOS25 [get_ports Adc1InitCs_o]
+set_property PACKAGE_PIN P15 [get_ports Adc2InitCs_o]
+set_property IOSTANDARD LVCMOS25 [get_ports Adc2InitCs_o]
+
+set_property PACKAGE_PIN H15 [get_ports Adc1InitRst_o]
+set_property IOSTANDARD LVCMOS25 [get_ports Adc1InitRst_o]
+set_property PACKAGE_PIN R15 [get_ports Adc2InitRst_o]
+set_property IOSTANDARD LVCMOS25 [get_ports Adc2InitRst_o]
+#
+#==========================================================================
+#  OTHER
+
+set_property PACKAGE_PIN J6 [get_ports Led_o]
+set_property IOSTANDARD LVCMOS33 [get_ports Led_o]
+
+set_property PACKAGE_PIN R4 [get_ports Overload_o]
+set_property IOSTANDARD LVCMOS33 [get_ports Overload_o]
+
+#set_property PACKAGE_PIN R8 [get_ports OverloadS_i]		;#NC
+#set_property IOSTANDARD LVCMOS33 [get_ports OverloadS_i]
+
+set_property PACKAGE_PIN T3 [get_ports StartMeas_i]
+set_property IOSTANDARD LVCMOS33 [get_ports StartMeas_i]
+
+set_property PACKAGE_PIN N3 [get_ports EndMeas_o]
+set_property IOSTANDARD LVCMOS33 [get_ports EndMeas_o]
+
+#set_property PACKAGE_PIN T3 [get_ports StartMeas_o]		;#NC
+#set_property IOSTANDARD LVCMOS33 [get_ports StartMeas_o]
+
+set_property PACKAGE_PIN R3 [get_ports TimersClk_o]
+set_property IOSTANDARD LVCMOS33 [get_ports TimersClk_o]
+
+# set_property PACKAGE_PIN V14 [get_ports {AmpEn_o[0]}]
+# set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[0]}]
+# set_property PACKAGE_PIN H17 [get_ports {AmpEn_o[1]}]
+# set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[1]}]
+# set_property PACKAGE_PIN V16 [get_ports {AmpEn_o[2]}]
+# set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[2]}]
+# set_property PACKAGE_PIN B16 [get_ports {AmpEn_o[3]}]
+# set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[3]}]
+
+
+set_property PACKAGE_PIN H17 [get_ports {AmpEn_o[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[0]}]
+
+set_property PACKAGE_PIN B16 [get_ports {AmpEn_o[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[1]}]
+
+set_property PACKAGE_PIN V16 [get_ports {AmpEn_o[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[2]}]
+
+set_property PACKAGE_PIN V14 [get_ports {AmpEn_o[3]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[3]}]
+
+
+
+set_property PACKAGE_PIN K3 [get_ports {PortSel_o[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PortSel_o[0]}]
+set_property PACKAGE_PIN K4 [get_ports {PortSel_o[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PortSel_o[1]}]
+#set_property PACKAGE_PIN R3 [get_ports {PortSel_o[2]}]		;#NC
+#set_property IOSTANDARD LVCMOS25 [get_ports {PortSel_o[2]}]
+#set_property PACKAGE_PIN P3 [get_ports {PortSel_o[3]}]		;#NC
+#set_property IOSTANDARD LVCMOS25 [get_ports {PortSel_o[3]}]
+
+#set_property PACKAGE_PIN F14 [get_ports {PortSelDir_o[0]}]		;#NC BUFF_DIR
+#set_property IOSTANDARD LVCMOS25 [get_ports {PortSelDir_o[0]}]
+#set_property PACKAGE_PIN F15 [get_ports {PortSelDir_o[1]}]		;#NC
+#set_property IOSTANDARD LVCMOS25 [get_ports {PortSelDir_o[1]}]
+#set_property PACKAGE_PIN R4 [get_ports {PortSelDir_o[2]}]		;#NC
+#set_property IOSTANDARD LVCMOS25 [get_ports {PortSelDir_o[2]}]
+#set_property PACKAGE_PIN M4 [get_ports {PortSelDir_o[3]}]		;#NC
+#set_property IOSTANDARD LVCMOS25 [get_ports {PortSelDir_o[3]}]
+
+#set_property PACKAGE_PIN R7 [get_ports SensEnM_io]			;#NC
+#set_property IOSTANDARD LVCMOS33 [get_ports SensEnM_io]
+
+#set_property PACKAGE_PIN T3 [get_ports StartMeasDsp_o]		;#NC
+#set_property IOSTANDARD LVCMOS33 [get_ports StartMeasDsp_o]
+
+set_property PACKAGE_PIN K2 [get_ports Mod_o]
+set_property IOSTANDARD LVCMOS33 [get_ports Mod_o]
+
+
+set_property PACKAGE_PIN N2 [get_ports DspTrigOut_i]
+set_property IOSTANDARD LVCMOS33 [get_ports DspTrigOut_i]
+set_property PACKAGE_PIN M2 [get_ports DspTrigIn_o]
+set_property IOSTANDARD LVCMOS33 [get_ports DspTrigIn_o]
+
+set_property PACKAGE_PIN L4 [get_ports {Trig6to1_io[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Trig6to1_io[0]}]
+set_property PACKAGE_PIN K1 [get_ports {Trig6to1_io[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Trig6to1_io[1]}]
+set_property PACKAGE_PIN B13 [get_ports {Trig6to1_io[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1_io[2]}]
+set_property PACKAGE_PIN A13 [get_ports {Trig6to1_io[3]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1_io[3]}]
+set_property PACKAGE_PIN B14 [get_ports {Trig6to1_io[4]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1_io[4]}]
+set_property PACKAGE_PIN A14 [get_ports {Trig6to1_io[5]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1_io[5]}]
+
+set_property PACKAGE_PIN N5 [get_ports {Trig6to1Dir_o[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Trig6to1Dir_o[0]}]
+set_property PACKAGE_PIN M5 [get_ports {Trig6to1Dir_o[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Trig6to1Dir_o[1]}]
+set_property PACKAGE_PIN D12 [get_ports {Trig6to1Dir_o[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1Dir_o[2]}]
+set_property PACKAGE_PIN E12 [get_ports {Trig6to1Dir_o[3]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1Dir_o[3]}]
+set_property PACKAGE_PIN B15 [get_ports {Trig6to1Dir_o[4]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1Dir_o[4]}]
+set_property PACKAGE_PIN A15 [get_ports {Trig6to1Dir_o[5]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1Dir_o[5]}]
+
+set_property PACKAGE_PIN A16 [get_ports DitherCtrlCh1_o]
+set_property IOSTANDARD LVCMOS25 [get_ports DitherCtrlCh1_o]
+
+set_property PACKAGE_PIN V15 [get_ports DitherCtrlCh2_o]
+set_property IOSTANDARD LVCMOS25 [get_ports DitherCtrlCh2_o]
+
+set_property PACKAGE_PIN M1 [get_ports DspReadyForRx_i]
+set_property IOSTANDARD LVCMOS33 [get_ports DspReadyForRx_i]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Ss_i_IBUF]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Sck_i_IBUF]
+
+
+set_false_path -from [get_clocks -of_objects [get_pins Clk200Gen/rx_plle2_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins Clk200Gen/rx_plle2_adv_inst/CLKOUT0]]
+
+
+
+
+
+
+
+

src/src/AdcDataRx/AdcDataInterface.v

@@ -0,0 +1,208 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// company: 
+// engineer: 
+// 
+// create date:    11:47:44 07/11/2019 
+// design name: 
+// module name:    adc_data_interface 
+// project name: 
+// target devices: 
+// tool versions: 
+// description: 
+//
+// dependencies: 
+//
+// revision: 
+// revision 0.01 - file created
+// additional comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	AdcDataInterface	
+#(	
+	parameter	AdcDataWidth	=	14,
+	parameter	ChNum			=	4,
+	parameter	Ratio			=	8
+)
+(
+	input	Clk_i,
+	input	RefClk_i,
+	input	Locked_i,
+	input	Rst_i,
+	
+	input	[AdcDataWidth-1:0]	testAdc,
+		
+	input	Adc1FclkP_i,		
+    input	Adc1FclkN_i,		
+	
+    input	Adc1DataDa0P_i,
+	input	Adc1DataDa0N_i,
+    input	Adc1DataDa1P_i,
+    input	Adc1DataDa1N_i,
+	
+	input	Adc1DataDb0P_i,
+    input	Adc1DataDb0N_i,
+    input	Adc1DataDb1P_i,
+    input	Adc1DataDb1N_i,
+		
+	input	Adc2FclkP_i,		
+    input	Adc2FclkN_i,		
+	
+	input	Adc2DataDa0P_i,
+    input	Adc2DataDa0N_i,
+    input	Adc2DataDa1P_i,
+    input	Adc2DataDa1N_i,
+	
+	input	Adc2DataDb0P_i,
+    input	Adc2DataDb0N_i,
+    input	Adc2DataDb1P_i,
+    input	Adc2DataDb1N_i,
+	
+	output	[AdcDataWidth-1:0]	Adc1ChT1Data_o,
+	output	[AdcDataWidth-1:0]	Adc1ChR1Data_o,
+	output	[AdcDataWidth-1:0]	Adc2ChR2Data_o,
+	output	[AdcDataWidth-1:0]	Adc2ChT2Data_o
+);
+//================================================================================
+//  reg/wire
+//================================================================================	
+	wire    [ChNum-1:0]    	adc1P;
+    wire    [ChNum-1:0]    	adc1N;
+    wire    [ChNum-1:0]    	adc2P;
+    wire    [ChNum-1:0]    	adc2N;
+	
+	reg	[AdcDataWidth*2-1:0]	adc1DataSyncPipe	[2:0];
+	reg	[AdcDataWidth*2-1:0]	adc2DataSyncPipe	[2:0];
+
+	wire	[(ChNum-2)*AdcDataWidth-1:0]	adc1Dout;
+	wire	[(ChNum-2)*AdcDataWidth-1:0]	adc2Dout;
+	
+	wire	[AdcDataWidth-1:0]	adc1ChAData;
+	wire	[AdcDataWidth-1:0]	adc1ChBData;
+	wire	[AdcDataWidth-1:0]	adc2ChAData;
+	wire	[AdcDataWidth-1:0]	adc2ChBData;	
+	
+	reg		[AdcDataWidth-1:0]	adc1ChT1DataSyncR;	
+	reg		[AdcDataWidth-1:0]	adc1ChR1DataSyncR;
+	reg		[AdcDataWidth-1:0]	adc2ChT2DataSyncR;
+	reg		[AdcDataWidth-1:0]	adc2ChR2DataSyncR;
+	
+	wire	[AdcDataWidth-1:0]	adc1ChT1DataSync;	
+	wire	[AdcDataWidth-1:0]	adc1ChR1DataSync;
+	wire	[AdcDataWidth-1:0]	adc2ChT2DataSync;
+	wire	[AdcDataWidth-1:0]	adc2ChR2DataSync;
+	
+	assign  adc1P	= {Adc1DataDb1P_i, Adc1DataDb0P_i, Adc1DataDa1P_i, Adc1DataDa0P_i};
+	assign  adc1N	= {Adc1DataDb1N_i, Adc1DataDb0N_i, Adc1DataDa1N_i, Adc1DataDa0N_i};
+	
+	assign  adc2P	= {Adc2DataDb1P_i, Adc2DataDb0P_i, Adc2DataDa1P_i, Adc2DataDa0P_i};
+	assign  adc2N	= {Adc2DataDb1N_i, Adc2DataDb0N_i, Adc2DataDa1N_i, Adc2DataDa0N_i};
+	
+	// assign	Adc1ChT1Data_o	=	adc1DataSyncPipe[2][AdcDataWidth*2-1-:14];
+	// assign	Adc1ChR1Data_o	=	adc1DataSyncPipe[2][AdcDataWidth-1-:14];
+	// assign	Adc2ChR2Data_o	=	adc2DataSyncPipe[2][AdcDataWidth*2-1-:14];
+	// assign	Adc2ChT2Data_o	=	adc2DataSyncPipe[2][AdcDataWidth-1-:14];
+	
+	assign	Adc1ChT1Data_o	=	adc1ChT1DataSync;
+	assign	Adc1ChR1Data_o	=	adc1ChR1DataSync;
+	assign	Adc2ChR2Data_o	=	adc2ChR2DataSync;
+	assign	Adc2ChT2Data_o	=	adc2ChT2DataSync;
+	
+	wire	idly_reset_int;
+	wire	rx_reset;
+	wire	rx2_cmt_locked;
+	wire	Adc1RxClk;
+	wire	Adc2RxClk;
+	
+//================================================================================
+//  instantiations
+//================================================================================
+
+top5x2_7to1_sdr_rx	Adc1Rx
+(                  
+	.reset		(Rst_i),
+	.refclkin	(RefClk_i),
+	.Locked_i	(Locked_i),
+	.clkin1_p	(Adc1FclkP_i),
+	.clkin1_n	(Adc1FclkN_i),	
+	.datain1_p	(adc1P),	
+	.datain1_n	(adc1N),	
+	.clkin2_p	(),	
+	.clkin2_n	(),	
+	.datain2_p	(),	
+	.datain2_n	(),	
+	.dummy		(),
+	.dout		(adc1Dout),
+	.DivClk_o	(Adc1RxClk)
+);
+
+top5x2_7to1_sdr_rx	Adc2Rx
+(                  
+	.reset		(Rst_i),
+	.refclkin	(RefClk_i),
+	.Locked_i	(Locked_i),
+	.clkin1_p	(Adc2FclkP_i),
+	.clkin1_n	(Adc2FclkN_i),	
+	.datain1_p	(adc2P),	
+	.datain1_n	(adc2N),	
+	.clkin2_p	(),	
+	.clkin2_n	(),	
+	.datain2_p	(),	
+	.datain2_n	(),	
+	.dummy		(),
+	.dout		(adc2Dout),
+	.DivClk_o	(Adc2RxClk)
+);
+
+
+AdcSync Adc1Sync
+(
+    .Clk_i	(Clk_i),
+	.Rst_i	(Rst_i),
+	
+    .Data_i	(adc1Dout),
+	
+	.Data_o	({adc1ChT1DataSync, adc1ChR1DataSync})
+);
+
+AdcSync Adc2Sync
+(
+    .Clk_i	(Clk_i),
+	.Rst_i	(Rst_i),
+	
+    .Data_i	(adc2Dout),
+	
+	.Data_o	({adc2ChR2DataSync, adc2ChT2DataSync})
+);
+
+// AdcSyncFifo	adc1SyncFifo	(
+	// .rst		(Rst_i),
+	// .wr_clk		(Adc1RxClk),	
+	// .rd_clk		(Clk_i),
+	// .din		(adc1Dout),
+	// .din		({testAdc,testAdc}),
+	// .wr_en		(1'b1),
+	// .rd_en		(1'b1),
+	// .dout		({adc1ChT1DataSync, adc1ChR1DataSync}),
+	// .full		(),
+	// .empty		()
+// );
+
+// AdcSyncFifo	adc2SyncFifo	(
+	// .rst		(Rst_i),
+	// .wr_clk		(Adc2RxClk),	
+	// .rd_clk		(Clk_i),
+	// .din		(adc2Dout),
+	// .wr_en		(1'b1),
+	// .rd_en		(1'b1),
+	// .dout		({adc2ChR2DataSync, adc2ChT2DataSync}),
+	// .full		(),
+	// .empty		()
+// );
+endmodule
+
+
+
+
+
+

src/src/AdcDataRx/AdcSync.v

@@ -0,0 +1,41 @@
+module AdcSync 
+#(	
+	parameter	AdcDataWidth	=	14
+)
+(
+    input	Clk_i,
+	input	Rst_i,
+	
+    input	[AdcDataWidth*2-1:0]	Data_i,
+	
+	output	[AdcDataWidth*2-1:0]	Data_o
+);
+
+//================================================================================
+//  REG/WIRE
+//================================================================================
+
+	reg	[AdcDataWidth*2-1:0]	adcDataSyncPipe	[2:0];
+	integer i;
+
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+	assign	Data_o	=	adcDataSyncPipe[2];
+//================================================================================
+//  CODING
+//================================================================================
+
+
+always @(posedge Clk_i) begin
+	if	(!Rst_i)	begin
+		adcDataSyncPipe[0]  <= Data_i;
+		for(i=1; i<3; i=i+1) begin
+			adcDataSyncPipe	[i]<=adcDataSyncPipe[i-1];
+		end
+	end	else	begin
+		adcDataSyncPipe	[i]	<=	0;
+	end
+end
+
+endmodule

src/src/AdcDataRx/delay_controller_wrap.v

@@ -0,0 +1,410 @@
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2012-2015 Xilinx, Inc.
+// This design is confidential and proprietary of Xilinx, All Rights Reserved.
+//////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /   Vendor: Xilinx
+// \   \   \/    Version: 1.2
+//  \   \        Filename: delay_controller_wrap.v
+//  /   /        Date Last Modified: 21JAN2015
+// /___/   /\    Date Created: 8JAN2013
+// \   \  /  \
+//  \___\/\___\
+// 
+//Device: 	7 Series
+//Purpose:  	Controls delays on a per-bit basis
+//		Number of bits from each seres set via an attribute
+//
+//Reference:	XAPP585
+//    
+//Revision History:
+//    Rev 1.0 - First created (nicks)
+//    Rev 1.2 - Updated format (brandond)
+//
+//////////////////////////////////////////////////////////////////////////////
+//
+//  Disclaimer: 
+//
+//		This disclaimer is not a license and does not grant any rights to the materials 
+//              distributed herewith. Except as otherwise provided in a valid license issued to you 
+//              by Xilinx, and to the maximum extent permitted by applicable law: 
+//              (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, 
+//              AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, 
+//              INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR 
+//              FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract 
+//              or tort, including negligence, or under any other theory of liability) for any loss or damage 
+//              of any kind or nature related to, arising under or in connection with these materials, 
+//              including for any direct, or any indirect, special, incidental, or consequential loss 
+//              or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered 
+//              as a result of any action brought by a third party) even if such damage or loss was 
+//              reasonably foreseeable or Xilinx had been advised of the possibility of the same.
+//
+//  Critical Applications:
+//
+//		Xilinx products are not designed or intended to be fail-safe, or for use in any application 
+//		requiring fail-safe performance, such as life-support or safety devices or systems, 
+//		Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
+//		or any other applications that could lead to death, personal injury, or severe property or 
+//		environmental damage (individually and collectively, "Critical Applications"). Customer assumes 
+//		the sole risk and liability of any use of Xilinx products in Critical Applications, subject only 
+//		to applicable laws and regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+//
+//////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ps/1ps
+
+module delay_controller_wrap (m_datain, s_datain, enable_phase_detector, enable_monitor, reset, clk, c_delay_in, m_delay_out, s_delay_out, data_out, bt_val, results, m_delay_1hot, del_mech) ;
+
+parameter integer 	S = 4 ;   			// Set the number of bits
+
+input		[S-1:0]	m_datain ;			// Inputs from master serdes
+input		[S-1:0]	s_datain ;			// Inputs from slave serdes
+input			enable_phase_detector ;		// Enables the phase detector logic when high
+input			enable_monitor ;		// Enables the eye monitoring logic when high
+input			reset ;				// Reset line synchronous to clk 
+input			clk ;				// Global/Regional clock 
+input		[4:0]	c_delay_in ;			// delay value found on clock line
+output		[4:0]	m_delay_out ;			// Master delay control value
+output		[4:0]	s_delay_out ;			// Master delay control value
+output	reg	[S-1:0]	data_out ;			// Output data
+input		[4:0]	bt_val ;			// Calculated bit time value for slave devices
+output	reg	[31:0]	results ;			// eye monitor result data	
+output	reg	[31:0]	m_delay_1hot ;			// Master delay control value as a one-hot vector	
+input			del_mech ;			// changes delay mechanism slightly at higher bit rates
+
+reg	[S-1:0]		mdataouta ;		
+reg			mdataoutb ;		
+reg	[S-1:0]		mdataoutc ;		
+reg	[S-1:0]		sdataouta ;		
+reg			sdataoutb ;		
+reg	[S-1:0]		sdataoutc ;		
+reg			s_ovflw ; 		
+reg	[1:0]		m_delay_mux ;				
+reg	[1:0]		s_delay_mux ;				
+reg			data_mux ;		
+reg			dec_run ;			
+reg			inc_run ;			
+reg			eye_run ;			
+reg	[4:0]		s_state ;					
+reg	[5:0]		pdcount ;					
+reg	[4:0]		m_delay_val_int ;	
+reg	[4:0]		s_delay_val_int ;	
+reg	[4:0]		s_delay_val_eye ;	
+reg			meq_max	;		
+reg			meq_min	;		
+reg			pd_max	;		
+reg			pd_min	;		
+reg			delay_change ;		
+wire	[S-1:0]		all_high ;		
+wire	[S-1:0]		all_low	;		
+wire	[7:0]		msxoria	;		
+wire	[7:0]		msxorda	;		
+reg	[1:0]		action	;		
+reg	[1:0]		msxor_cti ;
+reg	[1:0]		msxor_ctd ;
+reg	[1:0]		msxor_ctix ;
+reg	[1:0]		msxor_ctdx ;
+wire	[2:0]		msxor_ctiy ;
+wire	[2:0]		msxor_ctdy ;
+reg	[7:0]		match ;	
+reg	[31:0]		shifter ;	
+reg	[7:0]		pd_hold ;	
+	
+assign m_delay_out = m_delay_val_int ;
+assign s_delay_out = s_delay_val_int ;
+genvar i ;
+
+generate
+
+for (i = 0 ; i <= S-2 ; i = i+1) begin : loop0
+
+assign msxoria[i+1] = ((~s_ovflw & ((mdataouta[i] & ~mdataouta[i+1] & ~sdataouta[i])   | (~mdataouta[i] & mdataouta[i+1] &  sdataouta[i]))) | 
+	               ( s_ovflw & ((mdataouta[i] & ~mdataouta[i+1] & ~sdataouta[i+1]) | (~mdataouta[i] & mdataouta[i+1] &  sdataouta[i+1])))) ; // early bits                   
+assign msxorda[i+1] = ((~s_ovflw & ((mdataouta[i] & ~mdataouta[i+1] &  sdataouta[i])   | (~mdataouta[i] & mdataouta[i+1] & ~sdataouta[i])))) | 
+	               ( s_ovflw & ((mdataouta[i] & ~mdataouta[i+1] &  sdataouta[i+1]) | (~mdataouta[i] & mdataouta[i+1] & ~sdataouta[i+1]))) ;	// late bits
+end 
+endgenerate
+
+assign msxoria[0] = ((~s_ovflw & ((mdataoutb & ~mdataouta[0] & ~sdataoutb)    | (~mdataoutb & mdataouta[0] &  sdataoutb))) | 			// first early bit
+	             ( s_ovflw & ((mdataoutb & ~mdataouta[0] & ~sdataouta[0]) | (~mdataoutb & mdataouta[0] &  sdataouta[0])))) ;
+assign msxorda[0] = ((~s_ovflw & ((mdataoutb & ~mdataouta[0] &  sdataoutb)    | (~mdataoutb & mdataouta[0] & ~sdataoutb)))) | 			// first late bit
+	             ( s_ovflw & ((mdataoutb & ~mdataouta[0] &  sdataouta[0]) | (~mdataoutb & mdataouta[0] & ~sdataouta[0]))) ;
+
+always @ (posedge clk) begin				// generate number of incs or decs for low 4 bits
+	case (msxoria[3:0])
+		4'h0    : msxor_cti <= 2'h0 ;
+		4'h1    : msxor_cti <= 2'h1 ;
+		4'h2    : msxor_cti <= 2'h1 ;
+		4'h3    : msxor_cti <= 2'h2 ;
+		4'h4    : msxor_cti <= 2'h1 ;
+		4'h5    : msxor_cti <= 2'h2 ;
+		4'h6    : msxor_cti <= 2'h2 ;
+		4'h8    : msxor_cti <= 2'h1 ;
+		4'h9    : msxor_cti <= 2'h2 ;
+		4'hA    : msxor_cti <= 2'h2 ;
+		4'hC    : msxor_cti <= 2'h2 ;
+		default : msxor_cti <= 2'h3 ;
+	endcase
+	case (msxorda[3:0])
+		4'h0    : msxor_ctd <= 2'h0 ;
+		4'h1    : msxor_ctd <= 2'h1 ;
+		4'h2    : msxor_ctd <= 2'h1 ;
+		4'h3    : msxor_ctd <= 2'h2 ;
+		4'h4    : msxor_ctd <= 2'h1 ;
+		4'h5    : msxor_ctd <= 2'h2 ;
+		4'h6    : msxor_ctd <= 2'h2 ;
+		4'h8    : msxor_ctd <= 2'h1 ;
+		4'h9    : msxor_ctd <= 2'h2 ;
+		4'hA    : msxor_ctd <= 2'h2 ;
+		4'hC    : msxor_ctd <= 2'h2 ;
+		default : msxor_ctd <= 2'h3 ;
+	endcase
+	case (msxoria[7:4])				// generate number of incs or decs for high n bits, max 4
+		4'h0    : msxor_ctix <= 2'h0 ;
+		4'h1    : msxor_ctix <= 2'h1 ;
+		4'h2    : msxor_ctix <= 2'h1 ;
+		4'h3    : msxor_ctix <= 2'h2 ;
+		4'h4    : msxor_ctix <= 2'h1 ;
+		4'h5    : msxor_ctix <= 2'h2 ;
+		4'h6    : msxor_ctix <= 2'h2 ;
+		4'h8    : msxor_ctix <= 2'h1 ;
+		4'h9    : msxor_ctix <= 2'h2 ;
+		4'hA    : msxor_ctix <= 2'h2 ;
+		4'hC    : msxor_ctix <= 2'h2 ;
+		default : msxor_ctix <= 2'h3 ;
+	endcase
+	case (msxorda[7:4])
+		4'h0    : msxor_ctdx <= 2'h0 ;
+		4'h1    : msxor_ctdx <= 2'h1 ;
+		4'h2    : msxor_ctdx <= 2'h1 ;
+		4'h3    : msxor_ctdx <= 2'h2 ;
+		4'h4    : msxor_ctdx <= 2'h1 ;
+		4'h5    : msxor_ctdx <= 2'h2 ;
+		4'h6    : msxor_ctdx <= 2'h2 ;
+		4'h8    : msxor_ctdx <= 2'h1 ;
+		4'h9    : msxor_ctdx <= 2'h2 ;
+		4'hA    : msxor_ctdx <= 2'h2 ;
+		4'hC    : msxor_ctdx <= 2'h2 ;
+		default : msxor_ctdx <= 2'h3 ;
+	endcase
+end
+
+assign msxor_ctiy = {1'b0, msxor_cti} + {1'b0, msxor_ctix} ;
+assign msxor_ctdy = {1'b0, msxor_ctd} + {1'b0, msxor_ctdx} ;
+
+always @ (posedge clk) begin
+	if (msxor_ctiy == msxor_ctdy) begin
+		action <= 2'h0 ;
+	end
+	else if (msxor_ctiy > msxor_ctdy) begin
+		action <= 2'h1 ;
+	end 
+	else begin
+		action <= 2'h2 ;
+	end
+end
+		       	       
+generate
+for (i = 0 ; i <= S-1 ; i = i+1) begin : loop1
+assign all_high[i] = 1'b1 ;
+assign all_low[i] = 1'b0 ;
+end 
+endgenerate
+
+always @ (posedge clk) begin
+	mdataouta <= m_datain ;
+	mdataoutb <= mdataouta[S-1] ;
+	sdataouta <= s_datain ;
+	sdataoutb <= sdataouta[S-1] ;
+end
+	
+always @ (posedge clk) begin
+	if (reset == 1'b1) begin
+		s_ovflw <= 1'b0 ;
+		pdcount <= 6'b100000 ;
+		m_delay_val_int <= c_delay_in ; 			// initial master delay
+		s_delay_val_int <= c_delay_in ; 			// initial slave delay
+		data_mux <= 1'b0 ;
+		m_delay_mux <= 2'b01 ;
+		s_delay_mux <= 2'b01 ;
+		s_state <= 5'b00000 ;
+		inc_run <= 1'b0 ;
+		dec_run <= 1'b0 ;
+		eye_run <= 1'b0 ;
+		s_delay_val_eye <= 5'h00 ;
+		shifter <= 32'h00000001 ;
+		delay_change <= 1'b0 ;
+		results <= 32'h00000000 ;
+		pd_hold <= 8'h00 ;
+	end
+	else begin
+		case (m_delay_mux)
+			2'b00   : mdataoutc <= {mdataouta[S-2:0], mdataoutb} ;
+			2'b10   : mdataoutc <= {m_datain[0],      mdataouta[S-1:1]} ;
+			default : mdataoutc <= mdataouta ;
+		endcase 
+		case (s_delay_mux)  
+			2'b00   : sdataoutc <= {sdataouta[S-2:0], sdataoutb} ;
+			2'b10   : sdataoutc <= {s_datain[0],      sdataouta[S-1:1]} ;
+			default : sdataoutc <= sdataouta ;
+		endcase
+		if (m_delay_val_int == bt_val) begin
+			meq_max <= 1'b1 ;
+		end else begin 
+			meq_max <= 1'b0 ;
+		end 
+		if (m_delay_val_int == 5'h00) begin
+			meq_min <= 1'b1 ;
+		end else begin 
+			meq_min <= 1'b0 ;
+		end 
+		if (pdcount == 6'h3F && pd_max == 1'b0 && delay_change == 1'b0) begin
+			pd_max <= 1'b1 ;
+		end else begin 
+			pd_max <= 1'b0 ;
+		end 
+		if (pdcount == 6'h00 && pd_min == 1'b0 && delay_change == 1'b0) begin
+			pd_min <= 1'b1 ;
+		end else begin 
+			pd_min <= 1'b0 ;
+		end
+		if (delay_change == 1'b1 || inc_run == 1'b1 || dec_run == 1'b1 || eye_run == 1'b1) begin
+			pd_hold <= 8'hFF ;
+			pdcount <= 6'b100000 ; 
+		end													// increment filter count
+		else if (pd_hold[7] == 1'b1) begin
+			pdcount <= 6'b100000 ; 
+			pd_hold <= {pd_hold[6:0], 1'b0} ;
+		end
+		else if (action[0] == 1'b1 && pdcount != 6'b111111) begin 
+			pdcount <= pdcount + 6'h01 ; 
+		end													// decrement filter count
+		else if (action[1] == 1'b1 && pdcount != 6'b000000) begin 
+			pdcount <= pdcount - 6'h01 ; 
+		end
+		if ((enable_phase_detector == 1'b1 && pd_max == 1'b1 && delay_change == 1'b0) || inc_run == 1'b1) begin					// increment delays, check for master delay = max
+			delay_change <= 1'b1 ;
+			if (meq_max == 1'b0 && inc_run == 1'b0) begin
+				m_delay_val_int <= m_delay_val_int + 5'h01 ;
+			end 
+			else begin											// master is max
+				s_state[3:0] <= s_state[3:0] + 4'h1 ;
+				case (s_state[3:0]) 
+				4'b0000 : begin inc_run <= 1'b1 ; s_delay_val_int <= bt_val ; end			// indicate state machine running and set slave delay to bit time 
+				4'b0110 : begin data_mux <= 1'b1 ; m_delay_val_int <= 5'b00000 ; end			// change data mux over to forward slave data and set master delay to zero
+				4'b1001 : begin m_delay_mux <= m_delay_mux - 2'h1 ; end 				// change delay mux over to forward with a 1-bit less advance
+				4'b1110 : begin data_mux <= 1'b0 ; end 							// change data mux over to forward master data
+				4'b1111 : begin s_delay_mux <= m_delay_mux ; inc_run <= 1'b0 ; end			// change delay mux over to forward with a 1-bit less advance
+				default : begin inc_run <= 1'b1 ; end
+				endcase 
+			end
+		end
+		else if ((enable_phase_detector == 1'b1 && pd_min == 1'b1 && delay_change == 1'b0) || dec_run == 1'b1) begin				// decrement delays, check for master delay = 0
+			delay_change <= 1'b1 ;
+			if (meq_min == 1'b0 && dec_run == 1'b0) begin
+				m_delay_val_int <= m_delay_val_int - 5'h01 ;
+			end
+			else begin 											// master is zero
+				s_state[3:0] <= s_state[3:0] + 4'h1 ;
+				case (s_state[3:0]) 
+				4'b0000 : begin dec_run <= 1'b1 ; s_delay_val_int <= 5'b00000 ; end			// indicate state machine running and set slave delay to zero 
+				4'b0110 : begin data_mux <= 1'b1 ;  m_delay_val_int <= bt_val ;	end			// change data mux over to forward slave data and set master delay to bit time 
+				4'b1001 : begin m_delay_mux <= m_delay_mux + 2'h1 ; end  				// change delay mux over to forward with a 1-bit more advance
+				4'b1110 : begin data_mux <= 1'b0 ; end 							// change data mux over to forward master data
+				4'b1111 : begin s_delay_mux <= m_delay_mux ; dec_run <= 1'b0 ; end			// change delay mux over to forward with a 1-bit less advance
+				default : begin dec_run <= 1'b1 ; end
+				endcase 
+			end
+		end
+		else if (enable_monitor == 1'b1 && (eye_run == 1'b1 || delay_change == 1'b1)) begin
+			delay_change <= 1'b0 ;
+			s_state <= s_state + 5'h01 ;
+			case (s_state) 
+				5'b00000 : begin eye_run <= 1'b1 ; s_delay_val_int <= s_delay_val_eye ; end						// indicate state machine running and set slave delay to monitor value 
+				5'b10110 : begin 
+				           if (match == 8'hFF) begin results <= results | shifter ; end			//. set or clear result bit
+				           else begin results <= results & ~shifter ; end 							 
+				           if (s_delay_val_eye == bt_val) begin 					// only monitor active taps, ie as far as btval
+				          	shifter <= 32'h00000001 ; s_delay_val_eye <= 5'h00 ; end
+				           else begin shifter <= {shifter[30:0], shifter[31]} ; 
+				          	s_delay_val_eye <= s_delay_val_eye + 5'h01 ; end			// 
+				          	eye_run <= 1'b0 ; s_state <= 5'h00 ; end
+				default :  begin eye_run <= 1'b1 ; end
+			endcase 
+		end
+		else begin
+			delay_change <= 1'b0 ;
+			if (m_delay_val_int >= {1'b0, bt_val[4:1]} &&  del_mech == 1'b0) begin 						// set slave delay to 1/2 bit period beyond or behind the master delay
+				s_delay_val_int <= m_delay_val_int - {1'b0, bt_val[4:1]} ;
+				s_ovflw <= 1'b0 ;
+			end
+			else begin
+				s_delay_val_int <= m_delay_val_int + {1'b0, bt_val[4:1]} ;
+				s_ovflw <= 1'b1 ;
+			end 
+		end 
+		if (enable_phase_detector == 1'b0 && delay_change == 1'b0) begin
+			delay_change <= 1'b1 ;
+		end
+	end
+	if (enable_phase_detector == 1'b1) begin
+		if (data_mux == 1'b0) begin
+			data_out <= mdataoutc ;
+		end else begin 
+			data_out <= sdataoutc ;
+		end
+	end
+	else begin
+		data_out <= m_datain ;	
+	end
+end
+
+always @ (posedge clk) begin
+	if ((mdataouta == sdataouta)) begin
+		match <= {match[6:0], 1'b1} ;
+	end else begin
+		match <= {match[6:0], 1'b0} ;
+	end
+end
+
+always @ (m_delay_val_int) begin
+	case (m_delay_val_int)
+	    	5'b00000	: m_delay_1hot <= 32'h00000001 ;
+	    	5'b00001	: m_delay_1hot <= 32'h00000002 ;
+	    	5'b00010	: m_delay_1hot <= 32'h00000004 ;
+	    	5'b00011	: m_delay_1hot <= 32'h00000008 ;
+	    	5'b00100	: m_delay_1hot <= 32'h00000010 ;
+	    	5'b00101	: m_delay_1hot <= 32'h00000020 ;
+	    	5'b00110	: m_delay_1hot <= 32'h00000040 ;
+	    	5'b00111	: m_delay_1hot <= 32'h00000080 ;
+	    	5'b01000	: m_delay_1hot <= 32'h00000100 ;
+	    	5'b01001	: m_delay_1hot <= 32'h00000200 ;
+	    	5'b01010	: m_delay_1hot <= 32'h00000400 ;
+	    	5'b01011	: m_delay_1hot <= 32'h00000800 ;
+	    	5'b01100	: m_delay_1hot <= 32'h00001000 ;
+	    	5'b01101	: m_delay_1hot <= 32'h00002000 ;
+	    	5'b01110	: m_delay_1hot <= 32'h00004000 ;
+	    	5'b01111	: m_delay_1hot <= 32'h00008000 ;
+            	5'b10000	: m_delay_1hot <= 32'h00010000 ;
+            	5'b10001	: m_delay_1hot <= 32'h00020000 ;
+            	5'b10010	: m_delay_1hot <= 32'h00040000 ;
+            	5'b10011	: m_delay_1hot <= 32'h00080000 ;
+            	5'b10100	: m_delay_1hot <= 32'h00100000 ;
+            	5'b10101	: m_delay_1hot <= 32'h00200000 ;
+            	5'b10110	: m_delay_1hot <= 32'h00400000 ;
+            	5'b10111	: m_delay_1hot <= 32'h00800000 ;
+            	5'b11000	: m_delay_1hot <= 32'h01000000 ;
+            	5'b11001	: m_delay_1hot <= 32'h02000000 ;
+            	5'b11010	: m_delay_1hot <= 32'h04000000 ;
+            	5'b11011	: m_delay_1hot <= 32'h08000000 ;
+            	5'b11100	: m_delay_1hot <= 32'h10000000 ;
+            	5'b11101	: m_delay_1hot <= 32'h20000000 ;
+            	5'b11110	: m_delay_1hot <= 32'h40000000 ;
+            	default		: m_delay_1hot <= 32'h80000000 ; 
+         endcase
+end
+   	
+endmodule

src/src/AdcDataRx/n_x_serdes_1_to_7_mmcm_idelay_sdr.v

@@ -0,0 +1,169 @@
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2012-2015 Xilinx, Inc.
+// This design is confidential and proprietary of Xilinx, All Rights Reserved.
+//////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /   Vendor: Xilinx
+// \   \   \/    Version: 1.2
+//  \   \        Filename: n_x_serdes_1_to_7_mmcm_idelay_sdr.v
+//  /   /        Date Last Modified:  21JAN2015
+// /___/   /\    Date Created: 5MAR2010
+// \   \  /  \
+//  \___\/\___\
+// 
+//Device: 	7 Series
+//Purpose:  	Wrapper for multiple 1 to 7 SDR clock and data receiver using one PLL/MMCM for clock multiplication
+//
+//Reference:	XAPP585
+//    
+//Revision History:
+//    Rev 1.0 - First created (nicks)
+//    Rev 1.1 - Generate loop changed to correct problem when only one channel
+//    Rev 1.2 - Eye monitoring added, upated format
+//
+//////////////////////////////////////////////////////////////////////////////
+//
+//  Disclaimer: 
+//
+//		This disclaimer is not a license and does not grant any rights to the materials 
+//              distributed herewith. Except as otherwise provided in a valid license issued to you 
+//              by Xilinx, and to the maximum extent permitted by applicable law: 
+//              (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, 
+//              AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, 
+//              INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR 
+//              FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract 
+//              or tort, including negligence, or under any other theory of liability) for any loss or damage 
+//              of any kind or nature related to, arising under or in connection with these materials, 
+//              including for any direct, or any indirect, special, incidental, or consequential loss 
+//              or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered 
+//              as a result of any action brought by a third party) even if such damage or loss was 
+//              reasonably foreseeable or Xilinx had been advised of the possibility of the same.
+//
+//  Critical Applications:
+//
+//		Xilinx products are not designed or intended to be fail-safe, or for use in any application 
+//		requiring fail-safe performance, such as life-support or safety devices or systems, 
+//		Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
+//		or any other applications that could lead to death, personal injury, or severe property or 
+//		environmental damage (individually and collectively, "Critical Applications"). Customer assumes 
+//		the sole risk and liability of any use of Xilinx products in Critical Applications, subject only 
+//		to applicable laws and regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+//
+//////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ps/1ps
+
+module n_x_serdes_1_to_7_mmcm_idelay_sdr (clkin_p, clkin_n, datain_p, datain_n, enable_phase_detector, enable_monitor, rxclk, idelay_rdy, reset, rxclk_div, 
+                                          rx_mmcm_lckdps, rx_mmcm_lckd, rx_mmcm_lckdpsbs, clk_data, rx_data, status, debug, bit_rate_value, bit_time_value, eye_info, m_delay_1hot) ;
+
+parameter integer 	N = 8 ;				// Set the number of channels
+parameter integer 	D = 6 ;   			// Parameter to set the number of data lines per channel
+parameter integer      	MMCM_MODE = 1 ;   		// Parameter to set multiplier for MMCM to get VCO in correct operating range. 1 multiplies input clock by 7, 2 multiplies clock by 14, etc
+parameter real 	  	CLKIN_PERIOD = 6.000 ;		// clock period (ns) of input clock on clkin_p
+parameter 		HIGH_PERFORMANCE_MODE = "FALSE";// Parameter to set HIGH_PERFORMANCE_MODE of input delays to reduce jitter
+parameter         	DIFF_TERM = "FALSE" ; 		// Parameter to enable internal differential termination
+parameter         	SAMPL_CLOCK = "BUFIO" ;   	// Parameter to set sampling clock buffer type, BUFIO, BUF_H, BUF_G
+parameter         	PIXEL_CLOCK = "BUF_R" ;       	// Parameter to set pixel clock buffer type, BUF_R, BUF_H, BUF_G
+parameter         	USE_PLL = "FALSE" ;          	// Parameter to enable PLL use rather than MMCM use, overides SAMPL_CLOCK and INTER_CLOCK to be both BUFH
+parameter         	DATA_FORMAT = "PER_CLOCK" ;     // Parameter Used to determine method for mapping input parallel word to output serial words
+                                     	
+input 	[N-1:0]		clkin_p ;			// Input from LVDS clock receiver pin
+input 	[N-1:0]		clkin_n ;			// Input from LVDS clock receiver pin
+input 	[N*D-1:0]	datain_p ;			// Input from LVDS clock data pins
+input 	[N*D-1:0]	datain_n ;			// Input from LVDS clock data pins
+input 			enable_phase_detector ;		// Enables the phase detector logic when high
+input			enable_monitor ;		// Enables the monitor logic when high, note time-shared with phase detector function
+input 			reset ;				// Reset line
+input			idelay_rdy ;			// input delays are ready
+output 			rxclk ;				// Global/BUFIO rx clock network
+output 			rxclk_div ;			// Global/Regional clock output
+output 			rx_mmcm_lckd ; 			// MMCM locked, synchronous to rxclk_d4
+output 			rx_mmcm_lckdps ; 		// MMCM locked and phase shifting finished, synchronous to rxclk_d4
+output 	[N-1:0]		rx_mmcm_lckdpsbs ; 		// MMCM locked and phase shifting finished and bitslipping finished, synchronous to rxclk_div
+output 	[N*7-1:0]	clk_data ;	 		// Clock Data
+output 	[N*D*7-1:0]	rx_data ;	 		// Received Data
+output 	[(10*D+6)*N-1:0]debug ;	 			// debug info
+output 	[6:0]		status ;	 		// clock status
+input 	[15:0]		bit_rate_value ;	 	// Bit rate in Mbps, for example 16'h0585
+output	[4:0]		bit_time_value ;		// Calculated bit time value for slave devices
+output	[32*D*N-1:0]	eye_info ;			// Eye info
+output	[32*D*N-1:0]	m_delay_1hot ;			// Master delay control value as a one-hot vector
+
+wire			rxclk_d4 ;
+wire			pd ;
+
+serdes_1_to_7_mmcm_idelay_sdr #(
+	.SAMPL_CLOCK		(SAMPL_CLOCK),
+	.PIXEL_CLOCK		(PIXEL_CLOCK),
+	.USE_PLL		(USE_PLL),
+	.HIGH_PERFORMANCE_MODE	(HIGH_PERFORMANCE_MODE),
+      	.D			(D),				// Number of data lines
+      	.CLKIN_PERIOD		(CLKIN_PERIOD),			// Set input clock period
+      	.MMCM_MODE		(MMCM_MODE),			// Set mmcm vco, either 1 or 2
+	.DIFF_TERM		(DIFF_TERM),
+	.DATA_FORMAT		(DATA_FORMAT))
+rx0 (
+	.clkin_p   		(clkin_p[0]),
+	.clkin_n   		(clkin_n[0]),
+	.datain_p     		(datain_p[D-1:0]),
+	.datain_n     		(datain_n[D-1:0]),
+	.enable_phase_detector	(enable_phase_detector),
+	.enable_monitor		(enable_monitor),
+	.rxclk    		(rxclk),
+	.idelay_rdy		(idelay_rdy),
+	.rxclk_div		(rxclk_div),
+	.reset     		(reset),
+	.rx_mmcm_lckd		(rx_mmcm_lckd),
+	.rx_mmcm_lckdps		(rx_mmcm_lckdps),
+	.rx_mmcm_lckdpsbs	(rx_mmcm_lckdpsbs[0]),
+	.clk_data  		(clk_data[6:0]),
+	.rx_data		(rx_data[7*D-1:0]),
+	.bit_rate_value		(bit_rate_value),
+	.bit_time_value		(bit_time_value),
+	.status			(status),
+	.eye_info		(eye_info[32*D-1:0]),
+	.rst_iserdes		(rst_iserdes),
+	.m_delay_1hot		(m_delay_1hot[32*D-1:0]),
+	.debug			(debug[10*D+5:0])
+	);
+
+genvar i ;
+genvar j ;
+
+generate
+if (N > 1) begin
+for (i = 1 ; i <= (N-1) ; i = i+1)
+begin : loop0
+
+serdes_1_to_7_slave_idelay_sdr #(
+      	.D			(D),				// Number of data lines
+	.HIGH_PERFORMANCE_MODE	(HIGH_PERFORMANCE_MODE),
+	.DIFF_TERM		(DIFF_TERM),
+	.DATA_FORMAT		(DATA_FORMAT))
+rxn (
+	.clkin_p   		(clkin_p[i]),
+	.clkin_n   		(clkin_n[i]),
+	.datain_p     		(datain_p[D*(i+1)-1:D*i]),
+	.datain_n     		(datain_n[D*(i+1)-1:D*i]),
+	.enable_phase_detector	(enable_phase_detector),
+	.enable_monitor		(enable_monitor),
+	.rxclk    		(rxclk),
+	.idelay_rdy		(idelay_rdy),
+	.rxclk_div		(),
+	.reset     		(~rx_mmcm_lckdps),
+	.bitslip_finished	(rx_mmcm_lckdpsbs[i]),
+	.clk_data  		(clk_data[7*i+6:7*i]),
+	.rx_data		(rx_data[(D*(i+1)*7)-1:D*i*7]),
+	.bit_time_value		(bit_time_value),
+	.eye_info		(eye_info[32*D*(i+1)-1:32*D*i]),
+	.m_delay_1hot		(m_delay_1hot[(32*D)*(i+1)-1:(32*D)*i]),
+	.rst_iserdes		(rst_iserdes),
+	.debug			(debug[(10*D+6)*(i+1)-1:(10*D+6)*i]));
+
+end
+end
+endgenerate
+endmodule

src/src/AdcDataRx/serdes_1_to_7_mmcm_idelay_sdr.v

@@ -0,0 +1,718 @@
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2012-2015 Xilinx, Inc.
+// This design is confidential and proprietary of Xilinx, All Rights Reserved.
+//////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /   Vendor: Xilinx
+// \   \   \/    Version: 1.2
+//  \   \        Filename: serdes_1_to_7_mmcm_idelay_sdr.v
+//  /   /        Date Last Modified:  21JAN2015
+// /___/   /\    Date Created: 5MAR2010
+// \   \  /  \
+//  \___\/\___\
+//
+//Device: 	7 Series
+//Purpose:  	1 to 7 SDR receiver clock and data receiver using an MMCM for clock multiplication
+//		Data formatting is set by the DATA_FORMAT parameter.
+//		PER_CLOCK (default) format receives bits for 0, 1, 2 .. on the same sample edge
+//		PER_CHANL format receives bits for 0, 7, 14 ..  on the same sample edge
+//
+//Reference:	XAPP585
+//
+//Revision History:
+//    Rev 1.0 - First created (nicks)
+//    Rev 1.1 - PER_CLOCK and PER_CHANL descriptions swapped
+//    Rev 1.2 - Eye monitoring added, updated format
+//
+//////////////////////////////////////////////////////////////////////////////
+//
+//  Disclaimer:
+//
+//		This disclaimer is not a license and does not grant any rights to the materials
+//              distributed herewith. Except as otherwise provided in a valid license issued to you
+//              by Xilinx, and to the maximum extent permitted by applicable law:
+//              (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
+//              AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
+//              INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
+//              FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
+//              or tort, including negligence, or under any other theory of liability) for any loss or damage
+//              of any kind or nature related to, arising under or in connection with these materials,
+//              including for any direct, or any indirect, special, incidental, or consequential loss
+//              or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
+//              as a result of any action brought by a third party) even if such damage or loss was
+//              reasonably foreseeable or Xilinx had been advised of the possibility of the same.
+//
+//  Critical Applications:
+//
+//		Xilinx products are not designed or intended to be fail-safe, or for use in any application
+//		requiring fail-safe performance, such as life-support or safety devices or systems,
+//		Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
+//		or any other applications that could lead to death, personal injury, or severe property or
+//		environmental damage (individually and collectively, "Critical Applications"). Customer assumes
+//		the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
+//		to applicable laws and regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+//
+//////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ps/1ps
+
+module serdes_1_to_7_mmcm_idelay_sdr (clkin_p, clkin_n, datain_p, datain_n, enable_phase_detector, enable_monitor, rxclk, idelay_rdy, reset, rxclk_div,
+                                      rx_mmcm_lckdps, rx_mmcm_lckd, rx_mmcm_lckdpsbs, clk_data, rx_data, status, debug, bit_rate_value, bit_time_value, m_delay_1hot, rst_iserdes, eye_info) ;
+
+parameter integer 	D = 8 ;   			// Parameter to set the number of data lines
+parameter integer      	MMCM_MODE = 1 ;   		// Parameter to set multiplier for MMCM to get VCO in correct operating range. 1 multiplies input clock by 7, 2 multiplies clock by 14, etc
+parameter 		HIGH_PERFORMANCE_MODE = "FALSE";// Parameter to set HIGH_PERFORMANCE_MODE of input delays to reduce jitter
+parameter real 	  	CLKIN_PERIOD = 6.000 ;		// clock period (ns) of input clock on clkin_p
+parameter         	DIFF_TERM = "FALSE" ; 		// Parameter to enable internal differential termination
+parameter         	SAMPL_CLOCK = "BUFIO" ;   	// Parameter to set sampling clock buffer type, BUFIO, BUF_H, BUF_G
+parameter         	PIXEL_CLOCK = "BUF_R" ;       	// Parameter to set final pixel buffer type, BUF_R, BUF_H, BUF_G
+parameter         	USE_PLL = "FALSE" ;          	// Parameter to enable PLL use rather than MMCM use, note, PLL does not support BUFIO and BUFR
+parameter         	DATA_FORMAT = "PER_CLOCK" ;     // Parameter Used to determine method for mapping input parallel word to output serial words
+
+input 			clkin_p ;			// Input from LVDS clock receiver pin
+input 			clkin_n ;			// Input from LVDS clock receiver pin
+input 	[D-1:0]		datain_p ;			// Input from LVDS clock data pins
+input 	[D-1:0]		datain_n ;			// Input from LVDS clock data pins
+input 			enable_phase_detector ;		// Enables the phase detector logic when high
+input			enable_monitor ;		// Enables the monitor logic when high, note time-shared with phase detector function
+input 			reset ;				// Reset line
+input			idelay_rdy ;			// input delays are ready
+output 			rxclk ;				// Global/BUFIO rx clock network
+output 			rxclk_div ;			// Global/Regional clock output
+output 			rx_mmcm_lckd ; 			// MMCM locked, synchronous to rxclk_div
+output 			rx_mmcm_lckdps ; 		// MMCM locked and phase shifting finished, synchronous to rxclk_div
+output 			rx_mmcm_lckdpsbs ; 		// MMCM locked and phase shifting finished and bitslipping finished, synchronous to rxclk_div
+output 	[6:0]		clk_data ;	 		// Clock Data
+output 	[D*7-1:0]	rx_data ;	 		// Received Data
+output 	[10*D+5:0]	debug ;	 			// debug info
+output 	[6:0]		status ;	 		// clock status info
+input 	[15:0]		bit_rate_value ;	 	// Bit rate in Mbps, eg 16'h0585
+output	[4:0]		bit_time_value ;		// Calculated bit time value for slave devices
+output	reg		rst_iserdes ;			// serdes reset signal
+output	[32*D-1:0]	eye_info ;			// Eye info
+output	[32*D-1:0]	m_delay_1hot ;			// Master delay control value as a one-hot vector
+
+wire	[D*5-1:0]	m_delay_val_in ;
+wire	[D*5-1:0]	s_delay_val_in ;
+reg	[1:0]		bsstate ;
+reg 			bslip ;
+reg	[3:0]		bcount ;
+wire 	[6:0] 		clk_iserdes_data ;
+reg 	[6:0] 		clk_iserdes_data_d ;
+reg 			enable ;
+reg 			flag1 ;
+reg 			flag2 ;
+reg 	[2:0] 		state2 ;
+reg 	[4:0] 		state2_count ;
+reg 	[5:0] 		scount ;
+reg 			locked_out ;
+reg			chfound ;
+reg			chfoundc ;
+reg			not_rx_mmcm_lckd_int ;
+reg	[4:0]		c_delay_in ;
+reg	[4:0]		c_delay_in_target ;
+reg			c_delay_in_ud ;
+wire 	[D-1:0]		rx_data_in_p ;
+wire 	[D-1:0]		rx_data_in_n ;
+wire 	[D-1:0]		rx_data_in_m ;
+wire 	[D-1:0]		rx_data_in_s ;
+wire 	[D-1:0]		rx_data_in_md ;
+wire 	[D-1:0]		rx_data_in_sd ;
+wire	[(7*D)-1:0] 	mdataout ;
+wire	[(7*D)-1:0] 	mdataoutd ;
+wire	[(7*D)-1:0] 	sdataout ;
+reg			data_different ;
+reg			bs_finished ;
+reg			not_bs_finished ;
+reg	[4:0]		bt_val ;
+wire			mmcm_locked ;
+wire			rx_mmcmout_x1 ;
+wire			rx_mmcmout_xs ;
+reg			rstcserdes ;
+reg	[1:0]		c_loop_cnt ;
+
+parameter [D-1:0] 	RX_SWAP_MASK = 16'h0000 ;	// pinswap mask for input data bits (0 = no swap (default), 1 = swap). Allows inputs to be connected the wrong way round to ease PCB routing.
+
+assign clk_data = clk_iserdes_data ;
+assign debug = {s_delay_val_in, m_delay_val_in, bslip, c_delay_in} ;
+assign rx_mmcm_lckdpsbs = bs_finished & mmcm_locked ;
+assign rx_mmcm_lckd = ~not_rx_mmcm_lckd_int & mmcm_locked ;
+assign rx_mmcm_lckdps = ~not_rx_mmcm_lckd_int & locked_out & mmcm_locked ;
+assign bit_time_value = bt_val ;
+
+always @ (bit_rate_value) begin			// Generate tap number to be used for input bit rate
+	if      (bit_rate_value > 16'h1068) begin bt_val <= 5'h0C ; end
+	else if (bit_rate_value > 16'h0986) begin bt_val <= 5'h0D ; end
+	else if (bit_rate_value > 16'h0916) begin bt_val <= 5'h0E ; end
+	else if (bit_rate_value > 16'h0855) begin bt_val <= 5'h0F ; end
+	else if (bit_rate_value > 16'h0801) begin bt_val <= 5'h10 ; end
+	else if (bit_rate_value > 16'h0754) begin bt_val <= 5'h11 ; end
+	else if (bit_rate_value > 16'h0712) begin bt_val <= 5'h12 ; end
+	else if (bit_rate_value > 16'h0675) begin bt_val <= 5'h13 ; end
+	else if (bit_rate_value > 16'h0641) begin bt_val <= 5'h14 ; end
+	else if (bit_rate_value > 16'h0611) begin bt_val <= 5'h15 ; end
+	else if (bit_rate_value > 16'h0583) begin bt_val <= 5'h16 ; end
+	else if (bit_rate_value > 16'h0557) begin bt_val <= 5'h17 ; end
+	else if (bit_rate_value > 16'h0534) begin bt_val <= 5'h18 ; end
+	else if (bit_rate_value > 16'h0513) begin bt_val <= 5'h19 ; end
+	else if (bit_rate_value > 16'h0493) begin bt_val <= 5'h1A ; end
+	else if (bit_rate_value > 16'h0475) begin bt_val <= 5'h1B ; end
+	else if (bit_rate_value > 16'h0458) begin bt_val <= 5'h1C ; end
+	else if (bit_rate_value > 16'h0442) begin bt_val <= 5'h1D ; end
+	else if (bit_rate_value > 16'h0427) begin bt_val <= 5'h1E ; end
+	else                                begin bt_val <= 5'h1F ; end
+end
+
+// Bitslip state machine
+
+always @ (posedge rxclk_div)
+begin
+if (locked_out == 1'b0) begin
+	bslip <= 1'b0 ;
+	bsstate <= 1 ;
+	enable <= 1'b0 ;
+	bcount <= 4'h0 ;
+	bs_finished <= 1'b0 ;
+	not_bs_finished <= 1'b1 ;
+end
+else begin
+	enable <= 1'b1 ;
+   	if (enable == 1'b1) begin
+   		if (clk_iserdes_data != 7'b1111111) begin flag1 <= 1'b1 ; end else begin flag1 <= 1'b0 ; end
+   		if (clk_iserdes_data != 7'b0000000) begin flag2 <= 1'b1 ; end else begin flag2 <= 1'b0 ; end
+     		if (bsstate == 0) begin
+   			if (flag1 == 1'b1 && flag2 == 1'b1) begin
+     		   		bslip <= 1'b1 ;						// bitslip needed
+     		   		bsstate <= 1 ;
+     		   	end
+     		   	else begin
+     		   		bs_finished <= 1'b1 ;					// bitslip done
+     		   		not_bs_finished <= 1'b0 ;				// bitslip done
+     		   	end
+		end
+   		else if (bsstate == 1) begin
+     		   	bslip <= 1'b0 ;
+     		   	bcount <= bcount + 4'h1 ;
+   			if (bcount == 4'hF) begin
+     		   		bsstate <= 0 ;
+     		   	end
+   		end
+   	end
+end
+end
+
+// Clock input
+
+IBUFGDS_DIFF_OUT #(
+	.DIFF_TERM 		(DIFF_TERM),
+	.IBUF_LOW_PWR		("FALSE"))
+iob_clk_in (
+	.I    			(clkin_p),
+	.IB       		(clkin_n),
+	.O         		(rx_clk_in_p),
+	.OB         		(rx_clk_in_n));
+
+genvar i ;
+genvar j ;
+
+IDELAYE2 #(
+	.HIGH_PERFORMANCE_MODE 	(HIGH_PERFORMANCE_MODE),
+      	.IDELAY_VALUE		(1),
+      	.DELAY_SRC		("IDATAIN"),
+      	.IDELAY_TYPE		("VAR_LOAD"))
+idelay_cm(
+	.DATAOUT		(rx_clkin_p_d),
+	.C			(rxclk_div),
+	.CE			(1'b0),
+	.INC			(1'b0),
+	.DATAIN			(1'b0),
+	.IDATAIN		(rx_clk_in_p),
+	.LD			(1'b1),
+	.LDPIPEEN		(1'b0),
+	.REGRST			(1'b0),
+	.CINVCTRL		(1'b0),
+	.CNTVALUEIN		(c_delay_in),
+	.CNTVALUEOUT		());
+
+IDELAYE2 #(
+	.HIGH_PERFORMANCE_MODE 	(HIGH_PERFORMANCE_MODE),
+      	.IDELAY_VALUE		(1),
+      	.DELAY_SRC		("IDATAIN"),
+      	.IDELAY_TYPE		("VAR_LOAD"))
+idelay_cs(
+	.DATAOUT		(rx_clk_in_n_d),
+	.C			(rxclk_div),
+	.CE			(1'b0),
+	.INC			(1'b0),
+	.DATAIN			(1'b0),
+	.IDATAIN		(~rx_clk_in_n),
+	.LD			(1'b1),
+	.LDPIPEEN		(1'b0),
+	.REGRST			(1'b0),
+	.CINVCTRL		(1'b0),
+	.CNTVALUEIN		({1'b0, bt_val[4:1]}),
+	.CNTVALUEOUT		());
+
+ISERDESE2 #(
+	.DATA_WIDTH     	(7),
+	.DATA_RATE      	("SDR"),
+//	.SERDES_MODE    	("MASTER"),
+	.IOBDELAY	    	("IFD"),
+	.INTERFACE_TYPE 	("NETWORKING"))
+iserdes_cm (
+	.D       		(1'b0),
+	.DDLY     		(rx_clk_in_n_d),
+	.CE1     		(1'b1),
+	.CE2     		(1'b1),
+	.CLK    		(rxclk),
+	.CLKB    		(~rxclk),
+	.RST     		(rstcserdes),
+	.CLKDIV  		(rxclk_div),
+	.CLKDIVP  		(1'b0),
+	.OCLK    		(1'b0),
+	.OCLKB    		(1'b0),
+	.DYNCLKSEL    		(1'b0),
+	.DYNCLKDIVSEL  		(1'b0),
+	.SHIFTIN1 		(1'b0),
+	.SHIFTIN2 		(1'b0),
+	.BITSLIP 		(bslip),
+	.O	 		(),
+	.Q8 			(),
+	.Q7 			(clk_iserdes_data[0]),
+	.Q6 			(clk_iserdes_data[1]),
+	.Q5 			(clk_iserdes_data[2]),
+	.Q4 			(clk_iserdes_data[3]),
+	.Q3 			(clk_iserdes_data[4]),
+	.Q2 			(clk_iserdes_data[5]),
+	.Q1 			(clk_iserdes_data[6]),
+	.OFB 			(),
+	.SHIFTOUT1 		(),
+	.SHIFTOUT2 		());
+
+generate
+if (USE_PLL == "FALSE") begin : loop8					// use an MMCM
+assign status[6] = 1'b1 ;
+
+MMCME2_ADV #(
+      	.BANDWIDTH		("OPTIMIZED"),  		
+      	.CLKFBOUT_MULT_F	(7*MMCM_MODE),
+      	.CLKFBOUT_PHASE		(0.0),
+      	.CLKIN1_PERIOD		(CLKIN_PERIOD),
+      	.CLKIN2_PERIOD		(CLKIN_PERIOD),
+      	.CLKOUT0_DIVIDE_F	(1*MMCM_MODE),
+      	.CLKOUT0_DUTY_CYCLE	(0.5),
+      	.CLKOUT0_PHASE		(0.0),
+	.CLKOUT0_USE_FINE_PS	("FALSE"),
+      	.CLKOUT1_DIVIDE		(6*MMCM_MODE),
+      	.CLKOUT1_DUTY_CYCLE	(0.5),
+      	.CLKOUT1_PHASE		(22.5),
+	.CLKOUT1_USE_FINE_PS	("FALSE"),
+      	.CLKOUT2_DIVIDE		(7*MMCM_MODE),
+      	.CLKOUT2_DUTY_CYCLE	(0.5),
+      	.CLKOUT2_PHASE		(0.0),
+	.CLKOUT2_USE_FINE_PS	("FALSE"),
+      	.CLKOUT3_DIVIDE		(7),
+      	.CLKOUT3_DUTY_CYCLE	(0.5),
+      	.CLKOUT3_PHASE		(0.0),
+      	.CLKOUT4_DIVIDE		(7),
+      	.CLKOUT4_DUTY_CYCLE	(0.5),
+      	.CLKOUT4_PHASE		(0.0),
+      	.CLKOUT5_DIVIDE		(7),
+      	.CLKOUT5_DUTY_CYCLE	(0.5),
+      	.CLKOUT5_PHASE		(0.0),
+      	.COMPENSATION		("ZHOLD"),
+      	.DIVCLK_DIVIDE		(1),
+      	.REF_JITTER1		(0.100))
+rx_mmcm_adv_inst (
+      	.CLKFBOUT		(rx_mmcmout_x1),
+      	.CLKFBOUTB		(),
+      	.CLKFBSTOPPED		(),
+      	.CLKINSTOPPED		(),
+      	.CLKOUT0		(rx_mmcmout_xs),
+      	.CLKOUT0B		(),
+      	.CLKOUT1		(),
+      	.CLKOUT1B		(),
+      	.CLKOUT2		(),
+      	.CLKOUT2B		(),
+      	.CLKOUT3		(),
+      	.CLKOUT3B		(),
+      	.CLKOUT4		(),
+      	.CLKOUT5		(),
+      	.CLKOUT6		(),
+      	.DO			(),
+      	.DRDY			(),
+      	.PSDONE			(),
+      	.PSCLK			(1'b0),
+      	.PSEN			(1'b0),
+      	.PSINCDEC		(1'b0),
+      	.PWRDWN			(1'b0),
+      	.LOCKED			(mmcm_locked),
+      	.CLKFBIN		(rxclk_div),
+      	.CLKIN1			(rx_clkin_p_d),
+      	.CLKIN2			(1'b0),
+      	.CLKINSEL		(1'b1),
+      	.DADDR			(7'h00),
+      	.DCLK			(1'b0),
+      	.DEN			(1'b0),
+      	.DI			(16'h0000),
+      	.DWE			(1'b0),
+      	.RST			(reset)) ;
+
+   assign status[3:2] = 2'b00 ;
+
+   if (PIXEL_CLOCK == "BUF_G") begin 						// Final clock selection
+      BUFG	bufg_mmcm_x1 (.I(rx_mmcmout_x1), .O(rxclk_div)) ;
+      assign status[1:0] = 2'b00 ;
+   end
+   else if (PIXEL_CLOCK == "BUF_R") begin
+      BUFR #(.BUFR_DIVIDE("1"),.SIM_DEVICE("7SERIES"))bufr_mmcm_x1 (.I(rx_mmcmout_x1),.CE(1'b1),.O(rxclk_div),.CLR(1'b0)) ;
+      assign status[1:0] = 2'b01 ;
+   end
+   else begin
+      BUFH	bufh_mmcm_x1 (.I(rx_mmcmout_x1), .O(rxclk_div)) ;
+      assign status[1:0] = 2'b10 ;
+   end
+
+   if (SAMPL_CLOCK == "BUF_G") begin						// Sample clock selection
+      BUFG	bufg_mmcm_xn (.I(rx_mmcmout_xs), .O(rxclk)) ;
+      assign status[5:4] = 2'b00 ;
+   end
+   else if (SAMPL_CLOCK == "BUFIO") begin
+      BUFIO  	bufio_mmcm_xn (.I (rx_mmcmout_xs), .O(rxclk)) ;
+      assign status[5:4] = 2'b11 ;
+   end
+   else begin
+      BUFH	bufh_mmcm_xn (.I(rx_mmcmout_xs), .O(rxclk)) ;
+      assign status[5:4] = 2'b10 ;
+   end
+
+end
+else begin
+assign status[6] = 1'b0 ;
+
+PLLE2_ADV #(
+      	.BANDWIDTH		("OPTIMIZED"),
+      	.CLKFBOUT_MULT		(42),
+      	.CLKFBOUT_PHASE		(0.0),
+      	.CLKIN1_PERIOD		(CLKIN_PERIOD),
+      	.CLKIN2_PERIOD		(CLKIN_PERIOD),
+      	.CLKOUT0_DIVIDE		(3),
+      	.CLKOUT0_DUTY_CYCLE	(0.5),
+      	.CLKOUT0_PHASE		(0.0),
+      	.CLKOUT1_DIVIDE		(21),
+      	.CLKOUT1_DUTY_CYCLE	(0.5),
+      	.CLKOUT1_PHASE		(0),
+      	.CLKOUT2_DIVIDE		(7*MMCM_MODE),
+      	.CLKOUT2_DUTY_CYCLE	(0.5),
+      	.CLKOUT2_PHASE		(0.0),
+      	.CLKOUT3_DIVIDE		(7),
+      	.CLKOUT3_DUTY_CYCLE	(0.5),
+      	.CLKOUT3_PHASE		(0.0),
+      	.CLKOUT4_DIVIDE		(7),
+      	.CLKOUT4_DUTY_CYCLE	(0.5),
+      	.CLKOUT4_PHASE		(0.0),
+      	.CLKOUT5_DIVIDE		(7),
+      	.CLKOUT5_DUTY_CYCLE	(0.5),
+      	.CLKOUT5_PHASE		(0.0),
+      	.COMPENSATION		("ZHOLD"),
+      	.DIVCLK_DIVIDE		(1),
+      	.REF_JITTER1		(0.100))
+rx_plle2_adv_inst (
+      	.CLKFBOUT		(rx_mmcmFb),
+      	.CLKOUT0		(rx_mmcmout_xs),
+      	.CLKOUT1		(rx_mmcmout_x1),
+      	.CLKOUT2		(),
+      	.CLKOUT3		(),
+      	.CLKOUT4		(),
+      	.CLKOUT5		(),
+      	.DO			(),
+      	.DRDY			(),
+      	.PWRDWN			(1'b0),
+      	.LOCKED			(mmcm_locked),
+      	.CLKFBIN		(ClkFb),
+      	.CLKIN1			(rx_clkin_p_d),
+      	.CLKIN2			(1'b0),
+      	.CLKINSEL		(1'b1),
+      	.DADDR			(7'h00),
+      	.DCLK			(1'b0),
+      	.DEN			(1'b0),
+      	.DI			(16'h0000),
+      	.DWE			(1'b0),
+      	.RST			(reset)) ;
+
+   assign status[3:2] = 2'b00 ;
+
+   if (PIXEL_CLOCK == "BUF_G") begin 						// Final clock selection
+      BUFG	bufg_pll_x1 (.I(rx_mmcmout_x1), .O(rxclk_div)) ;
+	  BUFG	bufg_pll_fb (.I(rx_mmcmFb), .O(ClkFb)) ;
+      assign status[1:0] = 2'b00 ;
+   end
+   else if (PIXEL_CLOCK == "BUF_R") begin
+      BUFR #(.BUFR_DIVIDE("1"),.SIM_DEVICE("7SERIES"))bufr_pll_x1 (.I(rx_mmcmout_x1),.CE(1'b1),.O(rxclk_div),.CLR(1'b0)) ;
+      assign status[1:0] = 2'b01 ;
+   end
+   else begin
+      BUFH	bufh_pll_x1 (.I(rx_mmcmout_x1), .O(rxclk_div)) ;
+      assign status[1:0] = 2'b10 ;
+   end
+
+   if (SAMPL_CLOCK == "BUF_G") begin						// Sample clock selection
+      BUFG	bufg_pll_xn (.I(rx_mmcmout_xs), .O(rxclk)) ;
+      assign status[5:4] = 2'b00 ;
+   end
+   else if (SAMPL_CLOCK == "BUFIO") begin
+      BUFIO  	bufio_pll_xn (.I (rx_mmcmout_xs), .O(rxclk)) ;
+      assign status[5:4] = 2'b11 ;
+   end
+   else begin
+      BUFH	bufh_pll_xn (.I(rx_mmcmout_xs), .O(rxclk)) ;
+      assign status[5:4] = 2'b10 ;
+   end
+
+end
+endgenerate
+
+always @ (posedge rxclk_div) begin				//
+	clk_iserdes_data_d <= clk_iserdes_data ;
+	if ((clk_iserdes_data != clk_iserdes_data_d) && (clk_iserdes_data != 7'h00) && (clk_iserdes_data != 7'h7F)) begin
+		data_different <= 1'b1 ;
+	end
+	else begin
+		data_different <= 1'b0 ;
+	end
+end
+
+always @ (posedge rxclk_div) begin						// clock delay shift state machine
+	not_rx_mmcm_lckd_int <= ~(mmcm_locked & idelay_rdy) ;
+	rstcserdes <= not_rx_mmcm_lckd_int | rst_iserdes ;
+	if (not_rx_mmcm_lckd_int == 1'b1) begin
+		scount <= 6'h00 ;
+		state2 <= 0 ;
+		state2_count <= 5'h00 ;
+		locked_out <= 1'b0 ;
+		chfoundc <= 1'b1 ;
+		c_delay_in <= bt_val ;							// Start the delay line at the current bit period
+		rst_iserdes <= 1'b0 ;
+		c_loop_cnt <= 2'b00 ;
+	end
+	else begin
+		if (scount[5] == 1'b0) begin
+			scount <= scount + 6'h01 ;
+		end
+		state2_count <= state2_count + 5'h01 ;
+		if (chfoundc == 1'b1) begin
+			chfound <= 1'b0 ;
+		end
+		else if (chfound == 1'b0 && data_different == 1'b1) begin
+			chfound <= 1'b1 ;
+		end
+		if ((state2_count == 5'h1F && scount[5] == 1'b1)) begin
+			case(state2)
+			0	: begin							// decrement delay and look for a change
+				  if (chfound == 1'b1 || (c_loop_cnt == 2'b11 && c_delay_in == 5'h00)) begin  // quit loop if we've been around a few times
+					chfoundc <= 1'b1 ;
+					state2 <= 1 ;
+				  end
+				  else begin
+					chfoundc <= 1'b0 ;
+					if (c_delay_in != 5'h00) begin			// check for underflow
+						c_delay_in <= c_delay_in - 5'h01 ;
+					end
+					else begin
+						c_delay_in <= bt_val ;
+						c_loop_cnt <= c_loop_cnt + 2'b01 ;
+					end
+				  end
+				  end
+			1	: begin							// add half a bit period using input information
+				  state2 <= 2 ;
+				  if (c_delay_in < {1'b0, bt_val[4:1]}) begin		// choose the lowest delay value to minimise jitter
+				   	c_delay_in_target <= c_delay_in + {1'b0, bt_val[4:1]} ;
+				  end
+				  else begin
+				   	c_delay_in_target <= c_delay_in - {1'b0, bt_val[4:1]} ;
+				  end
+				  end
+			2 	: begin
+				  if (c_delay_in == c_delay_in_target) begin
+				   	state2 <= 3 ;
+				  end
+				  else begin
+				   	if (c_delay_in_ud == 1'b1) begin		// move gently to end position to stop MMCM unlocking
+						c_delay_in <= c_delay_in + 5'h01 ;
+				   		c_delay_in_ud <= 1'b1 ;
+				   	end
+				   	else begin
+						c_delay_in <= c_delay_in - 5'h01 ;
+				   		c_delay_in_ud <= 1'b0 ;
+				   	end
+				  end
+				  end
+			3 	: begin rst_iserdes <= 1'b1 ; state2 <= 4 ; end		// remove serdes reset
+			default	: begin							// issue locked out signal
+				  rst_iserdes <= 1'b0 ;  locked_out <= 1'b1 ;
+			 	  end
+			endcase
+		end
+	end
+end
+
+generate
+for (i = 0 ; i <= D-1 ; i = i+1)
+begin : loop3
+
+delay_controller_wrap # (
+	.S 			(7))
+dc_inst (
+	.m_datain		(mdataout[7*i+6:7*i]),
+	.s_datain		(sdataout[7*i+6:7*i]),
+	.enable_phase_detector	(enable_phase_detector),
+	.enable_monitor		(enable_monitor),
+	.reset			(not_bs_finished),
+	.clk			(rxclk_div),
+	.c_delay_in		({1'b0, bt_val[4:1]}),
+	.m_delay_out		(m_delay_val_in[5*i+4:5*i]),
+	.s_delay_out		(s_delay_val_in[5*i+4:5*i]),
+	.data_out		(mdataoutd[7*i+6:7*i]),
+	.bt_val			(bt_val),
+	.del_mech		(1'b0),
+	.m_delay_1hot		(m_delay_1hot[32*i+31:32*i]),
+	.results		(eye_info[32*i+31:32*i])) ;
+
+// Data bit Receivers
+
+IBUFDS_DIFF_OUT #(
+	.DIFF_TERM 		(DIFF_TERM))
+data_in (
+	.I    			(datain_p[i]),
+	.IB       		(datain_n[i]),
+	.O         		(rx_data_in_p[i]),
+	.OB         		(rx_data_in_n[i]));
+
+assign rx_data_in_m[i] = rx_data_in_p[i]  ^ RX_SWAP_MASK[i] ;
+assign rx_data_in_s[i] = ~rx_data_in_n[i] ^ RX_SWAP_MASK[i] ;
+
+IDELAYE2 #(
+	.HIGH_PERFORMANCE_MODE	(HIGH_PERFORMANCE_MODE),
+      	.IDELAY_VALUE		(0),
+      	.DELAY_SRC		("IDATAIN"),
+      	.IDELAY_TYPE		("VAR_LOAD"))
+idelay_m(
+	.DATAOUT		(rx_data_in_md[i]),
+	.C			(rxclk_div),
+	.CE			(1'b0),
+	.INC			(1'b0),
+	.DATAIN			(1'b0),
+	.IDATAIN		(rx_data_in_m[i]),
+	.LD			(1'b1),
+	.LDPIPEEN		(1'b0),
+	.REGRST			(1'b0),
+	.CINVCTRL		(1'b0),
+	.CNTVALUEIN		(m_delay_val_in[5*i+4:5*i]),
+	.CNTVALUEOUT		());
+
+ISERDESE2 #(
+	.DATA_WIDTH     	(7),
+	.DATA_RATE      	("SDR"),
+	.SERDES_MODE    	("MASTER"),
+	.IOBDELAY	    	("IFD"),
+	.INTERFACE_TYPE 	("NETWORKING"))
+iserdes_m (
+	.D       		(1'b0),
+	.DDLY     		(rx_data_in_md[i]),
+	.CE1     		(1'b1),
+	.CE2     		(1'b1),
+	.CLK	   		(rxclk),
+	.CLKB    		(~rxclk),
+	.RST     		(rst_iserdes),
+	.CLKDIV  		(rxclk_div),
+	.CLKDIVP  		(1'b0),
+	.OCLK    		(1'b0),
+	.OCLKB    		(1'b0),
+	.DYNCLKSEL    		(1'b0),
+	.DYNCLKDIVSEL  		(1'b0),
+	.SHIFTIN1 		(1'b0),
+	.SHIFTIN2 		(1'b0),
+	.BITSLIP 		(bslip),
+	.O	 		(),
+	.Q8  			(),
+	.Q7  			(mdataout[7*i+0]),
+	.Q6  			(mdataout[7*i+1]),
+	.Q5  			(mdataout[7*i+2]),
+	.Q4  			(mdataout[7*i+3]),
+	.Q3  			(mdataout[7*i+4]),
+	.Q2  			(mdataout[7*i+5]),
+	.Q1  			(mdataout[7*i+6]),
+	.OFB 			(),
+	.SHIFTOUT1		(),
+	.SHIFTOUT2 		());
+
+IDELAYE2 #(
+	.HIGH_PERFORMANCE_MODE	(HIGH_PERFORMANCE_MODE),
+      	.IDELAY_VALUE		(0),
+      	.DELAY_SRC		("IDATAIN"),
+      	.IDELAY_TYPE		("VAR_LOAD"))
+idelay_s(
+	.DATAOUT		(rx_data_in_sd[i]),
+	.C			(rxclk_div),
+	.CE			(1'b0),
+	.INC			(1'b0),
+	.DATAIN			(1'b0),
+	.IDATAIN		(rx_data_in_s[i]),
+	.LD			(1'b1),
+	.LDPIPEEN		(1'b0),
+	.REGRST			(1'b0),
+	.CINVCTRL		(1'b0),
+	.CNTVALUEIN		(s_delay_val_in[5*i+4:5*i]),
+	.CNTVALUEOUT		());
+
+ISERDESE2 #(
+	.DATA_WIDTH     	(7),
+	.DATA_RATE      	("SDR"),
+//	.SERDES_MODE    	("SLAVE"),
+	.IOBDELAY	    	("IFD"),
+	.INTERFACE_TYPE 	("NETWORKING"))
+iserdes_s (
+	.D       		(1'b0),
+	.DDLY     		(rx_data_in_sd[i]),
+	.CE1     		(1'b1),
+	.CE2     		(1'b1),
+	.CLK	   		(rxclk),
+	.CLKB    		(~rxclk),
+	.RST     		(rst_iserdes),
+	.CLKDIV  		(rxclk_div),
+	.CLKDIVP  		(1'b0),
+	.OCLK    		(1'b0),
+	.OCLKB    		(1'b0),
+	.DYNCLKSEL    		(1'b0),
+	.DYNCLKDIVSEL  		(1'b0),
+	.SHIFTIN1 		(1'b0),
+	.SHIFTIN2 		(1'b0),
+	.BITSLIP 		(bslip),
+	.O	 		(),
+	.Q8  			(),
+	.Q7  			(sdataout[7*i+0]),
+	.Q6  			(sdataout[7*i+1]),
+	.Q5  			(sdataout[7*i+2]),
+	.Q4  			(sdataout[7*i+3]),
+	.Q3  			(sdataout[7*i+4]),
+	.Q2  			(sdataout[7*i+5]),
+	.Q1  			(sdataout[7*i+6]),
+	.OFB 			(),
+	.SHIFTOUT1		(),
+	.SHIFTOUT2 		());
+
+for (j = 0 ; j <= 6 ; j = j+1) begin : loop1			// Assign data bits to correct serdes according to required format
+	if (DATA_FORMAT == "PER_CLOCK") begin
+		assign rx_data[D*j+i] = mdataoutd[7*i+j] ;
+	end
+	else begin
+		assign rx_data[7*i+j] = mdataoutd[7*i+j] ;
+	end
+end
+end
+endgenerate
+endmodule

src/src/AdcDataRx/serdes_1_to_7_slave_idelay_sdr.v

@@ -0,0 +1,495 @@
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2012-2015 Xilinx, Inc.
+// This design is confidential and proprietary of Xilinx, All Rights Reserved.
+//////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /   Vendor: Xilinx
+// \   \   \/    Version: 1.2
+//  \   \        Filename: serdes_1_to_7_slave_idelay_sdr.v
+//  /   /        Date Last Modified:  21JAN2015
+// /___/   /\    Date Created: 5MAR2010
+// \   \  /  \
+//  \___\/\___\
+// 
+//Device: 	7 Series
+//Purpose:  	1 to 7 SDR receiver slave data receiver
+//		Data formatting is set by the DATA_FORMAT parameter. 
+//		PER_CLOCK (default) format receives bits for 0, 1, 2 .. on the same sample edge
+//		PER_CHANL format receives bits for 0, 7, 14 ..  on the same sample edge
+//
+//Reference:	XAPP585
+//    
+//Revision History:
+//    Rev 1.0 - First created (nicks)
+//    Rev 1.1 - PER_CLOCK and PER_CHANL descriptions swapped
+//    Rev 1.2 - Eye monitoring added, updated format
+//
+//////////////////////////////////////////////////////////////////////////////
+//
+//  Disclaimer: 
+//
+//		This disclaimer is not a license and does not grant any rights to the materials 
+//              distributed herewith. Except as otherwise provided in a valid license issued to you 
+//              by Xilinx, and to the maximum extent permitted by applicable law: 
+//              (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, 
+//              AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, 
+//              INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR 
+//              FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract 
+//              or tort, including negligence, or under any other theory of liability) for any loss or damage 
+//              of any kind or nature related to, arising under or in connection with these materials, 
+//              including for any direct, or any indirect, special, incidental, or consequential loss 
+//              or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered 
+//              as a result of any action brought by a third party) even if such damage or loss was 
+//              reasonably foreseeable or Xilinx had been advised of the possibility of the same.
+//
+//  Critical Applications:
+//
+//		Xilinx products are not designed or intended to be fail-safe, or for use in any application 
+//		requiring fail-safe performance, such as life-support or safety devices or systems, 
+//		Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
+//		or any other applications that could lead to death, personal injury, or severe property or 
+//		environmental damage (individually and collectively, "Critical Applications"). Customer assumes 
+//		the sole risk and liability of any use of Xilinx products in Critical Applications, subject only 
+//		to applicable laws and regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+//
+//////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ps/1ps
+
+module serdes_1_to_7_slave_idelay_sdr (clkin_p, clkin_n, datain_p, datain_n, enable_phase_detector, enable_monitor, idelay_rdy, rxclk, reset, rxclk_div, 
+                                       bitslip_finished, clk_data, rx_data, debug, bit_time_value, m_delay_1hot, rst_iserdes, eye_info) ;
+
+parameter integer 	D = 8 ;   			// Parameter to set the number of data lines
+parameter 		HIGH_PERFORMANCE_MODE = "FALSE";// Parameter to set HIGH_PERFORMANCE_MODE of input delays to reduce jitter
+parameter         	DIFF_TERM = "FALSE" ; 		// Parameter to enable internal differential termination
+parameter         	DATA_FORMAT = "PER_CLOCK" ;     // Parameter Used to determine method for mapping input parallel word to output serial words
+                                     	
+input 			clkin_p ;			// Input from LVDS clock receiver pin
+input 			clkin_n ;			// Input from LVDS clock receiver pin
+input 	[D-1:0]		datain_p ;			// Input from LVDS clock data pins
+input 	[D-1:0]		datain_n ;			// Input from LVDS clock data pins
+input 			enable_phase_detector ;		// Enables the phase detector logic when high
+input			enable_monitor ;		// Enables the monitor logic when high, note time-shared with phase detector function
+input			idelay_rdy ;			// input delays are ready
+input 			reset ;				// Reset line
+input 			rxclk ;				// Global/BUFIO rx clock network
+input 			rxclk_div ;			// Global/Regional clock input
+output 			bitslip_finished ;	 	// bitslipping finished
+output 	[6:0]		clk_data ;	 		// Clock Data
+output 	[D*7-1:0]	rx_data ;	 		// Received Data
+output 	[10*D+5:0]	debug ;	 			// debug info
+input	[4:0]		bit_time_value ;		// Calculated bit time value from 'master'
+input			rst_iserdes ;			// reset serdes input
+output	[32*D-1:0]	eye_info ;			// Eye info
+output	[32*D-1:0]	m_delay_1hot ;			// Master delay control value as a one-hot vector
+
+wire	[D*5-1:0]	m_delay_val_in ;
+wire	[D*5-1:0]	s_delay_val_in ;
+wire			rx_clk_in ;			
+reg	[1:0]		bsstate ;                 	
+reg 			bslip ;                 	
+reg 			bslipreq ;                 	
+reg 			bslipr ;                 	
+reg	[3:0]		bcount ;                 	
+wire 	[6:0] 		clk_iserdes_data ;      	
+reg 	[6:0] 		clk_iserdes_data_d ;    	
+reg 			enable ;                	
+reg 			flag1 ;                 	
+reg 			flag2 ;                 	
+reg 	[2:0] 		state2 ;			
+reg 	[3:0] 		state2_count ;			
+reg 	[5:0] 		scount ;			
+reg 			locked_out ;	
+reg 			locked_out_rt ;	
+reg			chfound ;	
+reg			chfoundc ;
+reg	[4:0]		c_delay_in ;
+reg	[4:0]		old_c_delay_in ;
+reg			local_reset ;
+wire 	[D-1:0]		rx_data_in_p ;			
+wire 	[D-1:0]		rx_data_in_n ;			
+wire 	[D-1:0]		rx_data_in_m ;			
+wire 	[D-1:0]		rx_data_in_s ;		
+wire 	[D-1:0]		rx_data_in_md ;			
+wire 	[D-1:0]		rx_data_in_sd ;	
+wire	[(7*D)-1:0] 	mdataout ;						
+wire	[(7*D)-1:0] 	mdataoutd ;			
+wire	[(7*D)-1:0] 	sdataout ;						
+reg			bslip_ackr ;		
+reg			bslip_ack ;		
+reg	[1:0]		bstate ;
+reg			data_different ;		
+reg			bs_finished ;
+reg			not_bs_finished ;
+wire	[4:0]		bt_val ;
+reg	[D*4-1:0]	s_state ;                 			
+reg			retry ;
+reg			no_clock ;
+reg	[1:0]		c_loop_cnt ;  
+
+parameter [D-1:0] 	RX_SWAP_MASK = 16'h0000 ;	// pinswap mask for input data bits (0 = no swap (default), 1 = swap). Allows inputs to be connected the wrong way round to ease PCB routing.
+
+assign clk_data = clk_iserdes_data ;
+assign debug = {s_delay_val_in, m_delay_val_in, bslip, c_delay_in} ;
+assign bitslip_finished = bs_finished & ~reset ;
+assign bt_val = bit_time_value ;
+
+always @ (posedge rxclk_div or posedge reset) begin	// generate local sync (rxclk_div) reset
+if (reset == 1'b1 || retry == 1'b1) begin
+	local_reset <= 1'b1 ;
+end
+else begin
+	if (idelay_rdy == 1'b0) begin
+		local_reset <= 1'b1 ;
+	end
+	else begin
+		local_reset <= 1'b0 ;
+	end
+end
+end
+
+// Bitslip state machine
+
+always @ (posedge rxclk_div)
+begin
+if (locked_out == 1'b0) begin
+	bslip <= 1'b0 ;
+	bsstate <= 1 ;
+	enable <= 1'b0 ;
+	bcount <= 4'h0 ;
+	bs_finished <= 1'b0 ;
+	not_bs_finished <= 1'b1 ;
+	retry <= 1'b0 ;
+end
+else begin
+	enable <= 1'b1 ;
+   	if (enable == 1'b1) begin
+   		if (clk_iserdes_data != 7'b1100001) begin flag1 <= 1'b1 ; end else begin flag1 <= 1'b0 ; end
+   		if (clk_iserdes_data != 7'b1100011) begin flag2 <= 1'b1 ; end else begin flag2 <= 1'b0 ; end
+     		if (bsstate == 0) begin
+   			if (flag1 == 1'b1 && flag2 == 1'b1) begin
+     		   		bslip <= 1'b1 ;						// bitslip needed
+     		   		bsstate <= 1 ;
+     		   	end
+     		   	else begin
+     		   		bs_finished <= 1'b1 ;					// bitslip done
+     		   		not_bs_finished <= 1'b0 ;				// bitslip done
+     		   	end
+		end
+   		else if (bsstate == 1) begin				
+     		   	bslip <= 1'b0 ; 
+     		   	bcount <= bcount + 4'h1 ;
+   			if (bcount == 4'hF) begin
+     		   		bsstate <= 0 ;
+     		   	end
+   		end
+   	end
+end
+end
+
+// Clock input 
+
+IBUFGDS #(
+	.DIFF_TERM 		(DIFF_TERM)) 
+iob_clk_in (
+	.I    			(clkin_p),
+	.IB       		(clkin_n),
+	.O         		(rx_clk_in));
+
+genvar i ;
+genvar j ;
+
+IDELAYE2 #(
+	.HIGH_PERFORMANCE_MODE	(HIGH_PERFORMANCE_MODE),
+      	.IDELAY_VALUE		(1),
+      	.DELAY_SRC		("IDATAIN"),
+      	.IDELAY_TYPE		("VAR_LOAD"))
+idelay_cm(               	
+	.DATAOUT		(rx_clk_in_d),
+	.C			(rxclk_div),
+	.CE			(1'b0),
+	.INC			(1'b0),
+	.DATAIN			(1'b0),
+	.IDATAIN		(rx_clk_in),
+	.LD			(1'b1),
+	.LDPIPEEN		(1'b0),
+	.REGRST			(1'b0),
+	.CINVCTRL		(1'b0),
+	.CNTVALUEIN		(c_delay_in),
+	.CNTVALUEOUT		());
+	
+ISERDESE2 #(
+	.DATA_WIDTH     	(7), 				
+	.DATA_RATE      	("SDR"), 			
+	.SERDES_MODE    	("MASTER"), 			
+	.IOBDELAY	    	("IFD"), 			
+	.INTERFACE_TYPE 	("NETWORKING")) 		
+iserdes_cm (
+	.D       		(1'b0),
+	.DDLY     		(rx_clk_in_d),
+	.CE1     		(1'b1),
+	.CE2     		(1'b1),
+	.CLK    		(rxclk),
+	.CLKB    		(~rxclk),
+	.RST     		(local_reset),
+	.CLKDIV  		(rxclk_div),
+	.CLKDIVP  		(1'b0),
+	.OCLK    		(1'b0),
+	.OCLKB    		(1'b0),
+	.DYNCLKSEL    		(1'b0),
+	.DYNCLKDIVSEL  		(1'b0),
+	.SHIFTIN1 		(1'b0),
+	.SHIFTIN2 		(1'b0),
+	.BITSLIP 		(bslip),
+	.O	 		(),
+	.Q8 			(),
+	.Q7 			(clk_iserdes_data[0]),
+	.Q6 			(clk_iserdes_data[1]),
+	.Q5 			(clk_iserdes_data[2]),
+	.Q4 			(clk_iserdes_data[3]),
+	.Q3 			(clk_iserdes_data[4]),
+	.Q2 			(clk_iserdes_data[5]),
+	.Q1 			(clk_iserdes_data[6]),
+	.OFB 			(),
+	.SHIFTOUT1 		(),
+	.SHIFTOUT2 		());	
+
+always @ (posedge rxclk_div) begin				// 
+	clk_iserdes_data_d <= clk_iserdes_data ;
+	if ((clk_iserdes_data != clk_iserdes_data_d) && (clk_iserdes_data != 7'h00) && (clk_iserdes_data != 7'h7F)) begin
+		data_different <= 1'b1 ;
+	end
+	else begin
+		data_different <= 1'b0 ;
+	end
+	if ((clk_iserdes_data == 7'h00) || (clk_iserdes_data == 7'h7F)) begin
+		no_clock <= 1'b1 ;
+	end
+	else begin
+		no_clock <= 1'b0 ;
+	end
+end
+	
+always @ (posedge rxclk_div) begin					// clock delay shift state machine
+	if (local_reset == 1'b1) begin
+		scount <= 6'h00 ;
+		state2 <= 0 ;
+		state2_count <= 4'h0 ;
+		locked_out <= 1'b0 ;
+		chfoundc <= 1'b1 ;
+		chfound <= 1'b0 ;
+		c_delay_in <= bt_val ;						// Start the delay line at the current bit period
+		c_loop_cnt <= 2'b00 ;	
+	end
+	else begin
+		if (scount[5] == 1'b0) begin
+			if (no_clock == 1'b0) begin
+				scount <= scount + 6'h01 ;
+			end
+			else begin
+				scount <= 6'h00 ;
+			end
+		end
+		state2_count <= state2_count + 4'h1 ;
+		if (chfoundc == 1'b1) begin
+			chfound <= 1'b0 ;
+		end
+		else if (chfound == 1'b0 && data_different == 1'b1) begin
+			chfound <= 1'b1 ;
+		end
+		if ((state2_count == 4'hF && scount[5] == 1'b1)) begin
+			case(state2) 					
+			0	: begin							// decrement delay and look for a change
+				  if (chfound == 1'b1 || (c_loop_cnt == 2'b11 && c_delay_in == 5'h00)) begin  // quit loop if we've been around a few times
+					chfoundc <= 1'b1 ;				// change found
+					state2 <= 1 ;
+					c_delay_in <= old_c_delay_in ;
+				  end
+				  else begin
+					chfoundc <= 1'b0 ;
+					old_c_delay_in <= c_delay_in ;
+					if (c_delay_in != 5'h00) begin			// check for underflow
+						c_delay_in <= c_delay_in - 5'h01 ;
+					end
+					else begin
+						c_delay_in <= bt_val ;
+						c_loop_cnt <= c_loop_cnt + 2'b01 ;
+					end
+				  end
+				  end
+			1	: begin							// add half a bit period using input information
+				  state2 <= 2 ;
+				  if (c_delay_in < {1'b0, bt_val[4:1]}) begin		// choose the lowest delay value to minimise jitter
+				   	c_delay_in <= c_delay_in + {1'b0, bt_val[4:1]} ;
+				  end
+				  else begin
+				   	c_delay_in <= c_delay_in - {1'b0, bt_val[4:1]} ;
+				  end
+				  end
+			default	: begin							// issue locked out signal
+				  locked_out <= 1'b1 ;
+			 	  end
+			endcase
+		end
+	end
+end
+			
+generate
+for (i = 0 ; i <= D-1 ; i = i+1)
+begin : loop3
+
+delay_controller_wrap # (
+	.S 			(7))
+dc_inst (                       
+	.m_datain		(mdataout[7*i+6:7*i]),
+	.s_datain		(sdataout[7*i+6:7*i]),
+	.enable_phase_detector	(enable_phase_detector),
+	.enable_monitor		(enable_monitor),
+	.reset			(not_bs_finished),
+	.clk			(rxclk_div),
+	.c_delay_in		(c_delay_in),
+	.m_delay_out		(m_delay_val_in[5*i+4:5*i]),
+	.s_delay_out		(s_delay_val_in[5*i+4:5*i]),
+	.data_out		(mdataoutd[7*i+6:7*i]),
+	.bt_val			(bt_val),
+	.del_mech		(1'b0),
+	.m_delay_1hot		(m_delay_1hot[32*i+31:32*i]),
+	.results		(eye_info[32*i+31:32*i])) ;
+
+// Data bit Receivers 
+
+IBUFDS_DIFF_OUT #(
+	.DIFF_TERM 		(DIFF_TERM)) 
+data_in (
+	.I    			(datain_p[i]),
+	.IB       		(datain_n[i]),
+	.O         		(rx_data_in_p[i]),
+	.OB         		(rx_data_in_n[i]));
+
+assign rx_data_in_m[i] = rx_data_in_p[i]  ^ RX_SWAP_MASK[i] ;
+assign rx_data_in_s[i] = ~rx_data_in_n[i] ^ RX_SWAP_MASK[i] ;
+
+IDELAYE2 #(
+	.HIGH_PERFORMANCE_MODE	(HIGH_PERFORMANCE_MODE),
+      	.IDELAY_VALUE		(0),
+      	.DELAY_SRC		("IDATAIN"),
+      	.IDELAY_TYPE		("VAR_LOAD"))
+idelay_m(               	
+	.DATAOUT		(rx_data_in_md[i]),
+	.C			(rxclk_div),
+	.CE			(1'b0),
+	.INC			(1'b0),
+	.DATAIN			(1'b0),
+	.IDATAIN		(rx_data_in_m[i]),
+	.LD			(1'b1),
+	.LDPIPEEN		(1'b0),
+	.REGRST			(1'b0),
+	.CINVCTRL		(1'b0),
+	.CNTVALUEIN		(m_delay_val_in[5*i+4:5*i]),
+	.CNTVALUEOUT		());
+		
+ISERDESE2 #(
+	.DATA_WIDTH     	(7), 			
+	.DATA_RATE      	("SDR"), 		
+	.SERDES_MODE    	("MASTER"), 		
+	.IOBDELAY	    	("IFD"), 		
+	.INTERFACE_TYPE 	("NETWORKING")) 	
+iserdes_m (
+	.D       		(1'b0),
+	.DDLY     		(rx_data_in_md[i]),
+	.CE1     		(1'b1),
+	.CE2     		(1'b1),
+	.CLK	   		(rxclk),
+	.CLKB    		(~rxclk),
+	.RST     		(rst_iserdes),
+	.CLKDIV  		(rxclk_div),
+	.CLKDIVP  		(1'b0),
+	.OCLK    		(1'b0),
+	.OCLKB    		(1'b0),
+	.DYNCLKSEL    		(1'b0),
+	.DYNCLKDIVSEL  		(1'b0),
+	.SHIFTIN1 		(1'b0),
+	.SHIFTIN2 		(1'b0),
+	.BITSLIP 		(bslip),
+	.O	 		(),
+	.Q8  			(),
+	.Q7  			(mdataout[7*i+0]),
+	.Q6  			(mdataout[7*i+1]),
+	.Q5  			(mdataout[7*i+2]),
+	.Q4  			(mdataout[7*i+3]),
+	.Q3  			(mdataout[7*i+4]),
+	.Q2  			(mdataout[7*i+5]),
+	.Q1  			(mdataout[7*i+6]),
+	.OFB 			(),
+	.SHIFTOUT1		(),
+	.SHIFTOUT2 		());
+
+IDELAYE2 #(
+	.HIGH_PERFORMANCE_MODE	(HIGH_PERFORMANCE_MODE),
+      	.IDELAY_VALUE		(0),
+      	.DELAY_SRC		("IDATAIN"),
+      	.IDELAY_TYPE		("VAR_LOAD"))
+idelay_s(               	
+	.DATAOUT		(rx_data_in_sd[i]),
+	.C			(rxclk_div),
+	.CE			(1'b0),
+	.INC			(1'b0),
+	.DATAIN			(1'b0),
+	.IDATAIN		(rx_data_in_s[i]),
+	.LD			(1'b1),
+	.LDPIPEEN		(1'b0),
+	.REGRST			(1'b0),
+	.CINVCTRL		(1'b0),
+	.CNTVALUEIN		(s_delay_val_in[5*i+4:5*i]),
+	.CNTVALUEOUT		());
+	
+ISERDESE2 #(
+	.DATA_WIDTH     	(7), 			
+	.DATA_RATE      	("SDR"), 		
+//	.SERDES_MODE    	("SLAVE"), 		
+	.IOBDELAY	    	("IFD"), 		
+	.INTERFACE_TYPE 	("NETWORKING")) 	
+iserdes_s (
+	.D       		(1'b0),
+	.DDLY     		(rx_data_in_sd[i]),
+	.CE1     		(1'b1),
+	.CE2     		(1'b1),
+	.CLK	   		(rxclk),
+	.CLKB    		(~rxclk),
+	.RST     		(rst_iserdes),
+	.CLKDIV  		(rxclk_div),
+	.CLKDIVP  		(1'b0),
+	.OCLK    		(1'b0),
+	.OCLKB    		(1'b0),
+	.DYNCLKSEL    		(1'b0),
+	.DYNCLKDIVSEL  		(1'b0),
+	.SHIFTIN1 		(1'b0),
+	.SHIFTIN2 		(1'b0),
+	.BITSLIP 		(bslip),
+	.O	 		(),
+	.Q8  			(),
+	.Q7  			(sdataout[7*i+0]),
+	.Q6  			(sdataout[7*i+1]),
+	.Q5  			(sdataout[7*i+2]),
+	.Q4  			(sdataout[7*i+3]),
+	.Q3  			(sdataout[7*i+4]),
+	.Q2  			(sdataout[7*i+5]),
+	.Q1  			(sdataout[7*i+6]),
+	.OFB 			(),
+	.SHIFTOUT1		(),
+	.SHIFTOUT2 		());
+
+for (j = 0 ; j <= 6 ; j = j+1) begin : loop1			// Assign data bits to correct serdes according to required format
+	if (DATA_FORMAT == "PER_CLOCK") begin
+		assign rx_data[D*j+i] = mdataoutd[7*i+j] ;
+	end 
+	else begin
+		assign rx_data[7*i+j] = mdataoutd[7*i+j] ;
+	end
+end
+end
+endgenerate
+endmodule

src/src/AdcDataRx/top5x2_7to1_sdr_rx.v

@@ -0,0 +1,149 @@
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2012-2015 Xilinx, Inc.
+// This design is confidential and proprietary of Xilinx, All Rights Reserved.
+//////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /   Vendor: Xilinx
+// \   \   \/    Version: 1.2
+//  \   \        Filename: top5x2_7to1_sdr_rx.v
+//  /   /        Date Last Modified:  21JAN2015
+// /___/   /\    Date Created: 2SEP2011
+// \   \  /  \
+//  \___\/\___\
+// 
+//Device: 	7-Series
+//Purpose:  	SDR top level receiver example - 2 channels of 5-bits each
+//
+//Reference:	XAPP585.pdf
+//    
+//Revision History:
+//    Rev 1.0 - First created (nicks)
+//    Rev 1.1 - BUFG added to IDELAY reference clock
+//    Rev 1.2 - Updated format (brandond)
+//
+//////////////////////////////////////////////////////////////////////////////
+//
+//  Disclaimer: 
+//
+//		This disclaimer is not a license and does not grant any rights to the materials 
+//              distributed herewith. Except as otherwise provided in a valid license issued to you 
+//              by Xilinx, and to the maximum extent permitted by applicable law: 
+//              (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, 
+//              AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, 
+//              INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR 
+//              FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract 
+//              or tort, including negligence, or under any other theory of liability) for any loss or damage 
+//              of any kind or nature related to, arising under or in connection with these materials, 
+//              including for any direct, or any indirect, special, incidental, or consequential loss 
+//              or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered 
+//              as a result of any action brought by a third party) even if such damage or loss was 
+//              reasonably foreseeable or Xilinx had been advised of the possibility of the same.
+//
+//  Critical Applications:
+//
+//		Xilinx products are not designed or intended to be fail-safe, or for use in any application 
+//		requiring fail-safe performance, such as life-support or safety devices or systems, 
+//		Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
+//		or any other applications that could lead to death, personal injury, or severe property or 
+//		environmental damage (individually and collectively, "Critical Applications"). Customer assumes 
+//		the sole risk and liability of any use of Xilinx products in Critical Applications, subject only 
+//		to applicable laws and regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+//
+//////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ps/1ps
+
+module top5x2_7to1_sdr_rx 
+#(
+	parameter	integer	D	=	4,		// Set the number of outputs per channel to be 5 in this example
+	parameter	integer	N	=	1,       // Set the number of channels to be 2 in this example
+	parameter	DataWidth	=	14
+)
+(
+	input	reset,					// reset (active high)
+	input	refclkin,				// Reference clock for input delay control
+	input	Locked_i,				// Reference clock for input delay control
+	input	clkin1_p,	
+	input	clkin1_n,			// lvds channel 1 clock input
+	input	[D-1:0]	datain1_p,
+	input	[D-1:0]	datain1_n,			// lvds channel 1 data inputs
+	input	clkin2_p,	
+	input	clkin2_n,			// lvds channel 2 clock input
+	input	[D-1:0]	datain2_p,	
+	input	[D-1:0]	datain2_n,			// lvds channel 2 data inputs
+	output	reg	dummy,
+	output	[27:0]	dout,
+	output	DivClk_o
+	// output	[DataWidth-1:0]	dout
+);// Dummy output for test
+			
+		
+wire	refclkint; 		
+wire	rx_mmcm_lckdps;		
+wire	[1:0]	rx_mmcm_lckdpsbs;	
+wire	rxclk_div;		
+wire	clkin_p;			
+wire	clkin_n;			
+wire	[D*N-1:0]	datain_p;		
+wire	[D*N-1:0]	datain_n;		
+// wire	[N*DataWidth-1:0]	rxdall;			
+wire	[27:0]	rxdall;			
+wire	delay_ready;		
+wire	rx_mmcm_lckd;	
+
+IDELAYCTRL	icontrol 
+(              			// Instantiate input delay control block
+	.REFCLK	(refclkin),
+	.RST	(~Locked_i),
+	.RDY	(delay_ready)
+);
+
+// Input clock and data for 2 channels
+assign	clkin_p		=	clkin1_p;
+assign	clkin_n		=	clkin1_n;
+assign	datain_p	=	datain1_p;
+assign	datain_n	=	datain1_n;
+
+assign	dout		=	rxdall;
+assign	DivClk_o	=	rxclk_div;
+
+n_x_serdes_1_to_7_mmcm_idelay_sdr 
+#(
+	.N	(N),
+	.SAMPL_CLOCK	("BUF_G"),
+	.PIXEL_CLOCK	("BUF_G"),
+	.USE_PLL		("TRUE"),
+	.HIGH_PERFORMANCE_MODE	("FALSE"),
+	.D	(D),				// Number of data lines
+	.CLKIN_PERIOD	(40.000),			// Set input clock period
+	.MMCM_MODE		(4),				// Parameter to set multiplier for MMCM to get VCO in correct operating range. 1 multiplies input clock by 7, 2 multiplies clock by 14, etc
+	.DIFF_TERM		("TRUE"),
+	// .DATA_FORMAT	("PER_CLOCK")
+	.DATA_FORMAT	("PER_CHANL")
+) 			// PER_CLOCK or PER_CHANL data formatting
+ReceiverModule	
+(                          
+	.clkin_p	(clkin_p),
+	.clkin_n	(clkin_n),
+	.datain_p	(datain_p),
+	.datain_n	(datain_n),
+	.enable_phase_detector	(1'b0),
+	.rxclk		(),
+	.idelay_rdy	(delay_ready),
+	.rxclk_div	(rxclk_div),
+	.reset		(reset),
+	.rx_mmcm_lckd		(rx_mmcm_lckd),
+	.rx_mmcm_lckdps		(rx_mmcm_lckdps),
+	.rx_mmcm_lckdpsbs	(rx_mmcm_lckdpsbs),
+	.clk_data	(),
+	.rx_data	(rxdall),
+	.bit_rate_value		(16'h0350),			// required bit rate value
+	.bit_time_value		(),
+	.status		(),
+	.debug		()
+);
+      	
+endmodule

src/src/ClkGen/Clk200Gen.v

@@ -0,0 +1,86 @@
+module Clk200Gen 
+(
+    input	Clk_i,
+    input	Rst_i,
+	output	Clk200_o,
+	output	Clk10Timers_o,
+	output	Clk150_o,
+	
+	output	Locked_o
+);
+
+wire	ClkFb;
+wire	rxFb;
+
+PLLE2_ADV #(
+      	.BANDWIDTH		("OPTIMIZED"),
+      	.CLKFBOUT_MULT		(24),
+      	.CLKFBOUT_PHASE		(0.0),
+      	.CLKIN1_PERIOD		(20),
+      	.CLKIN2_PERIOD		(),
+      	.CLKOUT0_DIVIDE		(6),
+      	.CLKOUT0_DUTY_CYCLE	(0.5),
+      	.CLKOUT0_PHASE		(0.0),
+      	.CLKOUT1_DIVIDE		(120),
+      	.CLKOUT1_DUTY_CYCLE	(0.5),
+      	.CLKOUT1_PHASE		(0.0),
+      	.CLKOUT2_DIVIDE		(8),
+      	.CLKOUT2_DUTY_CYCLE	(0.5),
+      	.CLKOUT2_PHASE		(0.0),
+      	.CLKOUT3_DIVIDE		(120),
+      	.CLKOUT3_DUTY_CYCLE	(0.5),
+      	.CLKOUT3_PHASE		(0.0),
+      	.CLKOUT4_DIVIDE		(7),
+      	.CLKOUT4_DUTY_CYCLE	(0.5),
+      	.CLKOUT4_PHASE		(0.0),
+      	.CLKOUT5_DIVIDE		(7),
+      	.CLKOUT5_DUTY_CYCLE	(0.5),
+      	.CLKOUT5_PHASE		(0.0),
+      	.COMPENSATION		("BUF_IN"),
+      	.DIVCLK_DIVIDE		(1),
+      	.REF_JITTER1		(0.100))
+CommonPll (
+      	.CLKFBOUT		(ClkFb),
+      	.CLKOUT0		(rx_mmcmout_200),
+      	.CLKOUT1		(rx_mmcmout_10),
+      	.CLKOUT2		(rx_mmcmout_150),
+      	.CLKOUT3		(),
+      	.CLKOUT4		(),
+      	.CLKOUT5		(),
+      	.DO				(),
+      	.DRDY			(),
+      	.PWRDWN			(1'b0),
+      	.LOCKED			(Locked_o),
+      	.CLKFBIN		(rxFb),
+      	.CLKIN1			(Clk_i),
+      	.CLKIN2			(1'b0),
+      	.CLKINSEL		(1'b1),
+      	.DADDR			(7'h00),
+      	.DCLK			(1'b0),
+      	.DEN			(1'b0),
+      	.DI				(16'h0000),
+      	.DWE			(1'b0),
+      	.RST			(1'b0)
+) ;
+
+
+BUFG	bufg_mmcm_Fb (.I(ClkFb), .O(rxFb)) ;
+
+BUFG	ctrlClk200 (.I(rx_mmcmout_200), .O(Clk200_o)) ;
+BUFG	ctrlClk10 (.I(rx_mmcmout_10), .O(Clk10Timers_o)) ;
+BUFG	ctrlClk150 (.I(rx_mmcmout_150), .O(Clk150_o)) ;
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+

src/src/DitherGen/DitherGenv2.v

@@ -0,0 +1,131 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:		Churbanov S.
+// 
+// Create Date:    10:00:14 13/08/2019 
+// Design Name: 
+// Module Name:    DspPpiOut 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module DitherGenv2
+#(	
+	parameter	CmdDataRegWith		=	24,
+	parameter	FrAmpWordWidth		=	8,
+	parameter	RefFreqDiv			=	5
+)
+(
+	input	Rst_i,
+	input	Clk_i,	
+	
+	input	[CmdDataRegWith-1:0]	DitherCmd_i,
+	output	DitherCtrlT2R2_o,
+	output	DitherCtrlT1R1_o
+);
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	
+	wire	[FrAmpWordWidth-1:0]	ditherFreq	=	DitherCmd_i[CmdDataRegWith-1-:FrAmpWordWidth];
+	
+	wire	[4-1:0]	ditherAmpT2R2	=	DitherCmd_i[15:12];
+	wire	[4-1:0]	ditherAmpT1R1	=	DitherCmd_i[11:8];
+	wire	[4-1:0]	rampLimit		=	DitherCmd_i[7:4];
+	
+	wire	ditherEnT2R2	=	DitherCmd_i[1];
+	wire	ditherEnT1R1	=	DitherCmd_i[0];
+	
+	wire	[3:0]	ncoArray	[15:0];
+	
+	assign	ncoArray	[0]		=	0;
+	assign	ncoArray	[1]		=	1;
+	assign	ncoArray	[2]		=	2;
+	assign	ncoArray	[3]		=	3;
+	assign	ncoArray	[4]		=	4;
+	assign	ncoArray	[5]		=	5;
+	assign	ncoArray	[6]		=	6;
+	assign	ncoArray	[7]		=	7;
+	assign	ncoArray	[8]		=	8;
+	assign	ncoArray	[9]		=	7;
+	assign	ncoArray	[10]	=	6;
+	assign	ncoArray	[11]	=	5;
+	assign	ncoArray	[12]	=	4;
+	assign	ncoArray	[13]	=	3;
+	assign	ncoArray	[14]	=	2;
+	assign	ncoArray	[15]	=	1;
+	
+	reg	[3:0]	sawCnt;
+	
+	reg	[FrAmpWordWidth-1:0]	currStateT2R2;
+	reg	[FrAmpWordWidth-1:0]	currStateT1R1;
+	
+	wire	[3:0]	ncoSignalT2R2	=	ncoArray[currStateT2R2[FrAmpWordWidth-1-:4]];
+	wire	[3:0]	ncoSignalT1R1	=	ncoArray[currStateT1R1[FrAmpWordWidth-1-:4]];
+
+	wire	dithGenT2R2	=	((ncoSignalT2R2>>ditherAmpT2R2)>sawCnt)	?	1'b1:1'b0;
+	wire	dithGenT1R1	=	((ncoSignalT1R1>>ditherAmpT1R1)>sawCnt)	?	1'b1:1'b0;
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================	
+	assign	DitherCtrlT2R2_o	=	(ditherEnT2R2)	?	dithGenT2R2:1'b0;
+	assign	DitherCtrlT1R1_o	=	(ditherEnT1R1)	?	dithGenT1R1:1'b0;
+//================================================================================
+//  CODING
+//================================================================================	
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(sawCnt	!=	rampLimit)	begin
+			sawCnt	<=	sawCnt	+1;
+		end	else	begin
+			sawCnt	<=	0;
+		end
+	end	else	begin
+		sawCnt	<=	0;
+	end
+end
+
+wire	Clk5=(sawCnt<=10/2-1)?	1'b1:1'b0;
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(sawCnt	==rampLimit)	begin
+			currStateT2R2	<=	currStateT2R2+ditherFreq;
+			currStateT1R1	<=	currStateT1R1+ditherFreq;
+		end
+	end	else	begin
+		currStateT2R2	<=0;
+		currStateT1R1	<=0;
+	end
+end
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

src/src/ExtDspInterface/DspInterface.v

@@ -0,0 +1,364 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// company: 
+// engineer: 
+// 
+// create date:    16:37:06 07/11/2019 
+// design name: 
+// module name:    dsp_linkport_interface 
+// project name: 
+// target devices: 
+// tool versions: 
+// description: 					
+//
+// dependencies: 
+//
+// revision: 
+// revision 0.01 - file created
+// additional comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	DspInterface
+#(	
+	parameter	AdcDataWidth	=	14,	
+	parameter	ExtAdcDataWidth	=	16,	
+	parameter	ODataWidth		=	16,	
+	parameter	ResultWidth		=	40,
+	parameter	ChNum			=	16,
+	parameter	CmdRegWidth		=	32,
+	parameter	CmdDataRegWith	=	24,
+	parameter	HeaderWidth		=	7,
+	parameter	DataCntWidth	=	5,
+	parameter	CmdWidth		=	3
+)
+(
+	input	Clk_i,
+	input	Rst_i,
+	input	OscWind_i,
+	input	StartMeasDsp_i,
+	input	DspReadyForRx_i,
+	input	[31:0]	MeasNum_i,
+	
+	input	Mosi_i,
+	input	Sck_i,
+	input	Ss_i,
+	
+	input	Mode_i,
+	input	[CmdWidth-2:0]		PortSel_i,
+	input	[CmdWidth-1:0]		DecimFactor_i,
+	
+	input	[CmdRegWidth-1:0]	IfFtwL_i,
+	input	[CmdRegWidth-1:0]   IfFtwH_i,
+	
+	output	OscDataRdFlag_o,
+	input	[AdcDataWidth-1:0]	Adc1ChT1Data_i,	
+	input	[AdcDataWidth-1:0]	Adc1ChR1Data_i,	
+	input	[AdcDataWidth-1:0]	Adc2ChR2Data_i,	
+	input	[AdcDataWidth-1:0]	Adc2ChT2Data_i,	
+	
+	output	Mosi_o,
+	output	Sck_o,
+	output	Ss0_o,
+	output	Ss1_o,
+	input	Miso_i,
+	output	Miso_o,
+
+	
+	output	[CmdRegWidth-1:0]	CmdDataReg_o,
+	output	CmdDataVal_o,
+	
+	input	[CmdDataRegWith-1:0]	AnsReg_i,
+	output	[HeaderWidth-1:0]		AnsAddr_o,	
+
+	output	LpOutFs_o,
+	output	LpOutClk_o,
+	output	[ODataWidth-1:0]	LpOutData_o,
+	
+	input	[ResultWidth-1:0]	Adc1T1ImResult_i,
+	input	[ResultWidth-1:0]	Adc1T1ReResult_i,
+	input	[ResultWidth-1:0]	Adc1R1ImResult_i,
+	input	[ResultWidth-1:0]	Adc1R1ReResult_i,	
+	
+	input	[ResultWidth-1:0]	Adc2R2ImResult_i,
+	input	[ResultWidth-1:0]	Adc2R2ReResult_i,
+	input	[ResultWidth-1:0]	Adc2T2ImResult_i,
+	input	[ResultWidth-1:0]	Adc2T2ReResult_i,
+	input	[ChNum-1:0]			ServiseRegData_i,
+
+	input	LpOutStart_i
+);
+//================================================================================
+//	REG/WIRE
+//================================================================================
+	wire	[ResultWidth*(ChNum*2)-1:0]	measDataBus;
+	wire	[ResultWidth*(ChNum*2)-1:0]	fftDataBus;
+	wire	[ResultWidth*(ChNum*2)-1:0]	decimDataBus;
+	
+	reg		[ResultWidth*(ChNum*2)-1:0]	dataForFifo;
+	reg		dataForFifoVal;
+	
+	wire	fftDataBusVal;
+	wire	decimDataBusVal;
+	
+	wire	[ResultWidth*(ChNum*2)-1:0]	measDataBusTx;
+	wire	measDataValTx;
+	
+	wire	ppiBusy;
+	
+	reg	signed	[15:0]	adc1ChT1DataExt;	
+	reg	signed	[15:0]	adc1ChR1DataExt;	
+	reg	signed	[15:0]	adc2ChR2DataExt;	
+	reg	signed	[15:0]	adc2ChT2DataExt;
+	
+	reg		signed	[AdcDataWidth-1:0]	currDataChannel;
+	reg		signed	[AdcDataWidth-1:0]	testDataChannel;
+	wire	signed	[AdcDataWidth-1:0]	currDataChannelDecim;
+	wire	currDataChannelDecimVal;
+	
+	wire	signed	[15:0]	filteredDecimDataI;
+	wire	signed	[15:0]	filteredDecimDataQ;
+	wire	filteredDecimDataVal;
+//================================================================================
+//	ASSIGNMENTS
+//================================================================================
+
+	assign	measDataBus	[(ResultWidth*(ChNum*2-7))-1-:ResultWidth]	=	Adc1T1ImResult_i;
+	assign	measDataBus	[(ResultWidth*(ChNum*2-6))-1-:ResultWidth]	=	Adc1T1ReResult_i;
+	assign	measDataBus	[(ResultWidth*(ChNum*2-5))-1-:ResultWidth]	=	Adc1R1ImResult_i;
+	assign	measDataBus	[(ResultWidth*(ChNum*2-4))-1-:ResultWidth]	=	Adc1R1ReResult_i;
+	assign	measDataBus	[(ResultWidth*(ChNum*2-3))-1-:ResultWidth]	=	Adc2T2ImResult_i;
+	assign	measDataBus	[(ResultWidth*(ChNum*2-2))-1-:ResultWidth]	=	Adc2T2ReResult_i;
+	assign	measDataBus	[(ResultWidth*(ChNum*2-1))-1-:ResultWidth]	=	Adc2R2ImResult_i;
+	assign	measDataBus	[(ResultWidth*(ChNum*2-0))-1-:ResultWidth]	=	Adc2R2ReResult_i;
+	
+	assign	OscDataRdFlag_o	=	measDataValTx;
+	
+//================================================================================
+//	CODING
+//================================================================================
+
+reg	oscWindR;
+reg	[15:0]	testPatternData;
+
+wire	oscWindNeg	=	(!OscWind_i&oscWindR);
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		oscWindR	<=	OscWind_i;
+	end	else	begin
+		oscWindR	<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(oscWindNeg)	begin
+			testPatternData	<=	~testPatternData;
+		end
+	end	else	begin
+		testPatternData	<=	16'h1fff;
+	end
+end
+
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(OscWind_i)	begin
+			if	(testDataChannel	!=	(16'd511*16))	begin
+				testDataChannel	<=	testDataChannel+16'd511;
+			end	else	begin
+				testDataChannel	<=	16'd0;
+			end
+		end	else	begin
+			testDataChannel	<=	16'd0;
+		end
+	end	else	begin
+		testDataChannel	<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		case(PortSel_i)
+			0:	begin
+					// currDataChannel	<=	testDataChannel;
+					currDataChannel	<=	Adc2ChT2Data_i;		//Device T3
+				end
+			1:	begin
+					currDataChannel	<=	Adc2ChR2Data_i;		//Device R3
+				end
+			2:	begin
+					currDataChannel	<=	Adc1ChT1Data_i;		//Device T4
+				end
+			3:	begin
+					currDataChannel	<=	Adc1ChR1Data_i;		//Device R4
+				end
+		endcase
+	end	else	begin
+		currDataChannel	<=	0;
+	end
+end
+	
+SlaveSpi
+#(	
+	.CmdRegWidth	(CmdRegWidth),
+	.DataCntWidth	(DataCntWidth),
+	.HeaderWidth	(HeaderWidth)
+)
+DspSlaveSpi
+(
+	.Clk_i		(Clk_i),
+	.Rst_i		(Rst_i),
+
+	.Data_o		(CmdDataReg_o),
+	.Val_o		(CmdDataVal_o),
+	
+	.Mosi_i		(Mosi_i),
+	.Sck_i		(Sck_i),
+	.Ss_i		(Ss_i),
+	
+	.Mosi_o		(Mosi_o),
+	.Sck_o		(Sck_o),
+	.Ss0_o		(Ss0_o),
+	.Ss1_o		(Ss1_o),
+	
+	.AnsAddr_o	(AnsAddr_o),
+	.AnsReg_i	(AnsReg_i),
+	
+	.Miso_i		(Miso_i),
+	.Miso_o		(Miso_o)
+);
+
+DecimFilterWrapper	DecimFilter
+(
+	.Clk_i			(Clk_i),
+	.Rst_i			(Rst_i),
+	.OscWind_i		(OscWind_i),
+	.DecimFactor_i	(DecimFactor_i),
+	
+	.IfFtwL_i		(IfFtwL_i),
+	.IfFtwH_i		(IfFtwH_i),
+	
+	.AdcData_i		(currDataChannel),
+	// .TestData_o		(testData),
+	
+	.FilteredAdcDataI_o	(filteredDecimDataI),
+	.FilteredAdcDataQ_o	(filteredDecimDataQ),
+	.FilteredDataVal_o	(filteredDecimDataVal)
+);
+
+// FftDataFormer	FftDataFormerInst
+// (
+	// .Clk_i				(Clk_i), 
+	// .Rst_i				(Rst_i),	
+	// .OscWind_i			(OscWind_i),
+	// .MeasNum_i			(MeasNum_i),
+	
+	// .AdcData_i			({filteredDecimDataI,filteredDecimDataQ}),
+	// .AdcData_i			({testPatternData,testPatternData}),
+	// .AdcDataVal_i		(filteredDecimDataVal),
+	
+	// .OscDataBus_o		(fftDataBus),
+	// .OscDataBusVal_o	(fftDataBusVal)
+// );
+
+// decimBlock	
+// #(	
+	// .inOutDataWidth	(14),
+	// .decimCntWidth	(8)
+// )
+// Decimator
+// (
+	// .Clk_i			(Clk_i),
+	// .Rst_i			(Rst_i),
+	// .DecimFactor_i	(DecimFactor_i),
+	// .Data_i			(currDataChannel),
+	// .DataNd_i		(1'b1),
+	// .Data_o			(currDataChannelDecim),
+	// .DataValid_o	(currDataChannelDecimVal)
+// );
+
+OscDataFormer	DecimDataFormer
+(
+	.Clk_i				(Clk_i), 
+	.Rst_i				(Rst_i),	
+	.OscWind_i			(OscWind_i),
+	.MeasNum_i			(MeasNum_i),
+	
+	// .AdcDataVal_i		(currDataChannelDecimVal),
+	// .AdcData_i			(currDataChannelDecim),
+	
+	.AdcDataVal_i		(filteredDecimDataVal),
+	.AdcData_i			(filteredDecimDataI),	
+	
+	.OscDataBus_o		(decimDataBus),
+	.OscDataBusVal_o	(decimDataBusVal)
+);
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(Mode_i)	begin
+			dataForFifo		<=	decimDataBus;
+			dataForFifoVal	<=	decimDataBusVal;
+		end	else	begin
+			dataForFifo		<=	measDataBus;
+			dataForFifoVal	<=	LpOutStart_i;
+		end
+	end	else	begin
+		dataForFifo		<=	0;
+		dataForFifoVal	<=	0;
+	end
+end
+
+MeasDataFifoWrapper		
+#(	
+	.DataWidth	(ResultWidth),
+	.ChNum		(ChNum)
+)
+MeasDataFifoInst
+(
+	.Clk_i			(Clk_i), 
+	.Rst_i			(Rst_i),	
+	.PpiBusy_i		(ppiBusy),	
+	.MeasNum_i		(MeasNum_i),	
+	.StartMeasDsp_i	(StartMeasDsp_i),	
+	.DspReadyForRx_i(DspReadyForRx_i),	
+	// .MeasDataBus_i	(measDataBus),
+	.MeasDataBus_i	(dataForFifo),
+	// .MeasDataVal_i	(LpOutStart_i),	
+	.MeasDataVal_i	(dataForFifoVal),	
+	
+	.MeasDataBus_o	(measDataBusTx),
+	.MeasDataVal_o	(measDataValTx)
+);
+
+DspPpiOut	
+#(	
+	.ODataWidth		(ODataWidth),	
+	.ResultWidth	(ResultWidth), 
+	.ChNum			(ChNum)
+)
+MeasDataPpiOut
+(
+	.Rst_i				(Rst_i),	
+	.Clk_i				(Clk_i),		
+	
+	.MeasDataBus_i		(measDataBusTx),
+	.ServiseRegData_i	(ServiseRegData_i),
+	
+	.PpiBusy_o			(ppiBusy),
+	.LpOutStart_i		(measDataValTx),
+	
+	.LpOutClk_o			(LpOutClk_o),
+	.LpOutFs_o			(LpOutFs_o),
+	.LpOutData_o		(LpOutData_o)
+);
+
+endmodule
+
+
+
+
+
+
+

src/src/ExtDspInterface/DspPpiOut.v

@@ -0,0 +1,160 @@
+`timescale 1ns / 1ps
+(* keep_hierarchy = "yes" *)
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:		Churbanov S.
+// 
+// Create Date:    10:00:14 13/08/2019 
+// Design Name: 
+// Module Name:    DspPpiOut 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module DspPpiOut
+#(	
+	parameter	ODataWidth		=	16,	
+	parameter	ResultWidth		=	40, 
+	parameter	ChNum			=	8,
+	localparam	DataBusWidth	=	((ChNum*2)+1)*ResultWidth,
+	localparam	ServisePattern	=	32'hABCD
+)
+(
+	input	Rst_i,
+	input	Clk_i,	
+	
+	input	[ChNum-1:0]	ServiseRegData_i,
+	input	[ResultWidth*(ChNum*2)-1:0]	MeasDataBus_i,
+	
+	input	LpOutStart_i,
+	output	PpiBusy_o,
+	
+	output	LpOutClk_o,
+	output	LpOutFs_o,
+	output	[ODataWidth-1:0]	LpOutData_o
+);
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	reg	lpDataRst;
+	reg	[5:0]	txCnt	=	6'd0;	
+	reg	[DataBusWidth-1:0]	lpDataBuf;
+	reg	dataShEn;
+	reg	dataValid;
+	
+	reg	lpOutFs;
+	reg	ppiBusy;
+	
+	wire	oddrCe = (txCnt	<=	6'd19 && dataValid)	?	1'b1:1'b0;
+	
+	wire	[7:0]	ampEnT1	=	{{7{1'b0}},ServiseRegData_i[0]};
+	wire	[7:0]	ampEnR1	=	{{7{1'b0}},ServiseRegData_i[1]};
+	wire	[7:0]	ampEnR2	=	{{7{1'b0}},ServiseRegData_i[2]};
+	wire	[7:0]	ampEnT2	=	{{7{1'b0}},ServiseRegData_i[3]};
+	
+	wire	[31:0]	serviceData	=	{ampEnR2,ampEnT2,ampEnR1,ampEnT1};
+	
+	wire	outDataVal	=	(txCnt	<=	18	&&	txCnt	!=	0);
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================	
+	assign	LpOutData_o	=	lpDataBuf[ODataWidth-1:0];
+	assign	LpOutFs_o	=	lpOutFs;
+	assign	PpiBusy_o	=	ppiBusy;
+//================================================================================
+//  CODING
+//================================================================================	
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(LpOutStart_i)	begin
+			ppiBusy	<=	1'b1;
+		end	else	if	(!dataValid)	begin
+			ppiBusy	<=	1'b0;
+		end
+	end	else	begin
+		ppiBusy	<=	1'b0;
+	end
+end
+
+always	@(posedge Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(LpOutStart_i)	begin	
+			txCnt	<=	6'd19;
+		end	else	if	(dataValid)	begin
+			txCnt	<=	txCnt	-	6'd1;
+		end
+	end	else	begin
+		txCnt	<=	6'd0;
+	end
+end
+
+always	@(*)	begin
+	case (txCnt)
+		6'd19:	begin
+					dataShEn	=	1'b0;
+					dataValid	=	1'b1;
+					lpOutFs		=	1'b0;
+				end
+		6'd18:	begin 
+					dataShEn	=	1'b1;
+					dataValid	=	1'b1;
+					lpOutFs		=	1'b1;
+				end
+		6'd17:	begin 
+					dataShEn	=	1'b1;
+					dataValid	=	1'b1;
+					lpOutFs		=	1'b0;
+				end
+		6'd0:	begin	
+					dataShEn	=	1'b0;
+					dataValid	=	1'b0;
+					lpOutFs		=	1'b0;
+				end	
+		default: 
+			begin
+				dataShEn	=	1'b1;
+				dataValid	=	1'b1;
+				lpOutFs		=	1'b0;
+			end
+	endcase
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(txCnt	==	6'd19)	begin
+			lpDataBuf	<=	{serviceData,MeasDataBus_i};
+		end	else	if	(dataShEn)	begin
+			lpDataBuf	<=	{{ODataWidth{1'b0}},lpDataBuf[DataBusWidth-1:ODataWidth]};
+		end
+	end	else	begin
+		lpDataBuf	<=	{DataBusWidth{1'b0}};
+	end
+end
+//================================================================================
+//  INSTANTIATIONS
+//================================================================================		
+ODDR2
+#(
+	.DDR_ALIGNMENT("NONE"),
+	.INIT	(1'b0),
+	.SRTYPE	("SYNC")
+) clk_i10OutInst (
+	.Q		(LpOutClk_o),
+	.C0		(Clk_i),
+	.C1		(~Clk_i),
+	.CE		(1'b1),
+	.D0		(1'b1),
+	.D1		(1'b0),
+	.R		(1'b0),
+	.S		(1'b0)
+);		
+
+endmodule

src/src/ExtDspInterface/SlaveSpi.v

@@ -0,0 +1,213 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 17.09.2020 14:18:14
+// Design Name: 
+// Module Name: SlaveSpi
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module	SlaveSpi
+#(	
+	parameter	CmdRegWidth			=	32,
+	parameter	DataCntWidth		=	6,
+	parameter	HeaderWidth			=	7,
+	parameter	CmdDataRegWith		=	24,
+	parameter	Adc0DirAccessAddr	=	7'h13,
+	parameter	Adc1DirAccessAddr	=	7'h14
+)
+(
+	input	Clk_i,
+	input	Rst_i,
+
+	output	reg	[CmdRegWidth-1:0]	Data_o,
+	output	reg	Val_o,
+	
+	//-----------------------------------
+	//input Spi lines from ext. Dsp
+	input	Mosi_i,
+	input	Sck_i,
+	input	Ss_i,
+	//-----------------------------------
+	
+	//-----------------------------------
+	output	Mosi_o,
+	output	Sck_o,
+	output	Ss0_o,
+	output	Ss1_o,
+	//-----------------------------------
+	
+	output	[HeaderWidth-1:0]		AnsAddr_o,
+	input	[CmdDataRegWith-1:0]	AnsReg_i,
+	
+	input	Miso_i,
+	output	Miso_o
+);
+//================================================================================
+//	REG/WIRE
+//================================================================================
+	reg	[CmdRegWidth-1:0]		dataCaptReg;
+	reg	[DataCntWidth-1:0]		dataCnt;
+	reg	[HeaderWidth-1:0]		ansAddr;
+	reg	spiMode;
+	wire	directTransit	=	(ansAddr	==	Adc0DirAccessAddr)|(ansAddr	==	Adc1DirAccessAddr);
+	reg	txWind;
+	reg	[4:0]	txCnt;
+//================================================================================
+//	ASSIGNMENTS
+//================================================================================
+	assign	Mosi_o		=	(!spiMode&directTransit)?	Mosi_i:1'b1;
+	assign	Sck_o		=	(directTransit)?	Sck_i:1'b0;
+	assign	Ss0_o		=	(directTransit&&(ansAddr==Adc0DirAccessAddr))?	Ss_i:1'b1;
+	assign	Ss1_o		=	(directTransit&&(ansAddr==Adc1DirAccessAddr))?	Ss_i:1'b1;
+	assign	AnsAddr_o	=	ansAddr;
+	assign	Miso_o		=	txWind?	AnsReg_i[txCnt]:1'b0;
+//================================================================================
+//	CODING
+//================================================================================
+always	@(posedge	Sck_i)	begin
+	if	(~Ss_i)	begin
+		dataCaptReg	<=	{dataCaptReg[CmdRegWidth-2:0],Mosi_i};
+	end	else	begin
+		dataCaptReg	<=	dataCaptReg;
+	end
+end
+
+always	@(posedge	Sck_i)	begin
+	if	(~Rst_i)	begin
+		if	(~Ss_i)	begin
+			dataCnt	<=	dataCnt	+	5'd1;
+		end
+	end	else	begin
+		dataCnt	<=	0;
+	end
+end
+
+always	@(posedge	Sck_i)	begin
+	if	(~Rst_i)	begin
+		if	(dataCnt	==	5'd1)	begin
+			if	(dataCaptReg[CmdRegWidth-CmdRegWidth])	begin
+				spiMode	<=	1'b1;
+			end	else	begin
+				spiMode	<=	1'b0;
+			end
+		end
+	end	else	begin
+		spiMode	<=	1'b0;
+	end
+end
+
+always	@(negedge Sck_i)	begin
+	if	(~Rst_i)	begin
+		if	(~Ss_i)	begin
+			if	(dataCnt	==	5'd8)	begin
+				ansAddr	<=	dataCaptReg[CmdRegWidth-26-:HeaderWidth];
+			end	else	if	(dataCnt	==	5'd0)	begin
+				ansAddr	<=	7'h7F;
+			end
+		end	else	begin
+			ansAddr	<=	7'h7F;	
+		end
+	end	else	begin
+		ansAddr	<=	7'h7F;	
+	end
+end
+
+//================================================================================
+//	Generating output signals
+//================================================================================
+reg	ssReg;
+reg	ssRegR;
+
+always	@(posedge	Clk_i)	begin
+	ssReg	<=	Ss_i;
+	ssRegR	<=	ssReg;
+end
+
+reg	ssPos;
+
+always	@(posedge	Clk_i)	begin
+	ssPos	<=	ssReg&!ssRegR;
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!directTransit&!spiMode)	begin
+		if	(ssReg&!ssRegR)	begin
+			Val_o	<=	1'b1;
+		end	else	begin
+			Val_o	<=	0;
+		end
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(((ansAddr	!=	Adc0DirAccessAddr)|(ansAddr	!=	Adc1DirAccessAddr))&!spiMode)	begin
+		if	(ssReg&!ssRegR)	begin
+			Data_o	<=	dataCaptReg;
+		end	
+	end
+end
+
+always	@(*)	begin
+	if	(spiMode	&	!Ss_i)	begin
+		if	(dataCnt	>=5'd8|dataCnt	==	0)	begin
+			txWind	=	1'b1;
+		end	else	begin
+			txWind	=	1'b0;
+		end
+	end	else	begin
+		txWind	=	1'b0;
+	end
+end
+
+always	@(negedge	Sck_i)	begin
+	if	(txWind)	begin
+		if	(~Ss_i	&	txWind	&	txCnt!=	0)	begin
+			txCnt	<=	txCnt	-	5'd1;
+		end	else	begin
+			txCnt	<=	5'd24;
+		end
+	end	else	begin
+		txCnt	<=	5'd24;
+	end
+end
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

src/src/FftDataFiltering/DecimFilterWrapper.v

@@ -0,0 +1,186 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// company: 
+// engineer: 
+// 
+// create date:    16:37:06 07/11/2019 
+// design name: 
+// module name:    dsp_linkport_interface 
+// project name: 
+// target devices: 
+// tool versions: 
+// description: 					
+//
+// dependencies: 
+//
+// revision: 
+// revision 0.01 - file created
+// additional comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	DecimFilterWrapper
+#(	
+	parameter	AdcDataWidth		=	14,
+	parameter	N	=	8,
+	parameter	M	=	1,
+	parameter	FilteredDataWidth	=	30,
+	parameter	FirOutDataWidth		=	48,
+	parameter	FirOutCutBit		=	42
+)
+(
+	input	Clk_i,
+	input	[2:0]	DecimFactor_i,
+	input	Rst_i,
+	input	OscWind_i,
+	
+	input	[24-1:0]	IfFtwL_i,
+	input	[24-1:0]	IfFtwH_i,
+	
+	input	signed	[AdcDataWidth-1:0]	AdcData_i,
+	
+	output	signed	[16-1:0]	FilteredAdcDataI_o,
+	output	signed	[16-1:0]	FilteredAdcDataQ_o,
+	output	FilteredDataVal_o
+);
+//================================================================================
+//	REG/WIRE
+//================================================================================
+	wire	signed	[FilteredDataWidth-1:0]	decimDataI;
+	wire	signed	[FilteredDataWidth-1:0]	decimDataQ;
+	wire	decimDataValI;
+	reg		decimDataValIR;
+	wire	decimDataValQ;
+	reg		decimDataValQR;
+	
+	wire	signed	[FirOutDataWidth-1:0]	firDataOut;
+	wire	firDataOutVal;
+	
+	wire	[AdcDataWidth-1:0]	ncoCos;
+	wire	[AdcDataWidth-1:0]	ncoSin;
+	
+	wire	[AdcDataWidth-1:0]	adcSinResult;
+	wire	adcSinVal;
+	wire	[AdcDataWidth-1:0]	adcCosResult;
+	wire	adcCosVal;
+	
+	reg		[24-1:0]	ifFtwLReg;
+	reg		[24-1:0]	ifFtwHReg;
+	
+	reg		[15:0]	outDataI;
+	reg		[15:0]	outDataQ;
+	
+	localparam	maxWidthForR2	=	5'd18;	//msb for R = 2;
+	localparam	maxWidthForR3	=	5'd21;	//msb for R = 3;
+	// localparam	maxWidthForR4	=	5'd22;	//msb for R = 4;
+	localparam	maxWidthForR4	=	5'd29;	//msb for R = 4;
+	localparam	maxWidthForR5	=	5'd24;	//msb for R = 5;
+	localparam	maxWidthForR6	=	5'd25;	//msb for R = 6;
+	localparam	maxWidthForR7	=	5'd26;	//msb for R = 7;
+	// localparam	maxWidthForR8	=	5'd26;	//msb for R = 8;
+	// localparam	maxWidthForR9	=	5'd27;	//msb for R = 9;
+	// localparam	maxWidthForR10	=	5'd28;	//msb for R = 10;
+	
+//================================================================================
+//	ASSIGNMENTS
+//================================================================================
+
+	assign	FilteredAdcDataI_o	=	outDataI;
+	assign	FilteredAdcDataQ_o	=	outDataQ;
+
+	assign	FilteredDataVal_o	=	decimDataValIR;
+
+
+// {{14{AdcData_i[AdcDataWidth-1]}},AdcData_i}
+
+//================================================================================
+//	CODING
+//================================================================================
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		case(DecimFactor_i)
+			3'd0:	begin
+						outDataI	<=	AdcData_i;
+						outDataQ	<=	AdcData_i;
+						decimDataValIR	<=	OscWind_i;
+						decimDataValQR	<=	OscWind_i;
+					end
+			3'd1:	begin
+						outDataI	<=	AdcData_i;
+						outDataQ	<=	AdcData_i;
+						decimDataValIR	<=	OscWind_i;
+						decimDataValQR	<=	OscWind_i;
+					end
+			3'd2:	begin
+						outDataI	<=	decimDataI[maxWidthForR2-:16];
+						outDataQ	<=	decimDataQ[maxWidthForR2-:16];
+						decimDataValIR	<=	decimDataValI;
+						decimDataValQR	<=	decimDataValQ;
+					end
+			3'd3:	begin
+						outDataI	<=	decimDataI[maxWidthForR3-:16];
+						outDataQ	<=	decimDataQ[maxWidthForR3-:16];
+						decimDataValIR	<=	decimDataValI;
+						decimDataValQR	<=	decimDataValQ;
+					end
+			3'd4:	begin
+						outDataI	<=	decimDataI[maxWidthForR4-:16];
+						outDataQ	<=	decimDataQ[maxWidthForR4-:16];
+						decimDataValIR	<=	decimDataValI;
+						decimDataValQR	<=	decimDataValQ;
+					end
+			3'd5:	begin
+						outDataI	<=	decimDataI[maxWidthForR5-:16];
+						outDataQ	<=	decimDataQ[maxWidthForR5-:16];
+						decimDataValIR	<=	decimDataValI;
+						decimDataValQR	<=	decimDataValQ;
+					end
+			3'd6:	begin
+						outDataI	<=	decimDataI[maxWidthForR6-:16];
+						outDataQ	<=	decimDataQ[maxWidthForR6-:16];
+						decimDataValIR	<=	decimDataValI;
+						decimDataValQR	<=	decimDataValQ;
+					end
+			3'd7:	begin
+						outDataI	<=	decimDataI[maxWidthForR7-:16];
+						outDataQ	<=	decimDataQ[maxWidthForR7-:16];
+						decimDataValIR	<=	decimDataValI;
+						decimDataValQR	<=	decimDataValQ;
+					end
+		endcase
+	end	else	begin
+		outDataI	<=	16'd0;
+		outDataQ	<=	16'd0;
+		decimDataValIR	<=	1'b0;
+		decimDataValQR	<=	1'b0;
+	end
+end
+
+cicFilter 
+#(
+	.N (N),	//filter order
+	.M (M),	//comb delay
+	.filteredDataWidth	(FilteredDataWidth),
+	.inOutDataWidth		(FilteredDataWidth),
+	.decimCntWidth		(7)
+)
+cicFilterInstI
+(
+	.Clk_i			(Clk_i),
+	.Rst_i			(Rst_i),
+	.DecimFactor_i	(DecimFactor_i),
+	.Data_i			({{16{AdcData_i[AdcDataWidth-1]}},AdcData_i}),
+	.DataNd_i		(OscWind_i),
+	.Data_o			(decimDataI),
+	.DataValid_o	(decimDataValI)
+);
+
+endmodule
+
+
+
+
+
+
+
+

src/src/FftDataFiltering/cicFilter.v

@@ -0,0 +1,100 @@
+module cicFilter 
+#(
+	parameter N = 2,	//filter order
+	parameter M = 1,	//comb delay
+	// parameter R = 4,	//decim fartor
+	parameter	filteredDataWidth	=	28,
+	parameter	inOutDataWidth	=	16,
+	parameter	decimCntWidth	=	7
+)
+(
+	input Clk_i,
+	input Rst_i,
+	input [2:0]	DecimFactor_i,
+	input [inOutDataWidth-1:0] Data_i,
+	input DataNd_i,
+	output [filteredDataWidth-1:0] Data_o,
+	output DataValid_o
+);
+	
+wire	[filteredDataWidth-1:0]	inData	[N-1:0];
+
+wire	[filteredDataWidth-1:0]	intFilteredData	[N-1:0];
+wire	intFilteredDataValid	[N-1:0];
+wire	intDataVal	[N-1:0];
+
+wire	[filteredDataWidth-1:0]	decimIntData;
+wire	decimIntDataValid;
+
+wire	[filteredDataWidth-1:0]	combFilteredData	[N-1:0];
+wire	[filteredDataWidth-1:0]	combInData	[N-1:0];
+wire	combDataVal	[N-1:0];
+wire	combFilteredDataVal	[N-1:0];
+
+genvar i,j;
+generate 
+	for (i=0; i<N; i=i+1)	begin: IntFilterGen
+	
+		// assign	inData	[i]		=	(i==0)?{{filteredDataWidth-inOutDataWidth{Data_i[inOutDataWidth-1]}},Data_i}:intFilteredData[i-1][filteredDataWidth-1-:filteredDataWidth];
+		assign	inData	[i]		=	(i==0)?Data_i:intFilteredData[i-1];
+		assign	intDataVal[i]	=	(i==0)?DataNd_i:intFilteredDataValid[i-1];
+		
+		intFilterWrapper
+		#(
+			.filteredDataWidth	(filteredDataWidth),
+			.inOutDataWidth		(filteredDataWidth)
+		)
+		intFilterWrapperInst
+		(
+			.Clk_i		(Clk_i),
+			.Data_i		(inData[i]),
+			.DataNd_i	(intDataVal[i]),
+			.Data_o		(intFilteredData[i]),
+			.DataValid_o(intFilteredDataValid[i])
+		);
+	end
+	
+		decimBlock
+		#(	
+			// .R	(R),
+			.inOutDataWidth	(filteredDataWidth),
+			.decimCntWidth	(decimCntWidth)
+		)
+		decimBlockInst
+		(
+			.Clk_i			(Clk_i),
+			.Rst_i			(Rst_i),
+			.DecimFactor_i	(DecimFactor_i),
+			.Data_i			(intFilteredData[N-1]),
+			.DataNd_i		(intFilteredDataValid[N-1]),
+			.Data_o			(decimIntData),
+			.DataValid_o	(decimIntDataValid)
+		);	
+
+	
+	for (j=0; j<N; j=j+1)	begin: CombFilterGen
+	
+		assign	combInData	[j]	=	(j==0)?decimIntData:combFilteredData[j-1];
+		assign	combDataVal	[j]	=	(j==0)?decimIntDataValid:combFilteredDataVal[j-1];
+		
+		combFilterWrapper
+		#(
+			.M (M),
+			.filteredDataWidth	(filteredDataWidth),
+			.inOutDataWidth		(filteredDataWidth)
+		)
+		combFilterWrapperInst
+		(
+			.Clk_i		(Clk_i),
+			.Rst_i		(Rst_i),
+			.Data_i		(combInData[j]),
+			.DataNd_i	(combDataVal[j]),
+			.Data_o		(combFilteredData[j]),
+			.DataValid_o(combFilteredDataVal[j])
+		);
+	end
+endgenerate
+
+assign	Data_o	=	combFilteredData[N-1];
+assign	DataValid_o	=	combFilteredDataVal[N-1];
+endmodule

src/src/FftDataFiltering/combFilterBlock.v

@@ -0,0 +1,63 @@
+module combFilterBlock 
+#(
+	parameter	M=4,
+	parameter	inOutDataWidth	=	18,
+	parameter	filteredDataWidth	=	25
+)
+(
+	input Clk_i,
+	input Rst_i,
+	input [inOutDataWidth-1:0] Data_i,
+	input DataNd_i,
+	output [inOutDataWidth-1:0] Data_o,
+	output DataValid_o
+);
+
+reg ndReg;
+reg	signed	[inOutDataWidth-1:0]	inReg;
+reg signed	[inOutDataWidth-1:0]	sumResult;
+reg	dataValid;
+reg	signed	[inOutDataWidth-1:0] delData	[M-1:0];
+
+	always	@(posedge Clk_i)	begin
+		if	(!Rst_i)	begin
+			ndReg <= DataNd_i;
+			if	(DataNd_i)	begin
+				inReg	<=	Data_i;
+			end
+		end	else	begin
+			ndReg	<=	0;
+			inReg	<=	0;
+		end
+	end
+
+genvar i;
+generate 
+	for (i=0; i<M; i=i+1)	begin:combGen
+		always	@(posedge	Clk_i)	begin
+			if	(i==0)	begin
+				delData	[i]	<=	inReg;
+			end	else	begin
+				delData	[i]	<=	delData[i-1];
+			end
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(ndReg)	begin
+				sumResult	<=	inReg+-delData[M-1];
+				dataValid	<=	1'b1;
+			end	else	begin
+				dataValid	<=	1'b0;
+			end
+		end	else	begin
+			sumResult	<=	0;
+			dataValid	<=	1'b0;
+		end
+	end
+endgenerate
+
+assign	Data_o	=	sumResult;
+assign	DataValid_o	=	dataValid;
+endmodule

src/src/FftDataFiltering/combFilterWrapper.v

@@ -0,0 +1,69 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    16:47:07 10/26/2020 
+// Design Name: 
+// Module Name:    intFilterWrapper 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module combFilterWrapper
+#(
+	parameter	M = 4,
+	parameter	filteredDataWidth	=	25,
+	parameter	inOutDataWidth	=	18
+)
+(
+	input Clk_i,
+	input Rst_i,
+	input [inOutDataWidth-1:0] Data_i,
+	input DataNd_i,
+	output [inOutDataWidth-1:0] Data_o,
+	output DataValid_o
+);
+
+	wire [filteredDataWidth-1:0] combOutData;
+	wire combOutDataValid;
+	
+	combFilterBlock 
+	#(	.M(M),
+		.filteredDataWidth	(filteredDataWidth),
+		.inOutDataWidth	(inOutDataWidth)
+	)
+	combFilterBlockInst
+	(
+		.Clk_i(Clk_i),
+		.Rst_i(Rst_i),
+		.Data_i(Data_i),
+		.DataNd_i(DataNd_i),
+		.Data_o(Data_o),
+		.DataValid_o(DataValid_o)
+	);
+	
+	
+	// roundSymmetric 
+	// #( 
+		// .inDataWidth(inOutDataWidth),
+		// .outDataWidth(inOutDataWidth)
+	// )
+	// combRoundInst
+	// (
+		// .Rst_i(1'b0),
+		// .Clk_i(Clk_i),
+		// .Data_i(combOutData),
+		// .DataNd_i(combOutDataValid),
+		// .Data_o(Data_o),
+		// .DataValid_o(DataValid_o)
+	// );
+endmodule

src/src/FftDataFiltering/decimBlock.v

@@ -0,0 +1,88 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    12:42:08 10/27/2020 
+// Design Name: 
+// Module Name:    decimBlock 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module decimBlock
+#(	
+	// parameter	R	=	2,
+	parameter	inOutDataWidth	=	18,
+	parameter	decimCntWidth	=	7
+)
+(
+	input Clk_i,
+	input Rst_i,
+	input [2:0]	DecimFactor_i,
+	input [inOutDataWidth-1:0] Data_i,
+	input DataNd_i,
+	output [inOutDataWidth-1:0] Data_o,
+	output DataValid_o
+);
+
+reg	[decimCntWidth-1:0]	decimCnt;
+reg	[inOutDataWidth-1:0]	dataReg;
+reg	valReg;
+
+reg	[2:0]	decimFactor;
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(DecimFactor_i	<=	3'd1)	begin
+			decimFactor	<=	3'd1;
+		end	else	begin
+			decimFactor	<=	DecimFactor_i;
+		end
+	end	else	begin
+		decimFactor	<=	3'd1;
+	end
+end
+
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(DataNd_i)	begin
+			if	(decimCnt	==	decimFactor-1)	begin
+				decimCnt	<=	{decimCntWidth{1'b0}};
+				valReg		<=	1'b1;
+			end	else	begin
+				decimCnt	<=	decimCnt+7'd1;
+				valReg		<=	1'b0;
+			end
+		end	else	begin
+			decimCnt	<=	{decimCntWidth{1'b0}};
+			valReg		<=	1'b0;
+		end
+	end	else	begin
+		decimCnt	<=	{decimCntWidth{1'b0}};
+		valReg		<=	1'b0;
+	end
+end
+	
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(decimCnt	==	decimFactor-1)	begin
+			dataReg	<=	Data_i;
+		end	
+	end	else	begin
+		dataReg	<=	0;
+	end
+end
+
+assign	Data_o	=	dataReg;
+assign	DataValid_o	=	valReg;
+endmodule

src/src/FftDataFiltering/intFilterBlock.v

@@ -0,0 +1,38 @@
+module intFilterBlock 
+#(	parameter	inOutDataWidth	=	18,
+	parameter	filteredDataWidth	=	25
+)
+(
+	input Clk_i,
+	input [inOutDataWidth-1:0] Data_i,
+	input DataNd_i,
+	output [filteredDataWidth-1:0] Data_o,
+	output DataValid_o
+);
+
+	reg [1:0] ndShReg;
+	
+	always @ (posedge Clk_i)
+		ndShReg <= {ndShReg[0:0], DataNd_i};
+	
+	reg signed [inOutDataWidth-1:0] inReg;
+	reg signed [filteredDataWidth-1:0] sumResult;
+	
+	always	@(posedge	Clk_i)	begin
+		if (DataNd_i)	begin
+			inReg <= Data_i;
+		end
+	end
+	
+	always @ (posedge Clk_i)	begin
+		if (ndShReg[0])	begin
+			sumResult <= inReg + sumResult;
+		end	else	begin
+			sumResult <= 0;
+		end
+	end
+
+	assign Data_o = sumResult;
+	assign DataValid_o = ndShReg[1];
+
+endmodule

src/src/FftDataFiltering/intFilterWrapper.v

@@ -0,0 +1,63 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    16:47:07 10/26/2020 
+// Design Name: 
+// Module Name:    intFilterWrapper 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module intFilterWrapper
+#(	parameter	filteredDataWidth	=	25,
+	parameter	inOutDataWidth	=	18
+)
+(
+	input Clk_i,
+	input [inOutDataWidth-1:0] Data_i,
+	input DataNd_i,
+	output [inOutDataWidth-1:0] Data_o,
+	output DataValid_o
+);
+
+	wire [filteredDataWidth-1:0] intOutData;
+	wire intOutDataValid;
+	
+	intFilterBlock 
+	#(	.inOutDataWidth	(inOutDataWidth),
+		.filteredDataWidth	(filteredDataWidth)
+	)
+	intFilterBlockInst
+	(
+		.Clk_i(Clk_i),
+		.Data_i(Data_i),
+		.DataNd_i(DataNd_i),
+		.Data_o(Data_o),
+		.DataValid_o(DataValid_o)
+	);
+	
+	// roundSymmetric 
+	// #( 
+		// .inDataWidth(filteredDataWidth),
+		// .outDataWidth(inOutDataWidth)
+	// )
+	// intRoundInst
+	// (
+		// .Rst_i(1'b0),
+		// .Clk_i(Clk_i),
+		// .Data_i(intOutData),
+		// .DataNd_i(intOutDataValid),
+		// .Data_o(Data_o),
+		// .DataValid_o(DataValid_o)
+	// );	
+endmodule

src/src/GainOverloadControl/GainControl.v

@@ -0,0 +1,172 @@
+`timescale 1ns / 1ps
+(* KEEP = "TRUE" *)
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 		Churbanov S.
+// 
+// Create Date:    15:24:31 08/20/2019 
+// Design Name: 
+// Module Name:    gain_master 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.02 - File Modified
+// Additional Comments: 16.09.2019 file modified in assotiate with task.
+//
+//////////////////////////////////////////////////////////////////////////////////
+module GainControl
+#(	
+	parameter	AdcNcoMultWidth	=	35,
+	parameter	ThresholdWidth	=	24,
+	parameter	AdcDataWidth	=	14,
+	parameter	MeasPeriod		=	32
+)	
+(
+	input	Rst_i,
+	input	Clk_i,	
+	input	StartMeas_i,
+	input	GainAutoEn_i,
+	
+	input	signed	[AdcNcoMultWidth-1:0]	AdcCos_i,
+	input	signed	[AdcNcoMultWidth-1:0]	AdcSin_i,
+	
+	input	[ThresholdWidth-1:0]	GainLowThreshold_i,
+	input	[ThresholdWidth-1:0]	GainHighThreshold_i,
+	
+	output	GainNewState_o,
+	output	SensEn_o,
+	output	MeasStart_o
+);
+
+//================================================================================
+//  LOCALPARAMS
+	localparam	CntWidth		=	32;
+	localparam	Delay			=	100;
+	localparam	AverageDelay	=	MeasPeriod+Delay-1;
+	localparam	SumWidth		=	AdcNcoMultWidth+6-1;
+//================================================================================
+//  REG/WIRE
+	reg		[CntWidth-1:0]	measCnt;
+	
+	reg		signed	[SumWidth-1:0]	adcSinSum;			
+	reg		signed	[SumWidth-1:0]	adcCosSum;	
+	
+	reg		measWind;
+	wire	measEnd	=	(measCnt==AverageDelay-1)&measWind;
+	
+	reg	gainNewStateR;
+	reg		gainNewState;
+	wire	sensEn	=	((gainNewStateR& (!gainNewState))|(!gainNewStateR&gainNewState));
+	
+	reg		signed	[SumWidth-1:0]	sinShifted;
+	reg		signed	[SumWidth-1:0]	cosShifted;
+	
+	wire	signed	[ThresholdWidth-5:0]		sinShiftedCut	=	sinShifted	[(SumWidth-1)-:20];		//width is 20
+	wire	signed	[ThresholdWidth-5:0]		cosShiftedCut	=	cosShifted	[(SumWidth-1)-:20];		//width is 20
+	
+	wire	signed	[(ThresholdWidth*2)-9:0]	sinSumSquared	=	(sinShiftedCut*sinShiftedCut);	// width is 40
+	wire	signed	[(ThresholdWidth*2)-9:0]	cosSumSquared	=	(cosShiftedCut*cosShiftedCut);	// width is 40
+	
+	wire	signed	[(ThresholdWidth*2)-9:0]	sumSquared	=	(cosSumSquared+sinSumSquared);	//width is 40	
+	
+	wire	[(ThresholdWidth*2)-9:0]	lowThresholdCompl	=	{10'b0,GainLowThreshold_i,6'b0};
+	wire	[(ThresholdWidth*2)-9:0]	highThresholdCompl	=	{10'b0,GainHighThreshold_i,6'b0};
+	
+	wire	accWind	=	(measCnt>0	&	measCnt	<=MeasPeriod-2);
+//================================================================================
+//  ASSIGNMENTS
+	assign	GainNewState_o	=	gainNewState;
+	assign	SensEn_o		=	sensEn;
+	assign	MeasStart_o		=	GainAutoEn_i?	measEnd:StartMeas_i;
+//================================================================================
+//  CODING
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(GainAutoEn_i)	begin
+			if	(StartMeas_i)	begin
+				measWind	<=	1'b1;
+			end	else	if	(measEnd)	begin
+				measWind	<=	1'b0;
+			end
+		end	else	begin
+			measWind	<=	1'b0;
+		end
+	end	else	begin
+		measWind	<=	1'b0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(measWind)	begin
+		if	(measCnt	==	MeasPeriod-2)	begin
+			sinShifted	<=	adcSinSum>>>2;
+			cosShifted	<=	adcCosSum>>>2;
+		end
+	end	
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(measWind)	begin
+			if	(measCnt	!= AverageDelay-1)	begin
+				measCnt	<=	measCnt	+	3'd1;	
+			end
+		end	else	begin
+			measCnt	<=	3'd0;
+		end
+	end	else	begin
+		measCnt	<=	3'd0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(!accWind)	begin
+			adcSinSum	<=	AdcSin_i;
+			adcCosSum	<=	AdcCos_i;
+		end	else	begin
+			adcSinSum	<=	adcSinSum	+	AdcSin_i;
+			adcCosSum	<=	adcCosSum	+	AdcCos_i;
+		end
+	end	else	begin
+		adcSinSum	<=	0;	
+		adcCosSum	<=	0;
+	end
+end
+
+
+always	@(posedge	Clk_i)	begin	
+	if	(!Rst_i)	begin
+		if	(GainAutoEn_i)	begin
+			if	(measCnt	==	MeasPeriod-1)	begin
+				if	(gainNewState)	begin
+					if	(sumSquared	>	highThresholdCompl)	begin
+						gainNewState	<=	1'b0;
+					end	else	begin
+						gainNewState	<=	gainNewState;
+					end
+				end	else	begin
+					if	(sumSquared	<	lowThresholdCompl)	begin
+						gainNewState	<=	1'b1;
+					end	else	begin
+						gainNewState	<=	gainNewState;
+					end
+				end
+			end
+		end	else	begin
+			gainNewState	<=	1'b0;
+		end
+	end	else	begin
+		gainNewState	<=	1'b0;
+	end
+	
+	gainNewStateR	<=	gainNewState;
+end
+
+endmodule

src/src/GainOverloadControl/GainControlWrapper.v

@@ -0,0 +1,105 @@
+`timescale 1ns / 1ps
+// (* use_dsp48	=	"yes"*)
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 		Churbanov S.
+// 
+// Create Date:    15:24:31 08/20/2019 
+// Design Name: 
+// Module Name:    gain_master 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.02 - File Modified
+// Additional Comments: 16.09.2019 file modified in assotiate with task.
+//
+//////////////////////////////////////////////////////////////////////////////////
+module GainControlWrapper
+#(	
+	parameter	AdcDataWidth		=	14,
+	parameter	ThresholdWidth		=	24,
+	parameter	PhIncWidth			=	32,
+	parameter	IfNcoOutWidth		=	18,
+	parameter	MeasPeriod			=	32
+)	
+(
+	input	Rst_i,
+	input	Clk_i,	
+	input	StartMeas_i,
+	
+	input	[IfNcoOutWidth-1:0]	NcoSin_i,
+	input	[IfNcoOutWidth-1:0]	NcoCos_i,
+	
+	input	[AdcDataWidth-1:0]		AdcData_i,
+	
+	input	[ThresholdWidth-1:0]	GainLowThreshold_i,
+	input	[ThresholdWidth-1:0]	GainHighThreshold_i,
+	input	GainAutoEn_i,
+	input	GainManualState_i,
+	
+	output	AmpEnNewState_o,
+	output	SensEn_o,
+	output	MeasStart_o
+);
+
+//================================================================================
+//  LOCALPARAM
+	localparam	MultDataWidth	=	36;
+	
+//================================================================================
+	wire	[MultDataWidth-1:0]	adcSin;
+	wire	[MultDataWidth-1:0]	adcCos;
+
+	wire	[MultDataWidth-1:0]	adcSinCut	=	adcSin	[MultDataWidth-1:0];
+	wire	[MultDataWidth-1:0]	adcCosCut	=	adcCos	[MultDataWidth-1:0];
+	wire	gainNewState;
+//================================================================================
+//  ASSIGNMENTS
+	assign	AmpEnNewState_o	=	(GainAutoEn_i)?	gainNewState:GainManualState_i;
+//================================================================================
+//  CODING
+
+MultModule		
+#(	
+	.AdcDataWidth	(AdcDataWidth),
+	.IfNcoOutWidth	(IfNcoOutWidth)
+)	
+Adc1Mult	
+(
+	.Rst_i		(Rst_i),
+	.Clk_i		(Clk_i),
+	.AdcData_i	(AdcData_i),
+	.Sin_i		(NcoSin_i),
+	.Cos_i		(NcoCos_i),
+	.AdcSin_o	(adcSin),
+	.AdcCos_o	(adcCos)
+);
+
+
+GainControl		
+#(	
+	.AdcNcoMultWidth	(MultDataWidth),
+	.ThresholdWidth		(ThresholdWidth),
+	.AdcDataWidth		(AdcDataWidth),
+	.MeasPeriod			(MeasPeriod)
+)
+GainMaster
+(
+	.Rst_i					(Rst_i),
+	.StartMeas_i			(StartMeas_i),
+	.GainAutoEn_i			(GainAutoEn_i),
+	.Clk_i					(Clk_i),
+	.AdcCos_i				(adcSin),
+	.AdcSin_i				(adcCos),
+	.GainLowThreshold_i		(GainLowThreshold_i),
+	.GainHighThreshold_i	(GainHighThreshold_i),
+	.GainNewState_o			(gainNewState),
+	.SensEn_o				(SensEn_o),
+	.MeasStart_o			(MeasStart_o)
+); 
+endmodule

src/src/GainOverloadControl/OverloadDetect.v

@@ -0,0 +1,101 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 		Churbanov S.
+// 
+// Create Date:    15:24:31 08/20/2019 
+// Design Name: 
+// Module Name:  
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.02 - File Modified
+// Additional Comments: 16.09.2019 file modified in assotiate with task.
+//
+//////////////////////////////////////////////////////////////////////////////////
+module OverloadDetect
+#(	
+	parameter	ThresholdWidth	=	24,
+	parameter	AdcDataWidth	=	14,
+	parameter	MeasPeriod		=	32
+)	
+(
+	input	Rst_i,
+	input	Clk_i,	
+	input	[AdcDataWidth-1:0]		AdcData_i,
+	input	[ThresholdWidth-1:0]	OverThreshold_i,
+	output	Overload_o
+);
+
+//================================================================================
+//  LOG2 FUNCTION
+	function integer Log2;
+	input integer value;
+		begin
+			Log2 = 0;
+			while (value > 1) begin
+				value   = value >> 1;
+				Log2    = Log2 + 1;
+			end
+			
+			if	((2**Log2)<MeasPeriod)	begin
+				Log2	=	Log2+1;
+			end	
+		end
+	endfunction
+//================================================================================
+//  LOCALPARAMS
+	localparam CntWidth	=	Log2(MeasPeriod);
+	localparam SumWidth	=	AdcDataWidth+CntWidth;
+//================================================================================
+//  REG/WIRE
+	reg		overloadReg;
+	reg		[CntWidth-1:0]	measCnt;		
+	
+	reg		[SumWidth-1:0]	adcSum;	
+	
+	wire	[AdcDataWidth-1:0]	absAdc	=	(AdcData_i[AdcDataWidth-1])?	(~AdcData_i + 1):AdcData_i;
+//================================================================================
+//  ASSIGNMENTS
+	assign	Overload_o	=	overloadReg;
+//================================================================================
+//  CODING
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(measCnt	!= MeasPeriod-1)	begin
+			measCnt	<=	measCnt	+	{{{CntWidth-1{1'b0}},1'b1}};	
+		end	else	begin
+			measCnt	<=	{CntWidth{1'b0}};
+		end
+	end	else	begin
+		measCnt	<=	{CntWidth{1'b0}};
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(measCnt==MeasPeriod-1)	begin
+			adcSum	<=	absAdc;	
+		end	else	begin
+			adcSum	<=	adcSum	+	absAdc;
+		end
+	end	else	begin
+		adcSum	<=	0;
+	end
+end
+	
+always	@(posedge	Clk_i)	begin
+	if	(measCnt	==	MeasPeriod-1)	begin
+		if	((adcSum>>CntWidth)	>	OverThreshold_i)	begin
+			overloadReg	<=	1'b1;
+		end	else	begin
+			overloadReg	<=	1'b0;
+		end
+	end
+end
+endmodule

src/src/InitRst/InitRst.v

@@ -0,0 +1,104 @@
+module InitRst (
+    clk_i,
+    signal_o
+);
+
+//================================================================================
+//
+//  FUNCTIONS
+//
+//================================================================================
+
+    function integer bit_num;
+        input integer value;
+        begin
+            bit_num = 0;
+            while (value > 0) begin
+                value   = value >> 1;
+                bit_num = bit_num + 1;
+            end
+        end
+    endfunction
+
+//================================================================================
+//
+//  PARAMETER/LOCALPARAM
+//
+//================================================================================
+
+    parameter   DELAY_VALUE     = 20;
+    localparam  DELAY_CNT_W     = bit_num(DELAY_VALUE);
+
+//================================================================================
+//
+//  PORTS
+//
+//================================================================================
+
+    input           clk_i;
+    output  reg     signal_o;
+
+//================================================================================
+//
+//  STATE MACHINE STATES
+//
+//================================================================================
+
+    localparam      SM_RST_S    = 1'b0;
+    localparam      SM_DONE_S   = 1'b1;
+
+//================================================================================
+//
+//  REG/WIRE
+//
+//================================================================================
+
+    reg                         curr_state  = SM_RST_S;
+    reg     [DELAY_CNT_W-1:0]   delay_cnt   = {DELAY_CNT_W{1'b0}};
+    reg                         delay_flag  = 1'b0;
+
+    reg                         next_state;
+    reg     [DELAY_CNT_W-1:0]   delay_cnt_next	=	{DELAY_CNT_W{1'b0}};
+    reg                         signal_next;
+
+//================================================================================
+//
+//  CODING
+//
+//================================================================================
+
+initial begin
+    curr_state  = SM_RST_S;
+    delay_cnt   = {DELAY_CNT_W{1'b0}};
+    signal_o    = 1'b1;
+    delay_flag  = 1'b0;
+end
+
+always @(posedge clk_i) begin
+    curr_state  <= next_state;
+    delay_cnt   <= delay_cnt_next;
+    signal_o    <= signal_next;
+    delay_flag  <= delay_cnt > (DELAY_VALUE - 1);
+end
+
+always @(*) begin
+    next_state      = SM_RST_S;
+    delay_cnt_next  = delay_cnt;
+    signal_next     = 1'b1;
+    case(curr_state)
+        SM_RST_S    : begin
+            if (delay_flag) begin
+                next_state      = SM_DONE_S;
+            end else begin
+                next_state      = SM_RST_S;
+                delay_cnt_next  = delay_cnt + {{(DELAY_CNT_W-1){1'b0}}, 1'b1};
+            end
+        end
+        SM_DONE_S   : begin
+            signal_next = 1'b0;
+            next_state  = SM_DONE_S;
+        end
+    endcase
+end
+
+endmodule

src/src/InternalDsp/AdcCalibration.v

@@ -0,0 +1,131 @@
+`timescale 1ns / 1ps
+(* keep_hierarchy = "yes" *)
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    14:12:30 06/03/2020 
+// Design Name: 
+// Module Name:    WinParameters 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: kek
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//18.01.2022	AdcData_I is 1.0.13 now changing to 1.2.17 for further calculation. The integer part added to avoid the overflow of the corrected data.
+//////////////////////////////////////////////////////////////////////////////////
+
+module AdcCalibration 
+#(	
+	parameter	AccNum			=	128,
+	parameter	AdcDataWidth	=	14
+)
+(	
+	input		Clk_i,
+	input		Rst_i,
+	input		CalModeEn_i,
+	input		[AdcDataWidth-1:0]	AdcData_i,
+	
+	output		CalDone_o,
+	output		[AdcDataWidth-1:0]	CalibratedAdcData_o
+);
+
+//================================================================================
+//  Func
+//================================================================================
+	function integer Log2;
+	input integer value;
+		begin
+			Log2 = 0;
+			while (value > 1) begin
+				value   = value >> 1;
+				Log2    = Log2 + 1;
+			end
+		end
+	endfunction
+	
+	localparam ShiftValue	= Log2(AccNum);
+	localparam AccWidth		= AdcDataWidth+ShiftValue;
+	
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	reg signed	[AccWidth:0]	adcAcc;
+	reg signed	[AdcDataWidth-1:0]	calValue;
+	reg signed	[AdcDataWidth-1:0]	calValueR;
+	reg [ShiftValue-1:0]	accCnt;
+	reg calDone;
+	
+	wire	[AccWidth:0]	adcDataCompl	=	{{ShiftValue+1{AdcData_i[AdcDataWidth-1]}},AdcData_i};
+	
+	wire	signed	[AdcDataWidth-1:0]	calibratedData	=	AdcData_i-calValue;
+	
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================	
+	assign	CalDone_o	=	calDone;
+	assign	CalibratedAdcData_o	=	calibratedData;
+//================================================================================
+//  CODING
+//================================================================================	
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(CalModeEn_i)	begin
+			if	(!calDone)	begin
+				accCnt	<=	accCnt+1;
+			end	else	begin
+				accCnt	<=	0;
+			end
+		end	else	begin
+			accCnt	<=	0;
+		end
+	end	else	begin
+		accCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(accCnt	==	AccNum-1)	begin
+			calDone	<=	1'b1;
+		end	else	begin
+			calDone	<=	1'b0;
+		end
+	end	else	begin
+		calDone	<=	1'b0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(CalModeEn_i)	begin
+			if	(!calDone)	begin
+				adcAcc	<=	adcAcc+adcDataCompl;
+			end	else	begin
+				adcAcc	<=	adcDataCompl;
+			end
+		end	else	begin
+			adcAcc	<=	adcDataCompl;
+		end
+	end	
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(calDone)	begin
+			calValue	<=	adcAcc>>ShiftValue;
+		end	
+	end	else	begin
+		calValue	<=	14'h0;
+	end
+end
+
+endmodule
+

src/src/InternalDsp/ComplPrng.v

@@ -0,0 +1,95 @@
+
+//////////////////////////////////////////////////////////////////////////////////
+// Company: NPK TAIR
+// Engineer: Mikhail Zaytsev
+// 
+// Create Date: 21.02.2023
+// Design Name: 
+// Module Name: ComplPrng
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: Pseudorandom number generator (PRNG) based on 
+//				Linear Feedback Shift Register (LFSR). Taus88
+//
+// Dependencies: None
+// 
+//////////////////////////////////////////////////////////////////////////////////
+module ComplPrng
+#(
+	parameter DataPrngWidth = 4,
+	parameter InDataWidth = 14,
+	parameter OutDataWidth = 20
+)
+(
+	// input [InDataWidth-1:0] Data_i,
+	input Clk_i,
+	input Rst_i,
+
+	// output signed	[OutDataWidth-1:0] DataAndPrng_o
+	output signed	[OutDataWidth-1:0] PrngData_o
+);
+//================================================================================
+//	REG/WIRE
+//================================================================================
+reg [31:0] s1;
+reg [31:0] s2;
+reg [31:0] s3;
+reg signed	[31:0] dataPrng;
+
+wire	signed	[OutDataWidth-1:0]	adcDataExtended;
+
+wire	signed	[DataPrngWidth-1:0]	dataPrngCut;
+// wire	signed	[OutDataWidth-1:0]	dataPrngCutExtended;
+reg		signed	[OutDataWidth-1:0]	dataPrngCutExtended;
+
+reg	signed	[OutDataWidth-1:0]	dataAndPrngReg;
+//================================================================================
+//	ASSIGNMENTS
+//================================================================================
+// assign	adcDataExtended		=	{Data_i[InDataWidth-1], Data_i[InDataWidth-1], Data_i, 4'b0};
+assign	dataPrngCut			=	dataPrng[31-:DataPrngWidth];
+// assign	dataPrngCutExtended	=	{{OutDataWidth-DataPrngWidth{dataPrngCut[DataPrngWidth-1]}}, dataPrngCut};
+// assign	DataAndPrng_o		=	adcDataExtended+dataPrngCutExtended;
+// assign	DataAndPrng_o		=	dataAndPrngReg;
+assign	PrngData_o			=	dataPrngCutExtended;
+//================================================================================
+//	CODING
+//================================================================================
+always @(posedge Clk_i) begin
+	if (Rst_i) begin
+		s1 <= 32'd12345;
+		s2 <= 32'd12345;
+		s3 <= 32'd12345;
+	end else begin
+		s1 <= (((s1 & 32'd4294967294) << 12) ^ (((s1 << 13) ^ s1) >> 19));
+		s2 <= (((s2 & 32'd4294967288) << 4) ^ (((s2 << 2) ^ s2) >> 25));
+		s3 <= (((s3 & 32'd4294967280) << 17) ^ (((s3 << 3) ^ s3) >> 11));
+	end
+end
+
+always @(posedge Clk_i) begin
+	if (Rst_i) begin
+		dataPrng <= 32'b0;
+	end else begin
+		dataPrng <= s1 ^ s2 ^ s3;
+	end
+end
+
+always @(posedge Clk_i) begin
+	if (Rst_i) begin
+		dataPrngCutExtended	<=	0;
+	end else begin
+		dataPrngCutExtended	<=	{{OutDataWidth-DataPrngWidth{dataPrngCut[DataPrngWidth-1]}}, dataPrngCut};
+	end
+end
+
+// always @(posedge Clk_i) begin
+	// if (Rst_i) begin
+		// dataAndPrngReg	<=	0;
+	// end else begin
+		// dataAndPrngReg	<=	Data_i+dataPrngCutExtended;
+	// end
+// end
+
+endmodule

src/src/InternalDsp/CordicNco.v

@@ -0,0 +1,246 @@
+/*
+    NCO module.
+    The module implements CORDIC algorithm
+*/
+
+module CordicNco 
+#(	parameter                   ODatWidth	= 18,
+	parameter                   PhIncWidth	= 32,
+	parameter                   IterNum		= 10,
+	parameter                   EnSinN		= 0,
+	parameter                   WinTypeW	= 0
+)
+(
+    input	Clk_i,
+    input	Rst_i,
+    input	Val_i,
+    input	[PhIncWidth-1:0]	PhaseInc_i,
+	input	[WinTypeW-1:0]	WinType_i,
+	input	WindVal_i,
+	output	[ODatWidth-1:0]	Wind_o,
+	output	[ODatWidth-1:0]	Sin_o,
+	output	[ODatWidth-1:0]	Cos_o,
+    output	reg	Val_o
+);
+
+//================================================================================
+//  FUNCTIONS
+//================================================================================
+    function integer log2;
+        input integer value;
+        begin
+            log2 = 0;
+            while (value > 1) begin
+                value   = value >> 1;
+                log2    = log2 + 1;
+            end
+        end
+    endfunction
+//================================================================================
+//  LOCALPARAMS
+//================================================================================
+	localparam  [PhIncWidth-1:0]	angle270	= 3<<(PhIncWidth-2);
+	localparam  [PhIncWidth-1:0]	angle180	= 1<<(PhIncWidth-1);
+	localparam  [PhIncWidth-1:0]	angle90		= 1<<(PhIncWidth-2);
+	
+	localparam [17:0] initValue = 18'd78498;
+//================================================================================
+//  REG/WIRE DECLARATIONS
+//================================================================================
+	
+    wire	[PhIncWidth-1:0]	precompAngle[ODatWidth-1:0];   
+    wire	[ODatWidth-1:0]		xPipe[IterNum:0];
+    wire	[ODatWidth-1:0]		yPipe[IterNum:0];
+    wire	[IterNum:0]			valPipe;
+    reg		[PhIncWidth-1:0]	phaseDiffPipe[IterNum-1:0];
+    reg		[2:0]				scwSignPipe[IterNum-1:0];
+
+    reg		[PhIncWidth-1:0]	phaseAcc;
+    reg     [PhIncWidth-1:0]	currPhase;
+    reg		[2:0]				scwSignPrev;
+    reg		[2:0]				scwSign;
+    reg		[2:0]				valSr;
+
+	reg		[ODatWidth-1:0]		sin_o;
+	reg		[ODatWidth-1:0]		cos_o;
+	reg		[ODatWidth-1:0]		wind_o;
+    genvar	g;
+    integer	i;
+	
+	reg		valR;
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+    assign	xPipe[0]	=	(Val_i)	?	initValue:xPipe[0];
+    assign	yPipe[0]	=	(Val_i)	?	initValue:yPipe[0];
+    assign	valPipe[0]	=	valSr[2];
+	assign	Wind_o		=	(WindVal_i&&WinType_i==0)	?	wind_o:14'b0;
+
+	assign precompAngle[0] = 32'd536870912;
+	assign precompAngle[1] = 32'd316933406;
+	assign precompAngle[2] = 32'd167458907;
+	assign precompAngle[3] = 32'd85004756;
+	assign precompAngle[4] = 32'd42667331;
+	assign precompAngle[5] = 32'd21354465;
+	assign precompAngle[6] = 32'd10679838;
+	assign precompAngle[7] = 32'd5340245;
+	assign precompAngle[8] = 32'd2670163;
+	assign precompAngle[9] = 32'd1335087;
+	assign precompAngle[10] = 32'd667544;
+	assign precompAngle[11] = 32'd333772;
+	assign precompAngle[12] = 32'd166886;
+	assign precompAngle[13] = 32'd83443;
+	assign precompAngle[14] = 32'd41722;
+	assign precompAngle[15] = 32'd20861;
+	assign precompAngle[16] = 32'd10430;
+	assign precompAngle[17] = 32'd5215;
+	//assign precompAngle[18] = 32'd2608;
+
+	assign	Sin_o	=	WindVal_i	?	sin_o	:	14'h0;
+	assign	Cos_o	=	WindVal_i	?	cos_o	:	14'h0;
+//================================================================================
+//  CODING
+//================================================================================
+always @(posedge Clk_i) begin
+    if (Rst_i) begin
+        valR	<=	1'b0;
+    end else begin
+		valR	<=	Val_i;
+	end
+end
+
+//  Phase handle logic
+always @(posedge Clk_i) begin
+    if (Rst_i) begin
+        phaseAcc   <= {PhIncWidth{1'b0}};
+    end else if (Val_i) begin
+        phaseAcc   <= phaseAcc + PhaseInc_i;
+    end	else	begin
+		phaseAcc   <= {PhIncWidth{1'b0}};
+	end
+end
+
+always @(posedge Clk_i) begin
+    if (Rst_i) begin
+        currPhase   <= {PhIncWidth{1'b0}};
+        scwSign         <= 3'b0;
+    end else begin
+        if (phaseAcc > angle270) begin
+            currPhase   <= {PhIncWidth{1'b0}} - phaseAcc;
+            scwSign         <= 3'b010;
+        end else if (phaseAcc > angle180) begin
+            currPhase   <= phaseAcc - angle180;
+            scwSign         <= 3'b011;
+        end else if (phaseAcc > angle90) begin
+            currPhase   <= angle180 - phaseAcc;
+            scwSign         <= 3'b001;
+        end else begin
+            currPhase   <= phaseAcc;
+            scwSign         <= 3'b000;
+        end
+    end
+end
+
+//--------------------------------------------------------------------------------
+//  CORDIC pipe
+
+always @(posedge Clk_i) begin
+    if (Rst_i) begin
+        valSr <= 3'b0;
+    end else if	(Val_i)	begin
+        valSr <= {valSr[1:0], Val_i};
+    end	else	begin
+		valSr <= 3'b0;
+	end
+end
+
+always @(posedge Clk_i) begin
+    phaseDiffPipe[0]  <= currPhase - precompAngle[0];
+    scwSignPipe[0]     <= scwSign;
+    for(i=1; i<IterNum; i=i+1) begin
+        scwSignPipe[i] <= scwSignPipe[i-1];
+        if (phaseDiffPipe[i-1][PhIncWidth-1]) begin
+            phaseDiffPipe[i] <= phaseDiffPipe[i-1] + precompAngle[i];
+        end else begin
+            phaseDiffPipe[i] <= phaseDiffPipe[i-1] - precompAngle[i];
+        end
+    end
+end
+
+generate
+    for (g = 0; g < IterNum; g = g + 1) begin : cordic_pipe
+        cordic_rotation #(
+            .ODatWidth	(ODatWidth),
+            .Shift      (g+1)
+        ) cordic_rotation_inst (
+            .Clk_i      (Clk_i),
+            .Rst_i      (Rst_i),
+			.X_i        (xPipe[g]),
+			.Y_i        (yPipe[g]),
+			.Val_i      (valPipe[g]),
+			.Sign_i     (phaseDiffPipe[g][PhIncWidth-1]),
+			.X_o        (xPipe[g+1]),
+			.Y_o        (yPipe[g+1]),
+			.Val_o      (valPipe[g+1])
+		);
+    end
+endgenerate
+
+//--------------------------------------------------------------------------------
+//  Output logic
+
+generate 
+    if (EnSinN) begin
+        always @(posedge Clk_i) begin
+            if (Rst_i) begin
+                sin_o       <= {ODatWidth{1'b0}};
+            end else begin
+                if (scwSignPrev[1]) begin
+                    sin_o   <=  yPipe[IterNum];
+                end else begin
+                    sin_o   <= ~yPipe[IterNum] + {{(ODatWidth-1){1'b0}}, 1'b1};
+                end
+            end
+        end
+    end else begin
+        always @(posedge Clk_i) begin
+            if (Rst_i) begin
+                sin_o       <= {ODatWidth{1'b0}};
+            end else begin
+				if (scwSignPrev[1]) begin
+					sin_o   <= ~yPipe[IterNum] + {{(ODatWidth-1){1'b0}}, 1'b1};
+				end else begin
+					sin_o   <=  yPipe[IterNum];
+				end
+            end
+        end
+		always @(posedge Clk_i) begin
+            if (Rst_i) begin
+                wind_o       <= {ODatWidth{1'b0}};
+            end else begin
+				if (scwSignPrev[2]) begin
+					wind_o   <= ~yPipe[IterNum] + {{(ODatWidth-1){1'b0}}, 1'b1};
+				end else begin
+					wind_o   <=  yPipe[IterNum];
+				end
+            end
+        end
+    end
+endgenerate
+
+always @(posedge Clk_i) begin
+    if (Rst_i) begin
+        cos_o		<= {ODatWidth{1'b0}};
+        scwSignPrev	<= 3'b0;
+        Val_o		<= 1'b0;
+    end else begin
+        if (scwSignPrev[0]) begin
+            cos_o	<= ~xPipe[IterNum] + {{(ODatWidth-1){1'b0}}, 1'b1};
+        end else begin
+            cos_o	<= xPipe[IterNum];
+        end
+		scwSignPrev	<= scwSignPipe[IterNum-1];
+		Val_o		<= valPipe[0];
+    end	
+end
+endmodule

src/src/InternalDsp/CordicRotation.v

@@ -0,0 +1,74 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:32:49 05/13/2020 
+// Design Name: 
+// Module Name:    cordic_rotation 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module cordic_rotation 
+#(	parameter   ODatWidth	= 16,
+	parameter   Shift		= 1)
+(
+	input	Clk_i,
+	input	Rst_i,
+
+	input	signed  [ODatWidth-1:0]	X_i,
+	input	signed  [ODatWidth-1:0]	Y_i,
+	input	Val_i,
+	input	Sign_i,
+	output	reg	signed	[ODatWidth-1:0]	X_o,
+	output	reg	signed	[ODatWidth-1:0]	Y_o,
+	output	reg	Val_o
+);
+//================================================================================
+//  REG/WIRE DECLARATIONS
+//================================================================================
+    wire    [ODatWidth-1:0]    shiftedInX;
+    wire    [ODatWidth-1:0]    shiftedInY;
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+    assign  shiftedInX    =   X_i >>> Shift;
+    assign  shiftedInY    =   Y_i >>> Shift;
+//================================================================================
+//  CODING
+//================================================================================
+always @(posedge Clk_i) begin
+    if (Rst_i) begin
+        Val_o	<= 1'b0;
+    end else if	(Val_i)	begin
+        Val_o	<= Val_i;
+    end	else	begin
+		Val_o	<=	1'b0;
+	end
+end
+
+always @(posedge Clk_i) begin
+    if (Rst_i) begin
+        X_o   <= {ODatWidth{1'b0}};
+        Y_o   <= {ODatWidth{1'b0}};
+    end else if (Val_i) begin
+        if (Sign_i) begin
+            X_o   <= X_i + shiftedInY;
+            Y_o   <= Y_i - shiftedInX; 
+        end else begin
+            X_o   <= X_i - shiftedInY;
+            Y_o   <= Y_i + shiftedInX;
+        end
+    end
+end
+
+endmodule

src/src/InternalDsp/DspPipeline.v

@@ -0,0 +1,288 @@
+
+(* keep_hierarchy = "yes" *)	
+module DspPipeline 
+#(	
+	parameter	AdcDataWidth		=	14,
+	parameter	AccWidth			=	48,
+	parameter	WindWidth			=	14,
+	parameter	AdcCorrData			=	20,
+	parameter	NcoWidth			=	14,
+	parameter	ResultWidth			=	32,
+	parameter	WindNormCoefWidth	=	32,
+	parameter	WindCorrCoefWidth	=	32,
+	parameter	IntermediateWidth	=	14,
+	parameter	FracWidth			=	51
+)
+(
+    input	Clk_i,
+    input	Rst_i,
+    input	Val_i,
+    input	StartFpConv_i,
+	
+	input	[WindCorrCoefWidth-1:0]	FilterCorrCoef_i,
+	input	[WindCorrCoefWidth-1:0]	AverageNoizeLvl_i,
+	input	[AdcCorrData-1:0]	AdcData_i,
+	input	[WindWidth-1:0]		Wind_i,
+	input	[NcoWidth-1:0]		NcoSin_i,
+	input	[NcoWidth-1:0]		NcoCos_i,
+	input	[WindNormCoefWidth-1:0]	NormCoef_i,
+	
+	output	[ResultWidth-1:0]	CorrResultIm_o,
+	output	[ResultWidth-1:0]	CorrResultRe_o,
+    output	CorrResultVal_o
+);
+
+//================================================================================
+//  LOCALPARAMS
+	localparam	NormResultWidth	=	AccWidth+WindNormCoefWidth;
+	localparam	AdcWindWidth	=	37;
+//================================================================================
+//  REG/WIRE 
+	wire	[AdcWindWidth-1:0]	adcWindResult;
+	wire	adcWindResultVal;
+	
+	wire	[54:0]	adcWindSinResult;
+	wire	adcWindSinResultVal;
+	wire	[54:0]	adcWindCosResult;
+	wire	adcWindCosResultVal;
+	
+	wire	[AccWidth-1:0]	AccResultI;
+	wire	[AccWidth-1:0]	AccResultQ;
+	
+	wire	[ResultWidth-1:0]	NormResultI;
+	wire	NormResultIVal;
+	wire	[ResultWidth-1:0]	NormResultQ;
+	wire	NormResultQVal;
+	
+	wire	[ResultWidth-1:0]	iFp32Result;
+	wire	iFp32ResultVal;
+	wire	[ResultWidth-1:0]	qFp32Result;
+	wire	qFp32ResultVal;
+	
+	wire	CorrResultReVal;
+	wire	CorrResultImVal;
+	
+	reg		valReg;
+	reg		valRegReg;
+//================================================================================
+//  ASSIGNMENTS
+	assign	CorrResultVal_o	=	CorrResultReVal&CorrResultImVal;
+	
+//================================================================================
+//  CODING
+
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			valReg		<=	Val_i;
+			valRegReg	<=	valReg;
+		end	else	begin
+			valReg		<=	0;
+			valRegReg	<=	0;	
+		end
+	end
+	
+//===============================Adc*Wind=========================================
+SimpleMult	
+#(	
+	.FactorAWidth	(AdcCorrData),
+	.FactorBWidth	(WindWidth),
+	.OutputWidth	(AdcWindWidth)
+)
+AdcWindMult	
+(
+	.Rst_i		(Rst_i),
+	.Clk_i		(Clk_i),
+	.Val_i		(valRegReg),
+	.FactorA_i	(AdcData_i),
+	.FactorB_i	(Wind_i),
+	.Result_o	(adcWindResult),
+	.ResultVal_o(adcWindResultVal)
+);
+//===============================AdcWind*NcoSinCos================================
+SimpleMult	
+#(	
+	.FactorAWidth	(AdcWindWidth),
+	.FactorBWidth	(NcoWidth),
+	.OutputWidth	(NcoWidth+AdcWindWidth)
+)
+AdcNcoSinMult	
+(
+	.Rst_i		(Rst_i),
+	.Clk_i		(Clk_i),
+	.Val_i		(adcWindResultVal),
+	.FactorA_i	(adcWindResult),
+	.FactorB_i	(NcoSin_i),	
+	.Result_o	(adcWindSinResult),
+	.ResultVal_o(adcWindSinResultVal)
+);
+
+SimpleMult	
+#(	
+	.FactorAWidth	(AdcWindWidth),
+	.FactorBWidth	(NcoWidth),
+	.OutputWidth	(NcoWidth+AdcWindWidth)
+)
+AdcNcoCosMult	
+(
+	.Rst_i		(Rst_i),
+	.Clk_i		(Clk_i),
+	.Val_i		(adcWindResultVal),
+	.FactorA_i	(adcWindResult),
+	.FactorB_i	(NcoCos_i),
+	.Result_o	(adcWindCosResult),
+	.ResultVal_o(adcWindCosResultVal)
+);
+
+//===============================SumAcc===========================================
+SumAcc
+#(	
+	.IDataWidth	(NcoWidth+AdcWindWidth-1),
+	.ODataWidth	(AccWidth)
+)
+SummAccQ
+(
+    .Clk_i		(Clk_i),
+    .Rst_i		(Rst_i),
+    .Val_i		(adcWindSinResultVal),
+	
+	.Data_i		(adcWindSinResult[53:0]),
+	.Result_o	(AccResultQ)
+);
+
+SumAcc
+#(	
+	.IDataWidth	(NcoWidth+AdcWindWidth-1),
+	.ODataWidth	(AccWidth)
+)
+SummAccI
+(
+    .Clk_i		(Clk_i),
+    .Rst_i		(Rst_i),
+    .Val_i		(adcWindCosResultVal),
+	
+	.Data_i		(adcWindCosResult[53:0]),
+	.Result_o	(AccResultI)
+);
+
+//===============================InToFpConv=======================================
+MyIntToFp
+#(	
+	.InWidth	(AccWidth),
+	.ExpWidth	(8),
+	.ManWidth	(23),
+	.FracWidth	(FracWidth)
+)
+QToFp32
+(	
+	.Clk_i				(Clk_i),
+	.Rst_i				(Rst_i),
+	.InData_i			(AccResultQ),
+	.AverageNoizeLvl_i	(AverageNoizeLvl_i),
+	.InDataVal_i		(StartFpConv_i),
+	.OutData_o			(qFp32Result),
+	.OutDataVal_o		(qFp32ResultVal)
+);
+
+MyIntToFp
+#(	
+	.InWidth	(AccWidth),
+	.ExpWidth	(8),
+	.ManWidth	(23),
+	.FracWidth	(FracWidth)
+)
+IToFp32
+(	
+	.Clk_i				(Clk_i),
+	.Rst_i				(Rst_i),
+	.InData_i			(AccResultI),
+	.AverageNoizeLvl_i	(AverageNoizeLvl_i),
+	.InDataVal_i		(StartFpConv_i),
+	.OutData_o			(iFp32Result),
+	.OutDataVal_o		(iFp32ResultVal)
+);
+
+//===============================Result*NormCoeff=================================
+FpCustomMultiplier 
+# (
+	.ManWidth	(23),
+	.ExpWidth	(8)
+)
+ResultQNorm
+(
+	.Rst_i			(Rst_i),
+	.Clk_i			(Clk_i),
+	.A_i			(qFp32Result),
+	.B_i			(NormCoef_i),
+	.Nd_i			(qFp32ResultVal),
+	.Result_o		(NormResultQ),
+	.ResultValid_o	(NormResultQVal)
+);
+
+FpCustomMultiplier 
+# (
+	.ManWidth	(23),
+	.ExpWidth	(8)
+)
+ResultINorm
+(
+	.Rst_i			(Rst_i),
+	.Clk_i			(Clk_i),
+	.A_i			(iFp32Result),
+	.B_i			(NormCoef_i),
+	.Nd_i			(iFp32ResultVal),
+	.Result_o		(NormResultI),
+	.ResultValid_o	(NormResultIVal)
+);
+
+//===============================NormResult*CorrCoeff========================
+FpCustomMultiplier 
+# (
+	.ManWidth	(23),
+	.ExpWidth	(8)
+)
+ResultReCorr
+(
+	.Rst_i			(Rst_i),
+	.Clk_i			(Clk_i),
+	.A_i			(NormResultQ),
+	.B_i			(FilterCorrCoef_i),
+	.Nd_i			(NormResultQVal),
+	.Result_o		(CorrResultRe_o),
+	.ResultValid_o	(CorrResultReVal)
+);
+
+FpCustomMultiplier 
+# (
+	.ManWidth	(23),
+	.ExpWidth	(8)
+)
+ResultImCorr
+(
+	.Rst_i			(Rst_i),
+	.Clk_i			(Clk_i),
+	.A_i			(NormResultI),
+	.B_i			(FilterCorrCoef_i),
+	.Nd_i			(NormResultIVal),
+	.Result_o		(CorrResultIm_o),
+	.ResultValid_o	(CorrResultImVal)
+);
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

src/src/InternalDsp/InternalDsp.v

@@ -0,0 +1,409 @@
+`timescale 1ns / 1ps
+(* keep_hierarchy = "yes" *)
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    18:00:25 07/10/2019 
+// Design Name: 
+// Module Name:    internal_dsp 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module InternalDsp	
+#(	
+	parameter	AdcDataWidth		=	14,	
+	parameter	WindWidth			=	18,
+	parameter	WindNcoPhIncWidth	=	32,
+	parameter	NcoWidth			=	18,
+	parameter	ChNum				=	4,
+	parameter	ResultWidth			=	32,
+	parameter	WinTypeWidth		=	3,
+	parameter	BandCmdWidth		=	8,
+	parameter	WindPNumWidth		=	32,
+	parameter	WindNormCoefWidth	=	32,
+	parameter	WindCorrCoefWidth	=	32,
+	parameter	CmdDataRegWith		=	24,
+	parameter	IntermediateWidth	=	18,
+	parameter	CorrAdcDataWidth	=	20,
+	parameter	AccWidth			=	80
+)
+(
+	input	wire	Clk_i,
+	input	wire	WindCalcClk_i,
+	input	wire	Rst_i,
+	input	wire	NcoRst_i,
+	output	wire	OscWind_o,
+	
+	input	wire	[AdcDataWidth-1:0]	Adc1ChT1Data_i,	//A
+	input	wire	[AdcDataWidth-1:0]	Adc1ChR1Data_i,	//R1
+	input	wire	[AdcDataWidth-1:0]	Adc2ChR2Data_i,	//R2
+	input	wire	[AdcDataWidth-1:0]	Adc2ChT2Data_i,	//B	
+	
+	input	wire	GatingPulse_i,
+	
+	input	wire	StartMeas_i,
+	input	wire	StartMeasDsp_i,
+	input	wire	OscDataRdFlag_i,
+	
+	input	wire	[32-1:0]	MeasNum_i,
+	
+	input	wire	[CmdDataRegWith-1:0]	MeasCtrl_i,
+	input	wire	[CmdDataRegWith-1:0]	FilterCorrCoefL_i,
+	input	wire	[CmdDataRegWith-1:0]	FilterCorrCoefH_i,
+	
+	output	wire	EndMeas_o,
+	
+	input	wire	CalModeEn_i,
+	output	wire	CalModeDone_o,
+
+	input	wire	[CmdDataRegWith-1:0]	IfFtwL_i,
+	input	wire	[CmdDataRegWith-1:0]	IfFtwH_i,
+	
+	output	wire	[ResultWidth-1:0]	Adc1ImT1Data_o,
+	output	wire	[ResultWidth-1:0]	Adc1ReT1Data_o,
+	output	wire	[ResultWidth-1:0]	Adc1ImR1Data_o,
+	output	wire	[ResultWidth-1:0]	Adc1ReR1Data_o,
+	//adc2                 
+	output	wire	[ResultWidth-1:0]	Adc2ImR2Data_o,
+	output	wire	[ResultWidth-1:0]	Adc2ReR2Data_o,
+	output	wire	[ResultWidth-1:0]	Adc2ImT2Data_o,
+	output	wire	[ResultWidth-1:0]	Adc2ReT2Data_o,
+	
+	output	wire	[NcoWidth-1:0]	NcoSin_o,
+	output	wire	[NcoWidth-1:0]	NcoCos_o,
+	
+	output	wire	MeasDataRdy_o,
+	output	wire	MeasWind_o,
+	output	wire	MeasEnd_o,
+	output	wire	SampleStrobeGenRst_o
+);
+
+//================================================================================
+//  REG/WIRE
+	wire	[WindNormCoefWidth-1:0]	windNormCoef;
+	wire	[WindPNumWidth-1:0]		windPointsNum;
+	wire	[WindPNumWidth-1:0]		averageNoizeLvl;
+	wire	[WindNcoPhIncWidth-1:0]	windPhInc;
+	wire	[WindNcoPhIncWidth-1:0]	winPhIncStart;
+	
+	wire	[WindWidth-1:0]	wind;			
+
+	wire	[NcoWidth-1:0]	ncoCos;
+	wire	[NcoWidth-1:0]	ncoSin;
+	
+	wire	[CorrAdcDataWidth-1:0]	adcDataBus	[ChNum-1:0];
+	wire	[CorrAdcDataWidth-1:0]	adcDataBusExt	[ChNum-1:0];
+	wire	[CorrAdcDataWidth-1:0]	gatedAdcDataBus	[ChNum-1:0];
+	wire	[CorrAdcDataWidth-1:0]	calAdcData		[ChNum-1:0];
+	wire	[CorrAdcDataWidth-1:0]	prngData;
+	reg		[CorrAdcDataWidth-1:0]	prngDataBus		[ChNum-1:0];
+	wire	[ChNum-1:0]	calDone;
+	
+	genvar g;
+	integer i;
+	
+	wire	[ResultWidth-1:0]	resultImBus		[ChNum-1:0];
+	wire	[ResultWidth-1:0]	resultReBus		[ChNum-1:0];
+	wire	[ChNum-1:0]	resultValBus;
+	
+	wire	measWind;
+	wire	measWindDelayed;
+	wire	stopMeas;
+	wire	[1:0]	tukeyCtrl;
+	
+	reg		[CmdDataRegWith-1:0]	measCtrlReg;
+	reg		[32-1:0]	windPointsNumReg;
+	reg		[32-1:0]	measNumReg;
+	reg		[WindCorrCoefWidth-1:0]	filterCorrCoeffReg;
+	reg		[CmdDataRegWith-1:0]	ifFtwLReg;
+	reg		[CmdDataRegWith-1:0]	ifFtwHReg;
+	reg		[CmdDataRegWith-1:0]	filterCorrCoefLReg;
+	reg		[CmdDataRegWith-1:0]	filterCorrCoefHReg;
+	
+	wire	[31:0]	windArg;
+	
+	wire	[CorrAdcDataWidth-1:0]	adc1ChT1DataGated	=	(GatingPulse_i)?	adcDataBusExt[ChNum-4]:{CorrAdcDataWidth{1'b0}};
+	wire	[CorrAdcDataWidth-1:0]	adc1ChR1DataGated	=	(GatingPulse_i)?	adcDataBusExt[ChNum-3]:{CorrAdcDataWidth{1'b0}};
+	wire	[CorrAdcDataWidth-1:0]	adc2ChR2DataGated	=	(GatingPulse_i)?	adcDataBusExt[ChNum-2]:{CorrAdcDataWidth{1'b0}};
+	wire	[CorrAdcDataWidth-1:0]	adc2ChT2DataGated	=	(GatingPulse_i)?	adcDataBusExt[ChNum-1]:{CorrAdcDataWidth{1'b0}};	
+	
+	wire	[WindNcoPhIncWidth-1:0]	ncoPhInc = {ifFtwHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],ifFtwLReg};
+	
+//================================================================================
+//  ASSIGNMENTS
+
+	assign	adcDataBus	[ChNum-1]	=	{{2{Adc2ChT2Data_i[AdcDataWidth-1]}},Adc2ChT2Data_i,4'b0};
+	assign	adcDataBus	[ChNum-2]	=	{{2{Adc2ChR2Data_i[AdcDataWidth-1]}},Adc2ChR2Data_i,4'b0};
+	assign	adcDataBus	[ChNum-3]	=	{{2{Adc1ChR1Data_i[AdcDataWidth-1]}},Adc1ChR1Data_i,4'b0};
+	assign	adcDataBus	[ChNum-4]	=	{{2{Adc1ChT1Data_i[AdcDataWidth-1]}},Adc1ChT1Data_i,4'b0};
+	
+	assign	adcDataBusExt	[ChNum-1]	=	calAdcData	[ChNum-1]+prngDataBus[ChNum-1];
+	assign	adcDataBusExt	[ChNum-2]	=	calAdcData	[ChNum-2]+prngDataBus[ChNum-2];
+	assign	adcDataBusExt	[ChNum-3]	=	calAdcData	[ChNum-3]+prngDataBus[ChNum-3];
+	assign	adcDataBusExt	[ChNum-4]	=	calAdcData	[ChNum-4]+prngDataBus[ChNum-4];
+	
+	assign	gatedAdcDataBus	[ChNum-1]	=	adc2ChT2DataGated;
+	assign	gatedAdcDataBus	[ChNum-2]	=	adc2ChR2DataGated;
+	assign	gatedAdcDataBus	[ChNum-3]	=	adc1ChR1DataGated;
+	assign	gatedAdcDataBus	[ChNum-4]	=	adc1ChT1DataGated;
+	
+	assign	Adc1ImT1Data_o	=	resultImBus	[ChNum-4];
+	assign	Adc1ReT1Data_o	=	resultReBus	[ChNum-4];
+	assign	Adc1ImR1Data_o	=	resultImBus	[ChNum-3];
+	assign	Adc1ReR1Data_o	=	resultReBus	[ChNum-3];
+	//adc2                 
+	assign	Adc2ImR2Data_o	=	resultImBus	[ChNum-2];
+	assign	Adc2ReR2Data_o	=	resultReBus	[ChNum-2];
+	assign	Adc2ImT2Data_o	=	resultImBus	[ChNum-1];
+	assign	Adc2ReT2Data_o	=	resultReBus	[ChNum-1];
+	
+	
+	assign	MeasDataRdy_o	=	&resultValBus;
+	assign	EndMeas_o		=	stopMeas;
+	
+	assign	NcoCos_o	=	ncoCos;
+	assign	NcoSin_o	=	ncoSin;
+	assign	MeasWind_o	=	measWind;
+	
+	assign	CalModeDone_o	=	&calDone;
+	
+//================================================================================
+//  INSTANTIATIONS
+
+//----------------------------------------------
+//Module generates event signals for measurement
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(!StartMeas_i)	begin
+			measCtrlReg			<=	MeasCtrl_i;
+			ifFtwLReg			<=	IfFtwL_i;
+			ifFtwHReg			<=	IfFtwH_i;
+			filterCorrCoefLReg	<=	FilterCorrCoefL_i;
+			filterCorrCoefHReg	<=	FilterCorrCoefH_i;
+			measNumReg			<=	MeasNum_i;
+			windPointsNumReg	<=	windPointsNum;
+		end 
+	end	else	begin
+		measCtrlReg			<=	0;
+		ifFtwLReg			<=	0;
+		ifFtwHReg			<=	0;
+		filterCorrCoefLReg	<=	0;
+		filterCorrCoefHReg	<=	0;
+		measNumReg			<=	0;
+		windPointsNumReg	<=	0;
+	end 
+end
+
+MeasCtrlModule	
+#(	
+	.WindPNumWidth	(WindPNumWidth)
+)
+MeasCtrlModule	
+(
+	.Clk_i					(Clk_i),
+	.Rst_i					(Rst_i),
+	.OscWind_o				(OscWind_o),
+	.FilterCmd_i			(measCtrlReg[15-:8]),
+		
+	.MeasNum_i				(measNumReg),
+	.StartMeas_i			(StartMeas_i),
+	.StartMeasDsp_i			(StartMeasDsp_i),
+	.Mode_i					(measCtrlReg[0]),
+	.OscDataRdFlag_i		(OscDataRdFlag_i),
+		
+	.WindPointsNum_i		(windPointsNumReg),
+		
+	.WindPhInc_i			(windPhInc),
+	.WindPhIncStart_i		(winPhIncStart),
+	.WindArg_o				(windArg),
+		
+	.StartFpConv_o			(StartFpConv),
+	.MeasWind_o				(measWind),
+	.MeasWindDel_o			(measWindDelayed),
+	.StopMeas_o				(stopMeas),
+	.MeasEnd_o				(MeasEnd_o),
+	.WinCtrl_o				(winCtrl),
+	.TukeyCtrl_o			(tukeyCtrl),
+	.SampleStrobeGenRst_o	(SampleStrobeGenRst_o)
+);	
+
+//----------------------------------------------
+//Module selects settings for current window
+WinParameters 
+#(	
+	.WindPhIncWidth		(WindNcoPhIncWidth),
+	.WindNormCoefWidth	(WindNormCoefWidth),
+	.WindPNumWidth		(WindPNumWidth),
+	.BandCmdWidth		(BandCmdWidth)
+)
+WinParameters
+(	
+	.Clk_i				(Clk_i),
+	.Rst_i				(Rst_i),
+	.FilterCmd_i		(measCtrlReg[15-:8]),
+	.WinPhInc_o			(windPhInc),
+	.WinPhIncStart_o	(winPhIncStart),
+	.WinNormCoef_o		(windNormCoef),
+	.WinPointsNum_o		(windPointsNum),
+	.AverageNoiseLvl_o	(averageNoizeLvl)
+);
+
+//----------------------------------------------
+//Module generates win samples
+Win_calc	WinCalcInst
+(
+	.clk_i			(Clk_i),
+	.wind_clk		(WindCalcClk_i),
+	.filterCmd_i	(measCtrlReg[15-:8]),
+	.reset_i		(Rst_i),
+	.WinCtrl_i		(winCtrl),
+	.TukeyCtrl_i	(tukeyCtrl),
+	.MeasWind_i		(measWind),
+	.win_value_i	(windArg),
+	.win_type_i		(measCtrlReg[2:0]),
+	.win_o			(wind)
+);
+
+// Approximation3 WindCalc2
+// (
+    // .Clk_i			(Clk_i), 
+    // .Rst_i			(Rst_i),
+    // .Clk100_i		(WindCalcClk_i),
+    // .WinCtrl_i		(winCtrl),
+    // .Win_value_i	(windArg),
+    // .filterCmd_i	(measCtrlReg[15-:8]), 
+	// .Win_o			(wind)
+// );
+
+
+//----------------------------------------------
+//Module generates Sin and Cos for measurement
+
+CordicNco		
+#(	
+	.ODatWidth	(NcoWidth),
+	.PhIncWidth	(WindNcoPhIncWidth),
+	.IterNum	(15),
+	.EnSinN		(0)
+)
+ncoInst
+(
+	.Clk_i		(Clk_i),
+	.Rst_i		(Rst_i|NcoRst_i),
+	.Val_i		(1'b1),
+	.PhaseInc_i	({ifFtwHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],ifFtwLReg}),
+	.WindVal_i	(1'b1),
+	.WinType_i	(),
+	.Wind_o		(),
+	.Sin_o		(ncoSin),
+	.Cos_o		(ncoCos),	
+	.Val_o		()
+);
+
+ComplPrng
+#(
+	.DataPrngWidth	(8),
+	.InDataWidth 	(CorrAdcDataWidth),
+	.OutDataWidth	(CorrAdcDataWidth)
+)
+ComplPrngAdderInst
+(
+	.Clk_i	(Clk_i),
+	.Rst_i	(Rst_i),
+
+	.PrngData_o		(prngData)
+);
+
+always @(posedge Clk_i) begin
+	prngDataBus[0]  <= prngData;
+	for(i=1; i<4; i=i+1) begin
+		prngDataBus	[i]<=prngDataBus[i-1];
+	end
+end
+//------------------------------------------------
+//Generating needed amount of calculating channels
+generate
+	for	(g=0;	g<ChNum;	g=g+1)	begin	:DspChannel
+	
+		AdcCalibration 
+		#(	
+			.AccNum			(2097152),
+			.AdcDataWidth	(CorrAdcDataWidth)
+		)
+		AdcCalibrationInst
+		(	
+			.Clk_i					(Clk_i),
+			.Rst_i					(Rst_i),
+			.CalModeEn_i			(CalModeEn_i),
+			.AdcData_i				(adcDataBus[g]),
+			
+			.CalDone_o				(calDone[g]),
+			.CalibratedAdcData_o	(calAdcData[g])
+		);
+		
+		DspPipeline	
+		#(	
+			.AdcDataWidth		(AdcDataWidth),
+			.AccWidth			(AccWidth),
+			.WindWidth			(WindWidth),
+			.NcoWidth			(NcoWidth),
+			.ResultWidth		(ResultWidth),
+			.WindCorrCoefWidth	(WindCorrCoefWidth),
+			.WindNormCoefWidth	(WindNormCoefWidth),
+			.IntermediateWidth	(IntermediateWidth)
+		)
+		DspPipelineInst
+		(
+			.Clk_i				(Clk_i),
+			.Rst_i				(Rst_i),
+			.Val_i				(measWind),
+			.StartFpConv_i		(StartFpConv),
+			
+			.FilterCorrCoef_i	({filterCorrCoefHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],filterCorrCoefLReg}),
+			// .FilterCorrCoef_i	(32'h3f800000),
+			.AverageNoizeLvl_i	(averageNoizeLvl),
+			.AdcData_i			(gatedAdcDataBus[g]),
+			// .AdcData_i			({{2{ncoCos[17]}},ncoCos}),
+			.Wind_i				(wind),
+			.NcoSin_i			(ncoSin),
+			.NcoCos_i			(ncoCos),	
+			.NormCoef_i			(windNormCoef),
+			// .NormCoef_i			(32'h3f800000),
+			// .NormCoef_i			(32'h3f03993a),
+
+			.CorrResultIm_o		(resultImBus[g]),
+			.CorrResultRe_o		(resultReBus[g]),
+			.CorrResultVal_o	(resultValBus[g])
+		);
+	end
+endgenerate
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

src/src/InternalDsp/MeasCtrlModule.v

@@ -0,0 +1,348 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    14:22:41 09/18/2019 
+// Design Name: 
+// Module Name:    MeasCtrlModule 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module MeasCtrlModule
+#(	
+	parameter	WindPNumWidth	=	48,
+	localparam	TukeyWinAlpha	=	4
+)
+(
+	input	Clk_i,
+	input	Rst_i,
+	output	OscWind_o,
+	
+	input	StartMeas_i,
+	input	StartMeasDsp_i,
+	input	[7:0]	FilterCmd_i,
+	input	Mode_i,
+	input	OscDataRdFlag_i,
+	
+	input	[32-1:0]	MeasNum_i,
+
+	input	[WindPNumWidth-1:0]	WindPointsNum_i,
+	
+	input	[32-1:0]	WindPhInc_i,
+	input	[32-1:0]	WindPhIncStart_i,
+	output	[32-1:0]	WindArg_o,
+	
+	output	StartFpConv_o,
+	output	MeasWind_o,
+	output	MeasWindDel_o,
+	output	StopMeas_o,
+	output	MeasEnd_o,
+	output	WinCtrl_o,
+	output	SampleStrobeGenRst_o,
+	output	[1:0]	TukeyCtrl_o
+);
+
+
+//================================================================================
+//  REG/WIRE
+	reg	startFpConv;
+
+	reg	[1:0]	startFpConvPipe	[3:0];
+	integer i;
+
+	reg		measWind;
+	reg		measWindR;
+	
+	reg		startMeasReg;										
+	reg		startMeasDspReg;										
+	wire	startMeasCmd	=	(StartMeas_i		&	!startMeasReg);	//esli prihodit bol'she chem 1 sigtal zapuska na 1 izmerenie, to ostal'nie ignoriruutsya
+	wire	stopMeasCmd		=	(!StartMeasDsp_i	&	startMeasDspReg);
+	wire	startMeasDspPos	=	(StartMeasDsp_i		&	!startMeasDspReg);
+	
+	reg		[31:0]	measCnt;
+	
+	reg		[WindPNumWidth-1:0]	pNumCnt;
+
+	reg		measWindEnd;
+	reg		pMeasEnd;
+	wire	pNumCntRes		=	!measWind;
+	wire	measCntRes		=	pMeasEnd|!StartMeasDsp_i;
+	
+	wire	stopCalc		=	(stopMeasCmd|measWindEnd);
+
+	reg		[32-1:0]	windArg;
+	
+	wire	oscMode	=	(Mode_i	==	1'b1);
+	
+	reg		oscWind;
+	
+	wire	[31:0]	tukeyCosPNum = WindPointsNum_i/TukeyWinAlpha;
+	
+	wire	[31:0]	tukeyCosPNumDiv2			=	tukeyCosPNum/2;
+	wire	[31:0]	tukeyFirstCosValues			=	tukeyCosPNum/2;
+	wire	[31:0]	tukeyFirstCosValuesDiv2		=	tukeyFirstCosValues/2;
+	wire	[31:0]	tukeySecondCosValuesDiv2	=	(WindPointsNum_i-tukeyFirstCosValuesDiv2);
+	wire	[31:0]	tukeySecondCosValues		=	(WindPointsNum_i-tukeyCosPNum/2);
+
+	reg		[1:0]	tukeyCtrl;
+	reg		[1:0]	tukeyCtrlR;
+	reg		[1:0]	tukeyCtrlRR;
+
+	
+	wire	incPhase	=	(pNumCnt	<=	tukeyFirstCosValues);
+	wire	decrPhase	=	(pNumCnt	>=	tukeySecondCosValues-1	&	pNumCnt	<=	WindPointsNum_i-1);
+	
+	wire	wideFilterFlag	=	(FilterCmd_i>=8'h54	&	FilterCmd_i!=8'h70);
+	
+	reg		sampleStrobeGenRst;
+//================================================================================
+//  ASSIGNMENTS
+	assign	StartFpConv_o			=	startFpConvPipe	[2];
+	assign	MeasWind_o				=	measWind;
+	assign	MeasWindDel_o			=	measWindR;
+	assign	StopMeas_o				=	pMeasEnd;
+	assign	MeasEnd_o				=	stopMeasCmd;
+	assign	WindArg_o				=	windArg;
+	assign	OscWind_o				=	oscWind;
+	assign	TukeyCtrl_o				=	tukeyCtrl;
+	assign	WinCtrl_o				=	(pNumCnt<=tukeyFirstCosValuesDiv2+1|pNumCnt>tukeySecondCosValuesDiv2);
+	assign	SampleStrobeGenRst_o	=	sampleStrobeGenRst;
+//================================================================================
+//  CODING
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(measCnt	==	MeasNum_i-1	&	measWind)	begin
+				sampleStrobeGenRst	<=	1'b1;
+			end	else	begin
+				sampleStrobeGenRst	<=	1'b0;
+			end
+		end	else	begin
+			sampleStrobeGenRst	<=	1'b0;
+		end
+	end
+	
+	always	@(*)	begin
+		if	(!Rst_i)	begin
+			if	(measWind)	begin
+				if	(pNumCnt	!=	0)	begin
+					if	(pNumCnt	<=	tukeyFirstCosValues-1	|	pNumCnt	>	tukeySecondCosValues)	begin
+						tukeyCtrl	=	2'd2;
+					end	else	begin
+						tukeyCtrl	=	2'd1;
+					end
+				end	else	begin
+					tukeyCtrl	=	2'd0;
+				end
+			end	else	begin
+				tukeyCtrl	=	2'd0;
+			end
+		end	else	begin
+			tukeyCtrl	=	2'd0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			measWindR	<=	measWind;
+		end	else	begin
+			measWindR	<=	1'b0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			tukeyCtrlR	<=	tukeyCtrl;
+			tukeyCtrlRR	<=	tukeyCtrlR;
+		end	else	begin
+			tukeyCtrlR	<=	1'b0;
+			tukeyCtrlRR	<=	1'b0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(measWindR)	begin
+				if	(pNumCnt	==	WindPointsNum_i-1)	begin
+					measWindEnd	<=	1'b1;
+				end	else	begin
+					measWindEnd	<=	1'b0;
+				end
+			end	else	begin
+				measWindEnd	<=	1'b0;
+			end
+		end	else	begin
+			measWindEnd	<=	1'b0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(!oscMode)	begin
+				if	(measCnt	==	MeasNum_i-1)	begin
+					if	(measWindEnd)	begin
+						pMeasEnd	<=	1'b1;
+					end	else	begin
+						pMeasEnd	<=	1'b0;
+					end
+				end	else	begin
+					pMeasEnd	<=	1'b0;
+				end
+			end	else	begin
+				if	(measCnt	==	MeasNum_i-1)	begin
+					if	(OscDataRdFlag_i)	begin
+						pMeasEnd	<=	1'b1;
+					end	else	begin
+						pMeasEnd	<=	1'b0;
+					end
+				end	else	begin
+					pMeasEnd	<=	1'b0;
+				end
+			end
+		end	else	begin
+			pMeasEnd	<=	1'b0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(wideFilterFlag)	begin
+				if	(measWind)	begin
+					windArg	<=	windArg+WindPhInc_i;
+				end	else	begin
+					windArg	<=	WindPhInc_i>>1;
+				end
+			end	else	begin
+				if	(measWind)	begin
+					if	(incPhase)	begin
+						windArg	<=	windArg+WindPhInc_i;
+					end	
+					if	(decrPhase)	begin
+						windArg	<=	windArg-WindPhInc_i;
+					end
+				end	else	begin
+					windArg	<=	WindPhIncStart_i;
+				end
+			end
+		end	else	begin
+			windArg	<=	0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(!measCntRes)	begin
+				if	(!oscMode)	begin
+					if	(measCnt	!=	MeasNum_i-1)	begin
+						if	(measWindEnd)	begin
+							measCnt	<=	measCnt+1;
+						end
+					end
+				end	else	begin
+					if	(measCnt	!=	MeasNum_i-1)	begin
+						if	(OscDataRdFlag_i)	begin
+							measCnt	<=	measCnt+1;
+						end
+					end
+				end
+			end	else	begin
+				measCnt	<=	0;
+			end
+		end	else	begin
+			measCnt	<=	0;
+		end	
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(oscMode)	begin
+				if	(startMeasDspPos)	begin
+					oscWind	<=	1'b1;
+				end	
+				if	(pMeasEnd)	begin
+					oscWind	<=	1'b0;
+				end
+			end	else	begin
+				oscWind	<=	1'b0;
+			end
+		end	else	begin
+			oscWind	<=	1'b0;
+		end
+	end
+	
+	always	@(posedge	Clk_i) begin
+		if	(!Rst_i)	begin
+			if	(measWindEnd)	begin
+				startFpConv	<=	1'b1;
+			end	else	begin
+				startFpConv	<=	1'b0;
+			end
+		end	else	begin
+			startFpConv	<=	1'b0;
+		end
+	end
+
+	always @(posedge Clk_i) begin
+		startFpConvPipe[0]  <= startFpConv;
+		for(i=1; i<4; i=i+1) begin
+			startFpConvPipe	[i]<=startFpConvPipe[i-1];
+		end
+	end
+	
+	always 	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(pNumCntRes)	begin
+				pNumCnt	<=	{WindPNumWidth{1'b0}};
+			end	else	begin
+				pNumCnt	<=	pNumCnt	+	{{WindPNumWidth-1{1'b0}},1'b1};
+			end
+		end	else	begin
+			pNumCnt	<=	{WindPNumWidth{1'b0}};
+		end
+	end
+
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			startMeasReg	<=	StartMeas_i;
+		end	else	begin
+			startMeasReg	<=	1'b0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			startMeasDspReg	<=	StartMeasDsp_i;
+		end	else	begin
+			startMeasDspReg	<=	1'b0;
+		end
+	end
+	
+	always	@(*)	begin	
+		if	(!Rst_i)	begin
+			if	(StartMeasDsp_i)	begin
+				if	(!measWind)	begin
+					if	(startMeasCmd)	begin
+						measWind	=	1'b1;
+					end	
+				end	else	if	(stopCalc)	begin	
+					measWind	=	1'b0;
+				end
+			end	else	begin
+				measWind	=	1'b0;
+			end
+		end	else	begin
+			measWind	=	1'b0;
+		end
+	end
+
+endmodule

src/src/InternalDsp/NcoRstGen.v

@@ -0,0 +1,115 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 		Churbanov S.
+// 
+// Create Date:		15:22:20 12/08/2019 
+// Design Name: 
+// Module Name:		Win_parameters
+// Project Name:	Compact_main
+// Target Devices: 
+// Tool versions: 
+// Description: 	
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module NcoRstGen	
+(
+	input	Clk_i,
+	input	Rst_i,
+	input	[31:0]	NcoPhInc_i,
+	input	StartMeasEvent_i,
+	
+	output	NcoRst_o,
+	output	StartMeasEvent_o
+);
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	reg	[15:0]	startMeasEventReg;
+	reg	[31:0]	ncoPhIncReg;
+	reg	[31:0]	ncoPhIncRegR;
+	
+	wire	ncoPhIncUpdateFlag	=	(ncoPhIncRegR!=ncoPhIncReg);
+	wire	delFlag	=	(startMeasEventReg[15]);
+	
+	reg	[1:0]	currState;
+	
+	reg	rst;
+//================================================================================
+//  PARAMETERS
+//================================================================================
+	parameter	[1:0]	IDLE	=	2'd0;
+	parameter	[1:0]	RST		=	2'd1;
+	parameter	[1:0]	DEL		=	2'd2;
+//================================================================================
+//  ASSIGNMENTS
+// ================================================================================	
+	assign	NcoRst_o	=	rst;
+	assign	StartMeasEvent_o	=	(currState	==	IDLE)?	StartMeasEvent_i:startMeasEventReg[15];
+//================================================================================
+//  CODING
+//================================================================================	
+
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			ncoPhIncReg		<=	NcoPhInc_i;
+			ncoPhIncRegR	<=	ncoPhIncReg;
+		end	else	begin
+			ncoPhIncReg		<=	0;
+			ncoPhIncRegR	<=	0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			startMeasEventReg	<=	{startMeasEventReg[15:0],StartMeasEvent_i};
+		end	else	begin
+			startMeasEventReg	<=	0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			case(currState)
+			IDLE	:	begin
+							if (ncoPhIncUpdateFlag)	begin
+								currState	<= RST;
+								rst	<=	1'b1;
+							end	else begin
+								currState	<= IDLE;
+								rst	<=	1'b0;
+							end
+						end
+						
+			RST		:	begin
+							if	(rst	&	StartMeasEvent_i)	begin
+								currState	<= DEL;
+								rst	<=	1'b0;
+							end	else begin
+								currState	<= RST;
+								rst	<=	1'b1;
+							end
+						end
+		
+			DEL		:	begin
+							if	(delFlag)	begin
+								currState  <= IDLE;
+								rst	<=	1'b0;
+							end	else begin
+								currState  <= DEL;
+								rst	<=	1'b0;
+							end
+						end
+			endcase
+		end	else	begin
+			currState	<=	2'd0;
+		end
+	end
+
+endmodule

src/src/InternalDsp/WinParameters.v

@@ -0,0 +1,406 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    14:12:30 06/03/2020 
+// Design Name: 
+// Module Name:    WinParameters 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: kek
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module WinParameters 
+#(	
+	parameter	WindPhIncWidth		=	48,
+	parameter	WindNormCoefWidth	=	14,
+	parameter	WindPNumWidth		=	32,
+	parameter	BandCmdWidth		=	16
+)
+(	
+	input		Clk_i,
+	input		Rst_i,
+	input		[BandCmdWidth-1:0]		FilterCmd_i,
+	output		[WindPhIncWidth-1:0]	WinPhInc_o,
+	output		[WindPhIncWidth-1:0]	WinPhIncStart_o,
+	output		[WindNormCoefWidth-1:0]	WinNormCoef_o,
+	output		[WindPNumWidth-1:0]		WinPointsNum_o,
+	output		[WindPNumWidth-1:0]		AverageNoiseLvl_o
+);
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	reg [WindPhIncWidth-1:0]	windPhInc;
+	reg	[WindNormCoefWidth-1:0]	winNormCoef;
+	reg	[WindPNumWidth-1:0]		winPointsNum;
+	reg	[WindPNumWidth-1:0]		averageNoiseLvl;
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================	
+	assign	WinPhInc_o 			=	windPhInc;
+	assign	WinPhIncStart_o		 =	32'h80000000;
+	assign	WinNormCoef_o		=	winNormCoef;
+	assign	WinPointsNum_o		=	winPointsNum;
+	assign	AverageNoiseLvl_o	=	averageNoiseLvl;
+//================================================================================
+//  CODING
+//================================================================================	
+always	@	(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		case (FilterCmd_i)			
+			8'h0 : begin	//	1	Hz
+						windPhInc		<=	32'h2a8;
+						// winNormCoef		<=	32'h334269d2;
+						winNormCoef		<=	32'h3395e8ca;
+						winPointsNum	<=	32'h30291a0;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h1 : begin//	1.5	Hz
+						windPhInc		<=	32'h3fc;
+						// winNormCoef		<=	32'h3391cf5e;
+						winNormCoef		<=	32'h3395e8ca;
+						winPointsNum	<=	32'h201b66a;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h2 : begin//	2	Hz
+						windPhInc		<=	32'h550;
+						// winNormCoef		<=	32'h33c269d2;
+						winNormCoef		<=	32'h33c7e10e;
+						winPointsNum	<=	32'h18148d0;
+						averageNoiseLvl	<=	32'h0;
+					 end
+			8'h3 : begin//	3	Hz
+						windPhInc		<=	32'h7f9;
+						// winNormCoef		<=	32'h3411ccc1;
+						winNormCoef		<=	32'h3415e61b;
+						winPointsNum	<=	32'h100db35;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h4 : begin//	5	Hz
+						windPhInc		<=	32'hd49;
+						// winNormCoef		<=	32'h347301aa;
+						winNormCoef		<=	32'h3479d6a3;
+						winPointsNum	<=	32'h9a1d20;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h5 : begin//	7	Hz
+						windPhInc		<=	32'h129a;
+						// winNormCoef		<=	32'h34aa19fd;
+						winNormCoef		<=	32'h34aee23e;
+						winPointsNum	<=	32'h6e14cd;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h10 : begin//	10	Hz
+						windPhInc		<=	32'h1a93;
+						// winNormCoef		<=	32'h34f3005d;
+						winNormCoef		<=	32'h34f9d54a;
+						winPointsNum	<=	32'h4d0e90;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h11 : begin//	15	Hz
+						windPhInc		<=	32'h27dd;
+						// winNormCoef		<=	32'h35363ff7;
+						winNormCoef		<=	32'h353b5fa5;
+						winPointsNum	<=	32'h335f0a;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h12 : begin//	20	Hz
+						windPhInc		<=	32'h3527;
+						// winNormCoef		<=	32'h3572ffba;
+						winNormCoef		<=	32'h3579d49f;
+						winPointsNum	<=	32'h268748;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h13 : begin//	30	Hz
+						windPhInc		<=	32'h4fbb;
+						// winNormCoef		<=	32'h35b63fa7;
+						winNormCoef		<=	32'h35bb5f4e;
+						winPointsNum	<=	32'h19af85;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h14 : begin//	50	Hz
+						windPhInc		<=	32'h84e3;
+						// winNormCoef		<=	32'h3617df9c;
+						winNormCoef		<=	32'h361c24a2;
+						winPointsNum	<=	32'hf6950;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h15 : begin//	70	Hz
+						windPhInc		<=	32'hba0b;
+						// winNormCoef		<=	32'h36549f77;
+						winNormCoef		<=	32'h365a99ac;
+						winPointsNum	<=	32'hb0214;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h20 : begin//	100	Hz
+						windPhInc		<=	32'h109c7;
+						// winNormCoef		<=	32'h3697df93;
+						winNormCoef		<=	32'h369c248d;
+						winPointsNum	<=	32'h7b4a8;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h21 : begin//	150	Hz
+						windPhInc		<=	32'h18eab;
+						// winNormCoef		<=	32'h36e3cf84;
+						winNormCoef		<=	32'h36ea36ec;
+						winPointsNum	<=	32'h5231a;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h22 : begin//	200	Hz
+						windPhInc		<=	32'h21390;
+						// winNormCoef		<=	32'h3717df94;
+						winNormCoef		<=	32'h371c2478;
+						winPointsNum	<=	32'h3da54;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h23 : begin//	300	Hz 
+						windPhInc		<=	32'h31d5b;
+						// winNormCoef		<=	32'h3763cf83;
+						winNormCoef		<=	32'h376a36b6;
+						winPointsNum	<=	32'h2918d;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h24 : begin//	500	Hz
+						windPhInc		<=	32'h530e3;
+						// winNormCoef		<=	32'h37bdd7e8;
+						winNormCoef		<=	32'h37c32db2;
+						winPointsNum	<=	32'h18a88;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h25 : begin//	700	Hz
+						windPhInc		<=	32'h7449e;
+						// winNormCoef		<=	32'h3804e417;
+						winNormCoef		<=	32'h38089ffd;
+						winPointsNum	<=	32'h119ce;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h30 : begin//	1	kHz
+						windPhInc		<=	32'ha61fc;
+						// winNormCoef		<=	32'h383dd7e8;
+						winNormCoef		<=	32'h38432d23;
+						winPointsNum	<=	32'hc544;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h31 : begin//	1.5	kHz
+						windPhInc		<=	32'hf92fb;
+						// winNormCoef		<=	32'h388e6329;
+						winNormCoef		<=	32'h389262af;
+						winPointsNum	<=	32'h8382;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h32 : begin//	2	kHz
+						windPhInc		<=	32'h14c3f9;
+						// winNormCoef		<=	32'h38bdd900;
+						winNormCoef		<=	32'h38c32d23;
+						winPointsNum	<=	32'h62a2;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h33 : begin//	3	kHz
+						windPhInc		<=	32'h1f25f6;
+						// winNormCoef		<=	32'h390e6466;
+						winNormCoef		<=	32'h391262b5;
+						winPointsNum	<=	32'h41c1;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h34 : begin//	5	kHz
+						windPhInc		<=	32'h33ee26;
+						// winNormCoef		<=	32'h396d509f;
+						winNormCoef		<=	32'h3973f593;
+						winPointsNum	<=	32'h2774;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h35 : begin//	7	kHz
+						windPhInc		<=	32'h48bca9;
+						// winNormCoef		<=	32'h39a61fcc;
+						winNormCoef		<=	32'h39aac491;
+						winPointsNum	<=	32'h1c2e;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h40 : begin//	10	kHz
+						windPhInc		<=	32'h67dc4c;
+						// winNormCoef		<=	32'h39ed577f;
+						winNormCoef		<=	32'h39f3f593;
+						winPointsNum	<=	32'h13ba;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h41 : begin//	15	kHz
+						windPhInc		<=	32'h9c09c0;
+						// winNormCoef		<=	32'h3a3206c8;
+						winNormCoef		<=	32'h3a36f82e;
+						winPointsNum	<=	32'hd26;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h42 : begin//	20	kHz
+						windPhInc 		<=	32'hd00d00;
+						// winNormCoef		<=	32'h3a6d577f;
+						winNormCoef		<=	32'h3a73e7a1;
+						winPointsNum	<=	32'h9dd;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h43 : begin//	30	kHz
+						windPhInc		<=	32'h1381381;
+						// winNormCoef		<=	32'h3ab21643;
+						winNormCoef		<=	32'h3ab6f82e;
+						winPointsNum	<=	32'h693;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h44 : begin//	50	kHz
+						windPhInc		<=	32'h2082082;
+						// winNormCoef		<=	32'h3b14707d;
+						winNormCoef		<=	32'h3b1870f3;
+						winPointsNum	<=	32'h3f2;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h45 : begin//	70	KHz
+						windPhInc		<=	32'h2d82d82;
+						// winNormCoef		<=	32'h3b500d01;
+						winNormCoef		<=	32'h3b559010;
+						winPointsNum	<=	32'h2d1;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h50 : begin//	100	KHz
+						windPhInc		<=	32'h4104104;
+						// winNormCoef		<=	32'h3b949b93;
+						winNormCoef		<=	32'h3b98700b;
+						winPointsNum	<=	32'h1f9;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h51 : begin//	150	KHz
+						windPhInc 		<=	32'h6186186;
+						// winNormCoef		<=	32'h3bdfac1f;
+						winNormCoef		<=	32'h3be52dcd;
+						winPointsNum	<=	32'h150;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h52 : begin//	200	KHz
+						windPhInc		<=	32'h8421084;
+						// winNormCoef		<=	32'h3c14f209;
+						winNormCoef		<=	32'h3c18700b;
+						winPointsNum	<=	32'hfc;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h53 : begin//	300	KHz
+						windPhInc 		<=	32'hc30c30c;
+						// winNormCoef		<=	32'h3c607038;
+						winNormCoef		<=	32'h3c652dcd;
+						winPointsNum	<=	32'ha8;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h54 : begin//	500	KHz
+						windPhInc 		<=	32'h1c71c71;
+						// winNormCoef		<=	32'h3ce38e38;
+						winNormCoef		<=	32'h3ce98ccd;
+						winPointsNum	<=	32'h90;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h55 : begin//	700	KHz
+						windPhInc		<=	32'h2828282;
+						// winNormCoef		<=	32'h3d20a0a0;
+						winNormCoef		<=	32'h3d24cd6d;
+						winPointsNum	<=	32'h66;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h60 : begin//	1	MHz
+						windPhInc 		<=	32'h38e38e3;
+						// winNormCoef		<=	32'h3d638e39;
+						winNormCoef		<=	32'h3d698ccd;
+						winPointsNum	<=	32'h48;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h61 : begin//	1.5	MHz
+						windPhInc 		<=	32'h5555555;
+						// winNormCoef		<=	32'h3daaaaab;
+						winNormCoef		<=	32'h3daf299a;
+						winPointsNum	<=	32'h30;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h62 : begin//	2	MHz
+						windPhInc 		<=	32'h71c71c7;
+						// winNormCoef		<=	32'h3de38e39;
+						winNormCoef		<=	32'h3de98759;
+						winPointsNum	<=	32'h24;
+						averageNoiseLvl	<=	32'h0;
+					end	
+			8'h63 : begin
+						windPhInc 		<=	32'h0;
+						// winNormCoef		<=	32'h3e124925;
+						winNormCoef		<=	32'h3e1665f8;
+						winPointsNum	<=	32'he;
+						averageNoiseLvl	<=	32'h3b83126f;
+					end	
+			// 8'h64 : begin//	5	MHz
+						// windPhInc 		<=	32'h12492492;
+						// winNormCoef		<=	32'h3e924925;
+						// winPointsNum	<=	32'he;
+					// end	
+			// 8'h64 : begin//	2,46	MHz
+						// windPhInc 		<=	32'h9d89d89;
+						// winNormCoef		<=	32'h3df76c57;
+						// winPointsNum	<=	32'h1a;
+					// end	
+			// 8'h70 : begin
+						// параметры для калибровки - прямоугольное окно 65536 отсчетов	2^16
+						// windPhInc 		<=	32'h1FFFFFFF;
+						// winNormCoef		<=	32'h6D13892;
+						// winPointsNum	<=	32'h10000;
+					// end	
+			// 8'h71 : begin
+						// 7.5MHZ
+						// windPhInc 		<=	32'h1c71c71c;
+						// winNormCoef		<=	32'h3ee38e39;
+						// winPointsNum	<=	32'h9;
+					// end	
+			// 8'h72 : begin
+						// 10MHZ
+						// windPhInc 		<=	32'h24924924;
+						// winNormCoef		<=	32'h3f124925;
+						// winPointsNum	<=	32'h7;
+					// end	
+			8'h64 : begin
+						windPhInc 		<=	32'h0;
+						// winNormCoef		<=	32'h3e800000;
+						winNormCoef		<=	32'h3e839930;
+						winPointsNum	<=	32'h8;
+						averageNoiseLvl	<=	32'h3bc49ba6;
+					end	
+			8'h70 : begin
+						// параметры для калибровки - прямоугольное окно 65536 отсчетов	2^16
+						windPhInc 		<=	32'h1FFFFFFF;
+						winNormCoef		<=	32'h6D13892;
+						winPointsNum	<=	32'h10000;
+						averageNoiseLvl	<=	32'h0;
+					end	
+			8'h71 : begin							
+						windPhInc 		<=	32'h0;
+						// winNormCoef		<=	32'h3eaaaaab;
+						winNormCoef		<=	32'h3eaf76cd;
+						winPointsNum	<=	32'h6;
+						averageNoiseLvl	<=	32'h3c03126f;
+					end	
+			8'h72 : begin	
+						windPhInc 		<=	32'h0;
+						// winNormCoef		<=	32'h3f000000;
+						winNormCoef		<=	32'h3f039939;
+						winPointsNum	<=	32'h4;
+						averageNoiseLvl	<=	32'h3a83126f;
+					end
+					
+			default: begin	
+						windPhInc 		<=	32'h15555555;
+						winNormCoef		<=	32'h3e86cfea;
+						winPointsNum	<=	32'hc;
+						averageNoiseLvl	<=	32'h0;
+					 end					 
+		endcase
+	end	
+end
+endmodule
+

src/src/InternalDsp/Win_calc.v

@@ -0,0 +1,196 @@
+`timescale 1ns / 1ps
+(* keep_hierarchy = "yes" *)	
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 		Churbanov S.
+// 
+// Create Date:		15:22:20 12/08/2019 
+// Design Name: 
+// Module Name:		Win_parameters
+// Project Name:	Compact_main
+// Target Devices: 
+// Tool versions: 
+// Description: 	
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module Win_calc	(
+	input			clk_i,
+	input			wind_clk,
+	input	[7:0]	filterCmd_i,
+	input			reset_i,
+	input			WinCtrl_i,
+	input			MeasWind_i,
+	input	[1:0]	TukeyCtrl_i,
+	input	[31:0]	win_value_i,
+	input	[2:0]	win_type_i,	
+	output	signed [17:0]	win_o,
+	output	reg	signed [17:0]	sinWin_o
+);
+
+//================================================================================
+//  PARAMETERS
+//================================================================================
+	localparam	signed	A3_1	=	18'h15584;
+// ????????? ??? ?????????? SIN
+	localparam signed	[17:0]	A1	=	18'h12400;			// a-1
+	localparam signed	[17:0]	A2	=	18'h002C0;			// b
+	localparam signed	[17:0]	A3	=	~A3_1	+	1'b1;	// c
+	localparam signed	[17:0]	A4	=	18'h0126C;			// d
+	localparam signed	[17:0]	A5	=	18'h01C5C;			// e
+	
+	localparam	CalcWidth			=	10;
+	localparam	CalcWidthR			=	18;
+	localparam	b2Width				=	CalcWidth*2;
+	localparam	b3Width				=	CalcWidth*3;
+	localparam	b4Width				=	CalcWidth*4;
+	localparam	b5Width				=	CalcWidth*5;
+	
+	localparam [31:0]	testArg	=	32'h12492492;
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	reg			signed	[17:0]	sinWind;
+	reg			signed	[17:0]	tukeyWind;	
+		
+	reg	[1:0]	tukeyCtrlR;
+	reg	[1:0]	tukeyCtrlRR;
+	
+	reg	[35:0]	sinWindPow2;
+	
+	wire	sinFilterFlag	=	(filterCmd_i>=8'h54	&	filterCmd_i<=8'h62);
+	wire	rectFilterFlag	=	(filterCmd_i>=8'h63	&	filterCmd_i!=8'h70);
+	
+	wire	[CalcWidth-1:0]	bCurr	=	win_value_i[31]	?	10'h3FF	-	win_value_i[31-:CalcWidth]	:	win_value_i	[31-:CalcWidth];
+	
+	wire	[CalcWidthR-1:0]	bNew	=	win_value_i[31]	?	18'h3FFFF	-	win_value_i[31:14]	:	win_value_i	[31:14];
+	
+	wire	signed	[17:0]	constOne	=	18'b011111111111111111;
+	
+	reg		signed	[18:0]	tukeyCorr;
+	
+	reg		[17:0]	tukeyWindOut;
+	
+	wire	signed [17:0]	windMux1;
+	wire	signed [17:0]	windMux2;
+	
+	wire	signed	[b2Width-1:0]	b2	=	bCurr**2;
+	wire	signed	[b3Width-1:0]	b3	=	bCurr**3;
+	wire	signed	[b4Width-1:0]	b4	=	bCurr**4;
+	wire	signed	[b5Width-1:0]	b5	=	bCurr**5;
+	
+	wire	signed	[CalcWidthR-1:0]	b2Cut	=	b2[b2Width-2-:CalcWidthR];
+	wire	signed	[CalcWidthR-1:0]	b3Cut	=	b3[b3Width-3-:CalcWidthR];
+	wire	signed	[CalcWidthR-1:0]	b4Cut	=	b4[b4Width-4-:CalcWidthR];
+	wire	signed	[CalcWidthR-1:0]	b5Cut	=	b5[b5Width-5-:CalcWidthR];
+	
+	reg		signed	[CalcWidthR*2-1:0]	a1b;
+	reg		signed	[CalcWidthR*2-1:0]	a2b2;
+	reg		signed	[CalcWidthR*2-1:0]	a3b3;
+	reg		signed	[CalcWidthR*2-1:0]	a4b4;
+	reg		signed	[CalcWidthR*2-1:0]	a5b5;
+	
+	wire	signed	[CalcWidthR-1:0]	a1bCut	=	a1b	[CalcWidthR*2-2-:CalcWidthR];
+	wire	signed	[CalcWidthR-1:0]	a2b2Cut	=	a2b2[CalcWidthR*2-2-:CalcWidthR];
+	wire	signed	[CalcWidthR-1:0]	a3b3Cut	=	a3b3[CalcWidthR*2-2-:CalcWidthR];
+	wire	signed	[CalcWidthR-1:0]	a4b4Cut	=	a4b4[CalcWidthR*2-2-:CalcWidthR];
+	wire	signed	[CalcWidthR-1:0]	a5b5Cut	=	a5b5[CalcWidthR*2-2-:CalcWidthR];
+	
+	reg		signed	[CalcWidthR-1:0]	bPrevSh;
+		
+	wire	signed	[CalcWidthR-1:0]	approxSin	=	a5b5Cut+a4b4Cut+a3b3Cut+a2b2Cut+a1bCut+bPrevSh;	
+	
+	wire	signed	[CalcWidthR-1:0]	resultSin	=	approxSin[17]?	18'h1ffff:approxSin;
+//================================================================================
+//  ASSIGNMENTS
+// ================================================================================	
+	
+	assign	windMux1	=	(sinFilterFlag)	?	sinWindPow2[34-:18]:tukeyWindOut;
+	assign	windMux2	=	(rectFilterFlag)?	18'h1ffff:windMux1;
+
+	assign	win_o		=	windMux2;
+// ================================================================================
+//  CODING
+//================================================================================	
+
+always	@(posedge	clk_i)	begin
+	if	(!reset_i)	begin
+		a5b5	<=	A5*b5Cut;
+		a4b4	<=	A4*b4Cut;
+		a3b3	<=	A3*b3Cut;
+		a2b2	<=	A2*b2Cut;
+		a1b		<=	A1*bNew;
+		bPrevSh	<=	bNew;
+	end	else	begin
+		a5b5	<=	0;
+		a4b4	<=	0;
+		a3b3	<=	0;
+		a2b2	<=	0;
+		a1b		<=	0;
+		bPrevSh	<=	0;
+	end
+end
+
+always	@(posedge	clk_i)	begin
+	if	(!reset_i)	begin
+		tukeyCtrlR	<=	TukeyCtrl_i;
+		tukeyCtrlRR	<=	tukeyCtrlR;
+	end	else	begin
+		tukeyCtrlR	<=	0;
+		tukeyCtrlRR	<=	0;
+	end
+end
+
+always	@(*)	begin
+	if	(!reset_i)	begin
+		tukeyCorr	=	(tukeyWind+constOne);
+		sinWindPow2	=	resultSin**2;
+	end	else	begin
+		tukeyCorr	=	18'h0;
+		sinWindPow2	=	18'h0;
+	end
+end
+
+always	@(*)	begin
+	if	(!reset_i)	begin
+		case(tukeyCtrlR)
+			2'h0:		begin
+							tukeyWindOut	=	0;
+						end
+			2'h1:		begin
+							tukeyWindOut	=	18'h1ffff;
+						end
+			2'h2:		begin
+							tukeyWindOut	=	tukeyCorr[18-:18];
+						end
+			default:	begin
+							tukeyWindOut	=	0;
+						end
+		endcase
+	end	else	begin
+		tukeyWindOut	=	18'h0;
+	end
+end
+
+
+always	@(*)	begin
+	if	(!reset_i)	begin
+		if	(!win_type_i)	begin 
+			if	(!WinCtrl_i)	begin
+				tukeyWind	=	resultSin;
+			end	else	begin
+				tukeyWind	=	0-resultSin;
+			end
+		end	else	begin
+			tukeyWind	=	18'h0;
+		end
+	end	else	begin
+		tukeyWind	=	18'h0;
+	end
+end
+endmodule

src/src/Math/FpCustomMultiplier.v

@@ -0,0 +1,125 @@
+module FpCustomMultiplier 
+# (
+	parameter	ManWidth	=	16,
+	parameter	ExpWidth	=	6
+)
+(
+	Rst_i,
+	Clk_i,
+	A_i,
+	B_i,
+	Nd_i,
+	Result_o,
+	ResultValid_o
+);	
+
+	localparam	InOutWidth	=	1+ExpWidth+ManWidth;
+	
+	input	Rst_i;
+	input	Clk_i;
+	
+	input	[InOutWidth-1:0]	A_i;
+	input	[InOutWidth-1:0]	B_i;
+	input	Nd_i;
+	output	[InOutWidth-1:0]	Result_o;
+	output	ResultValid_o;
+	
+	localparam	ExtManWidth			=	2+ManWidth;
+	localparam	MultResultWidth		=	(ExtManWidth*2)-2;
+	localparam	ExpConst			=	(2**(ExpWidth-1))-1;
+	
+	reg	expA_or;
+	reg	expB_or;
+	
+	reg	signed	[ExtManWidth-1:0]	manAReg;
+	reg	signed	[ExtManWidth-1:0]	manBReg;
+	
+	reg	[ExpWidth-1:0]	expAReg;
+	reg	[ExpWidth-1:0]	expBReg;
+	
+	always	@(posedge	Clk_i)	begin
+		expA_or	<=	|A_i[InOutWidth-2 -:ExpWidth];	//looking for zero exponents for mult operation
+		expB_or	<=	|B_i[InOutWidth-2 -:ExpWidth];
+		
+		manAReg	<=	{2'b01,A_i[ManWidth-1 -:ManWidth]};	//add 0-sign and implied 1 to mantissa.
+		manBReg	<=	{2'b01,B_i[ManWidth-1 -:ManWidth]};
+		
+		expAReg	<=	A_i[InOutWidth-2 -:ExpWidth];	//exp highlight
+		expBReg	<=	B_i[InOutWidth-2 -:ExpWidth];
+	end
+	
+	reg	[ExpWidth:0]	expAddProd;
+	reg	expZero;
+	reg	signed	[MultResultWidth-1:0]	manMultProd;
+	
+	always	@(posedge	Clk_i)	begin
+		manMultProd	<=	manAReg*manBReg;	//man(C)=man(A)*man(B)
+		
+		expAddProd	<=	expAReg+expBReg-ExpConst;	//exp(C)=exp(A)+exp(B)-ExpConst. ExpConst = 2^ExpWidth-1;
+		
+		expZero	<=	~(expA_or&expB_or);	//setting exp(C) = 0 when either A or B is zero or denormalized.
+	end
+	
+	reg	[ExpWidth-1:0]	expCReg;
+	reg	expResultNegative;
+	reg	[ManWidth-1:0]	manCReg;
+	
+	always	@(posedge	Clk_i)	begin
+		expResultNegative	<=	expAddProd[ExpWidth]; //if exponents are too small then their result will be negative
+		
+		if	(Rst_i)	begin
+			expCReg	<=	{ExpWidth{1'b0}};
+		end	else	if	(expAddProd[ExpWidth]||expZero)	begin
+			expCReg	<=	{ExpWidth{1'b0}};
+		end	else	begin
+			expCReg	<=	expAddProd[ExpWidth-1:0]+manMultProd[MultResultWidth-1];
+		end
+		
+		if	(Rst_i)	begin
+			manCReg	<=	{ManWidth{1'b0}};
+		end	else	if	(expAddProd[ExpWidth]||expZero)	begin
+			manCReg	<=	{ManWidth{1'b0}};
+		end	else	if	(!manMultProd[MultResultWidth-1])	begin	//normalize man(C) in accordance to MSB value
+			manCReg	<=	manMultProd[MultResultWidth-3 -:ManWidth];	
+		end	else	begin
+			manCReg	<=	manMultProd[MultResultWidth-2 -:ManWidth];
+		end
+	end
+		
+	reg	[4:0]	signCShReg;
+	always	@(posedge	Clk_i)	begin
+		signCShReg	<=	{signCShReg[3:0], A_i[InOutWidth-1] ^ B_i[InOutWidth-1]};
+	end
+	
+	reg	[5:0]	resValidShReg;
+	always	@(posedge	Clk_i)	begin
+		resValidShReg	<=	{resValidShReg[4:0],	Nd_i};
+	end
+	
+	assign Result_o = {signCShReg[2], expCReg,manCReg};
+	assign ResultValid_o = resValidShReg[2];
+	
+endmodule
+
+
+
+
+
+
+
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+
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+

src/src/Math/MultModule.v

@@ -0,0 +1,76 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    mult_module 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	MultModule	
+#(	
+	parameter	AdcDataWidth	=	14,
+	parameter	IfNcoOutWidth	=	18,
+	parameter	MultDataWidth	=	36
+)	
+(
+	input	Rst_i,
+	input	Clk_i,
+	input	signed	[AdcDataWidth-1:0]	AdcData_i,
+	input	signed	[IfNcoOutWidth-1:0]	Sin_i,
+	input	signed	[IfNcoOutWidth-1:0]	Cos_i,
+	output	signed	[MultDataWidth-1:0]	AdcSin_o,
+	output	signed	[MultDataWidth-1:0]	AdcCos_o
+);
+
+//================================================================================
+//  LOCALPARAM
+
+//================================================================================
+//  REG/WIRE
+	reg	signed	[IfNcoOutWidth-1:0]	adcDataCompl;
+	reg	signed	[IfNcoOutWidth-1:0]	sinReg;
+	reg	signed	[IfNcoOutWidth-1:0]	cosReg;
+	
+	reg	signed	[MultDataWidth-1:0]	AdcSinReg;
+	reg	signed	[MultDataWidth-1:0]	AdcCosReg;
+//================================================================================
+//  ASSIGNMENTS
+	assign	AdcSin_o	=	AdcSinReg;
+	assign	AdcCos_o	=	AdcCosReg;
+//================================================================================
+//  CODING
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			adcDataCompl	<=	{AdcData_i,4'b0};
+			sinReg	<=	Sin_i;
+			cosReg	<=	Cos_i;
+		end	else	begin
+			adcDataCompl	<=	0;
+			sinReg	<=	0;
+			cosReg	<=	0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			AdcSinReg	<=	adcDataCompl*sinReg;
+			AdcCosReg	<=	adcDataCompl*cosReg;
+		end	else	begin
+			AdcSinReg	<=	{MultDataWidth{1'b0}};
+			AdcCosReg	<=	{MultDataWidth{1'b0}};
+		end
+	end
+	
+endmodule

src/src/Math/MyIntToFp.v

@@ -0,0 +1,153 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    12:14:34 01/28/2021 
+// Design Name: 
+// Module Name:    FpConvTop 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	MyIntToFp	
+#(	
+	parameter	InWidth		=	32,
+	parameter	ExpWidth	=	8,
+	parameter	ManWidth	=	23,
+	parameter	FracWidth	=	17
+)
+(Clk_i,Rst_i,InData_i,AverageNoizeLvl_i,InDataVal_i,OutData_o,OutDataVal_o);
+
+	input	Clk_i;
+	input	Rst_i;
+	input	[InWidth-1:0]	InData_i;
+	input	InDataVal_i;
+	
+	localparam	OutWidth	=	1+ExpWidth+ManWidth;	//sign+ExpWidth+ManWidth
+	localparam	ExpConst	=	(2**(ExpWidth-1))-1;
+	
+	input		[OutWidth-1:0]	AverageNoizeLvl_i;
+	output	reg	[OutWidth-1:0]	OutData_o;
+	output	reg	OutDataVal_o;
+	
+//================================================================================
+//  Func
+	function integer Log2;
+	input integer value;
+		begin
+			Log2 = 0;
+			while (value > 1) begin
+				value   = value >> 1;
+				Log2    = Log2 + 1;
+			end
+			
+			if	((2**Log2)<InWidth)	begin
+				Log2	=	Log2+1;
+			end	
+		end
+	endfunction
+	
+	localparam Stages = Log2(InWidth);
+	
+//================================================================================
+//  Coding
+	reg		[InWidth-1:0]	inDataR;
+	reg		signR;
+	reg		outValR;
+	wire	[OutWidth-1:0]	fpOut;
+	wire	[Stages-1:0]	distance;
+	genvar  i;
+	wire	[ExpWidth-1:0]	fpExp;
+	
+always	@(posedge	Clk_i)	begin
+	if	(Rst_i)	begin
+		inDataR	<=	{InWidth{1'b0}};
+		signR	<=	1'b0;
+		outValR	<=	1'b0;
+	end	else	begin
+		if	(InData_i	[InWidth-1])	begin
+			inDataR	<=	~InData_i+1'b1;
+		end	else	begin
+			inDataR	<=	InData_i;
+		end
+		signR	<=	InData_i[InWidth-1];
+		outValR	<=	InDataVal_i;
+	end
+end
+
+wire	[(Stages+1)*InWidth-1:0]	dataArray;
+
+assign  dataArray [InWidth-1:0] = inDataR;			
+	
+generate	
+	for (i=0; i<Stages; i=i+1)	begin: searchMSB
+		wire [InWidth-1:0] dataIn;	
+        wire [InWidth-1:0] shiftedDataOut;
+        wire [InWidth-1:0] dataOut;
+		
+        assign  dataIn = dataArray[(i+1)*InWidth-1:i*InWidth];
+
+        wire    shiftDesired = ~|(dataIn[InWidth-1:InWidth-(1 << (Stages-1-i))]);
+        assign  distance[(Stages-1-i)] = shiftDesired;		
+        assign  shiftedDataOut = dataIn << (1 << (Stages-1-i));	
+        assign  dataOut = shiftDesired ? shiftedDataOut : dataIn;	
+        assign  dataArray[(i+2)*InWidth-1:(i+1)*InWidth] = dataOut;	
+	end
+endgenerate
+
+wire	[InWidth-1:0]	scaledData	=	dataArray[(Stages+1)*InWidth-1:Stages*InWidth];
+wire	[ManWidth-1:0]	mantisa		=	scaledData[InWidth-2 -:ManWidth];
+
+assign	fpExp		=	(ExpConst+(InWidth-1-FracWidth))-distance;
+assign	fpOut		=	&distance ? {signR, 31'h0}:	{signR, fpExp,	mantisa};
+
+always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
+	if	(Rst_i)	begin
+		OutData_o		<=	{OutWidth{1'b0}};
+		OutDataVal_o	<=	1'b0;
+	end	else	begin
+		if	(outValR)	begin
+			if	(fpOut!=0)	begin
+				OutData_o	<=	fpOut;
+			end	else	begin
+				// OutData_o	<=	32'h3a83126f;
+				OutData_o	<=	AverageNoizeLvl_i;
+			end
+		end
+		OutDataVal_o	<=	outValR;
+	end
+end
+endmodule
+
+
+
+
+
+
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+
+

src/src/Math/SimpleMult.v

@@ -0,0 +1,66 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    SimpleMult 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	SimpleMult	
+#(	
+	parameter	FactorAWidth	=	14,
+	parameter	FactorBWidth	=	14,
+	parameter	OutputWidth		=	18
+)	
+(
+	input	Rst_i,
+	input	Clk_i,
+	input	Val_i,
+	input	signed	[FactorAWidth-1:0]	FactorA_i,
+	input	signed	[FactorBWidth-1:0]	FactorB_i,
+	
+	
+	output	signed	[OutputWidth-1:0]	Result_o,
+	output	ResultVal_o
+);
+
+//================================================================================
+//  LOCALPARAM
+	localparam	ResultWidth	=	FactorAWidth+FactorBWidth;
+//================================================================================
+//  REG/WIRE
+	reg	[ResultWidth-1:0]	resultReg;
+	reg	resultValReg;
+//================================================================================
+//  ASSIGNMENTS
+	assign	Result_o	=	(ResultWidth==OutputWidth)?	resultReg:resultReg[ResultWidth-2-:OutputWidth];
+	assign	ResultVal_o	=	resultValReg;
+//================================================================================
+//  CODING
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(Val_i)	begin
+				resultReg		<=	FactorA_i*FactorB_i;
+				resultValReg	<=	Val_i;
+			end	else	begin
+				resultReg		<=	{ResultWidth{1'b0}};
+				resultValReg	<=	1'b0;
+			end
+		end	else	begin
+			resultReg		<=	{ResultWidth{1'b0}};
+			resultValReg	<=	1'b0;
+		end
+	end
+endmodule

src/src/Math/SumAcc.v

@@ -0,0 +1,39 @@
+module SumAcc 
+#(	
+	parameter	IDataWidth	=	14,
+	parameter	ODataWidth	=	48
+)
+(
+    input	Clk_i,
+    input	Rst_i,
+    input	Val_i,
+	input	[IDataWidth-1:0]	Data_i,
+	
+	output	[ODataWidth-1:0]	Result_o
+);
+
+//================================================================================
+//  LOCALPARAMS
+
+//================================================================================
+//  REG/WIRE
+	reg		[ODataWidth-1:0]	dataAcc;
+	reg		resultVal;
+	wire	[ODataWidth-1:0]	extData	=	{{(ODataWidth - IDataWidth){Data_i[IDataWidth-1]}}, Data_i};	//sign extension
+	
+//================================================================================
+//  ASSIGNMENTS
+	assign	Result_o	=	dataAcc;
+//================================================================================
+//  CODING
+	always	@(posedge	Clk_i)	begin
+		if	(Rst_i)	begin
+			dataAcc		<=	{ODataWidth{1'b0}};
+		end	else	if	(Val_i)	begin
+			dataAcc		<=	dataAcc+extData;
+		end	else	begin
+			dataAcc		<=	0;
+		end
+	end
+
+endmodule

src/src/MeasDataFifo/FftDataFormer.v

@@ -0,0 +1,137 @@
+`timescale 1ns / 1ps
+(* keep_hierarchy = "yes" *)	
+module FftDataFormer
+#(	
+	parameter	AdcDataWidth		=	16,	
+	parameter	ExtAdcDataWidth		=	AdcDataWidth+2,	
+	parameter	ChNum				=	1,
+	parameter	OutDataWidth		=	256,
+	parameter	DataValCycles		=	OutDataWidth/(AdcDataWidth*2)
+)	
+(
+	input	Clk_i, 
+	input	Rst_i,	
+	input	OscWind_i,
+	input	[31:0]	MeasNum_i,
+	
+	input	[AdcDataWidth*2-1:0]	AdcData_i,
+	input	AdcDataVal_i,
+
+	
+	output	[OutDataWidth-1:0]	OscDataBus_o,
+	output	OscDataBusVal_o
+);
+//================================================================================
+//  REG/WIRE
+//================================================================================
+
+	reg	[OutDataWidth-1:0]	oscDataBusReg;
+	reg	[OutDataWidth-1:0]	oscDataBusRegReg;
+	
+	reg	oscDataBusValReg;
+	reg	oscDataBusValRegReg;
+	
+	reg	[DataValCycles-1:0]	cycleCnt;
+	
+	reg	[31:0]	wrDataCnt;
+	wire	wrDone	=	OscWind_i?	(wrDataCnt	==	MeasNum_i):1'b0;
+	
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+
+	assign	OscDataBus_o	=	oscDataBusRegReg;
+	assign	OscDataBusVal_o	=	oscDataBusValRegReg;
+	
+//================================================================================
+//  CODING
+//================================================================================	
+
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(OscWind_i)	begin
+				if	(!wrDone)	begin
+					oscDataBusValRegReg	<=	oscDataBusValReg;
+				end	else	begin
+					oscDataBusValRegReg	<=	0;
+				end
+			end	else	begin
+				oscDataBusValRegReg	<=	0;
+			end
+		end	else	begin
+			oscDataBusValRegReg	<=	0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(oscDataBusValReg)	begin
+				// oscDataBusRegReg	<=	oscDataBusReg;
+				oscDataBusRegReg	<=	{oscDataBusReg[127:0], oscDataBusReg[OutDataWidth-1:128]};
+			end	
+		end	else	begin
+			oscDataBusRegReg	<=	0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(OscWind_i)	begin
+				if	(AdcDataVal_i)	begin
+					if	(cycleCnt	!=	DataValCycles-1)	begin
+						cycleCnt	<=	cycleCnt+4'd1;
+					end	else	begin
+						cycleCnt	<=	4'd0;
+					end
+				end	
+			end	else	begin
+				cycleCnt	<=	0;
+			end
+		end	else	begin
+			cycleCnt	<=	4'd0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(OscWind_i)	begin
+				if	(oscDataBusValRegReg)	begin
+					if	(wrDataCnt	!=	MeasNum_i)	begin
+						wrDataCnt	<=	wrDataCnt+1;
+					end
+				end
+			end	else	begin
+				wrDataCnt	<=	0;
+			end
+		end	else	begin
+			wrDataCnt	<=	0;
+		end
+	end
+
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(OscWind_i)	begin
+				if	(AdcDataVal_i)	begin
+					oscDataBusReg	<=	{oscDataBusReg[OutDataWidth-AdcDataWidth-1:0],AdcData_i};	//first points
+				end
+			end	else	begin
+				oscDataBusReg	<=	0;
+			end
+		end	else	begin
+			oscDataBusReg	<=	0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(cycleCnt	==	DataValCycles-1	&	AdcDataVal_i)	begin
+				oscDataBusValReg	<=	1'b1;
+			end	else	begin
+				oscDataBusValReg	<=	1'b0;
+			end
+		end	else	begin
+			oscDataBusValReg	<=	1'b0;
+		end
+	end
+
+endmodule

src/src/MeasDataFifo/FifoController.v

@@ -0,0 +1,110 @@
+`timescale 1ns / 1ps
+
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    14:12:30 06/03/2020 
+// Design Name: 
+// Module Name:    WinParameters 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: kek
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//
+//////////////////////////////////////////////////////////////////////////////////
+	
+module FifoController	
+#(
+	parameter	TxInPack		=	200,		
+	parameter	WorkTimeCycles	=	404000
+	// parameter	WorkTimeCycles	=	20000
+)
+(
+	input	Clk_i, 
+	input	Rst_i,	
+	input	PpiBusy_i,	
+	input	DspReadyForRx_i,
+	input	MeasDataVal_i,
+	input	[32-1:0]	MeasNum_i,
+	input	FullFlag_i,
+	input	EmptyFlag_i,
+	
+	output	MeasDataVal_o,
+	
+	output	reg	WrEn_o,
+	output	RdEn_o
+);
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	reg	rdEn;
+	reg	[13:0]	wrCnt;
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+	assign	MeasDataVal_o	=	rdEn&(!PpiBusy_i);
+	assign	RdEn_o			=	rdEn&(!PpiBusy_i);
+	
+//================================================================================
+//  CODING
+//================================================================================		
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(WrEn_o)	begin
+			wrCnt	<=	wrCnt+14'd1;
+		end	
+	end	else	begin
+		wrCnt	<=	14'd0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(!FullFlag_i)	begin
+			if	(MeasDataVal_i)	begin
+				if	(wrCnt!=MeasNum_i)	begin
+					WrEn_o	<=	1'b1;
+				end	else	begin
+					WrEn_o	<=	1'b0;
+				end
+			end	else	begin
+				WrEn_o	<=	1'b0;
+			end
+		end	else	begin
+			WrEn_o	<=	1'b0;
+		end
+	end	else	begin
+		WrEn_o	<=	1'b0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(!DspReadyForRx_i)	begin
+			if	(!PpiBusy_i)	begin
+				if	(!EmptyFlag_i)	begin
+					rdEn	<=	1'b1;
+				end	else	begin
+					rdEn	<=	1'b0;
+				end
+			end	else	begin
+				rdEn	<=	1'b0;
+			end
+		end	else	begin
+			rdEn	<=	1'b0;
+		end
+	end	else	begin
+		rdEn	<=	1'b0;
+	end
+end
+
+endmodule

src/src/MeasDataFifo/MeasDataFifoWrapper.v

@@ -0,0 +1,121 @@
+`timescale 1ns / 1ns
+	
+module MeasDataFifoWrapper	
+#(	
+	parameter	DataWidth	=	32,
+	parameter	ChNum		=	4
+)
+(
+	input	Clk_i, 
+	input	Rst_i,	
+	input	PpiBusy_i,	
+	input	StartMeasDsp_i,
+	input	DspReadyForRx_i,
+	input	[DataWidth-1:0]	MeasNum_i,
+	
+	input	[DataWidth*(ChNum*2)-1:0]	MeasDataBus_i,
+	input	MeasDataVal_i,
+	
+	output	[DataWidth*(ChNum*2)-1:0]	MeasDataBus_o,
+	output	MeasDataVal_o
+);
+//================================================================================
+//  REG/WIRE
+//================================================================================
+
+	wire	fullFlagExt;
+	wire	emptyFlagExt;
+	
+	wire	fullFlag;
+	wire	emptyFlag;
+	
+	wire	wrEn;
+	wire	rdEn;
+
+	reg		startMeasDspReg;
+	wire	startMeasDspNeg;
+	wire	startMeasDspPos;
+	
+	reg		ppiBusyReg;
+	
+	reg		rstFromDsp;
+	wire	trueRstFromDsp;
+	
+	integer	i;
+	reg	[0:0]	rstFromDspPipe	[49:0];
+	
+	reg		[13:0]	rdCnt;
+	wire	rstOr;
+	
+	wire	[DataWidth*(ChNum*2)-1:0]	measDataBus;
+	wire	writeEn	=	!(emptyFlagExt|fullFlag);
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+	assign	rstOr	=	Rst_i|startMeasDspPos;
+	assign	MeasDataVal_o		=	rdEn;
+	assign	startMeasDspPos		=	(StartMeasDsp_i&(!startMeasDspReg));
+//================================================================================
+//  CODING
+//================================================================================		
+
+always	@(posedge	Clk_i)	begin
+	if	(!rstOr)	begin
+		if	(rdEn)	begin
+			rdCnt	<=	rdCnt+14'd1;
+		end	
+	end	else	begin
+		rdCnt	<=	14'd0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		startMeasDspReg	<=	StartMeasDsp_i;
+	end	else	begin
+		startMeasDspReg	<=	1'b0;
+	end
+end
+
+MeasDataFifoExtender	MeasDataFifoExtender
+(
+	.clk	(Clk_i),
+	.srst	(Rst_i|startMeasDspPos),
+	.din	(MeasDataBus_i),
+	.wr_en	(wrEn),
+	.rd_en	(writeEn),
+	.dout	(measDataBus),
+	.full	(fullFlagExt),
+	.empty	(emptyFlagExt)
+);
+
+MeasDataFifo	MeasDataFifo
+(
+	.clk	(Clk_i),
+	.srst	(Rst_i|startMeasDspPos),
+	.din	(measDataBus),
+	.wr_en	(writeEn),
+	.rd_en	(rdEn),
+	.dout	(MeasDataBus_o),
+	.full	(fullFlag),
+	.empty	(emptyFlag)
+);
+
+  
+FifoController	FifoController
+(
+	.Clk_i				(Clk_i), 
+	.Rst_i				(Rst_i|startMeasDspPos),	
+	.DspReadyForRx_i	(DspReadyForRx_i),	
+	.PpiBusy_i			(PpiBusy_i),	
+	.MeasNum_i			(MeasNum_i),	
+	.MeasDataVal_i		(MeasDataVal_i),
+	.FullFlag_i			(fullFlagExt),
+	.EmptyFlag_i		(emptyFlag),
+	
+	.MeasDataVal_o		(),
+	.WrEn_o				(wrEn),
+	.RdEn_o				(rdEn)
+);
+
+endmodule

src/src/MeasDataFifo/OscDataFormer.v

@@ -0,0 +1,138 @@
+`timescale 1ns / 1ps
+(* keep_hierarchy = "yes" *)	
+module OscDataFormer
+#(	
+	parameter	AdcDataWidth		=	16,	
+	parameter	ExtAdcDataWidth		=	AdcDataWidth+2,	
+	parameter	ChNum				=	1,
+	parameter	DataValCycles		=	16,
+	parameter	OutDataWidth		=	(16*ChNum)*DataValCycles
+)	
+(
+	input	Clk_i, 
+	input	Rst_i,	
+	input	OscWind_i,
+	input	[31:0]	MeasNum_i,
+	
+	input	AdcDataVal_i,
+	input	[AdcDataWidth-1:0]	AdcData_i,	
+	
+	output	[OutDataWidth-1:0]	OscDataBus_o,
+	output	OscDataBusVal_o
+);
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	
+	wire	signed	[15:0]	adcDataExt	=	{{2{AdcData_i[AdcDataWidth-1]}},AdcData_i};
+	
+	reg	[OutDataWidth-1:0]	oscDataBusReg;
+	reg	[OutDataWidth-1:0]	oscDataBusRegReg;
+	
+	reg	oscDataBusValReg;
+	reg	oscDataBusValRegReg;
+	
+	reg	[4-1:0]	cycleCnt;
+	
+	reg	[31:0]	wrDataCnt;
+	wire	wrDone	=	OscWind_i?	(wrDataCnt	==	MeasNum_i):1'b0;
+	
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+	assign	OscDataBus_o	=	oscDataBusRegReg;
+	assign	OscDataBusVal_o	=	oscDataBusValRegReg;
+	
+//================================================================================
+//  CODING
+//================================================================================	
+
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(OscWind_i)	begin
+				if	(!wrDone)	begin
+					oscDataBusValRegReg	<=	oscDataBusValReg;
+				end	else	begin
+					oscDataBusValRegReg	<=	0;
+				end
+			end	else	begin
+				oscDataBusValRegReg	<=	0;
+			end
+		end	else	begin
+			oscDataBusValRegReg	<=	0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(OscWind_i)	begin
+				if	(oscDataBusValReg)	begin
+					oscDataBusRegReg	<=	{oscDataBusReg[127:0], oscDataBusReg[OutDataWidth-1:128]};
+					// oscDataBusRegReg	<=	{16'h7,16'h6,16'h5,16'h4,16'h3,16'h2,16'h1,16'h0,16'hF,16'hE,16'hD,16'hC,16'hB,16'hA,16'h9,16'h8};
+				end	
+			end	else	begin
+				oscDataBusRegReg	<=	0;
+			end
+		end	else	begin
+			oscDataBusRegReg	<=	0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(OscWind_i)	begin
+				if	(AdcDataVal_i)	begin
+					cycleCnt	<=	cycleCnt+4'd1;
+				end
+			end	else	begin
+				cycleCnt	<=	0;
+			end
+		end	else	begin
+			cycleCnt	<=	4'd0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(OscWind_i)	begin
+				if	(oscDataBusValRegReg)	begin
+					if	(wrDataCnt	!=	MeasNum_i)	begin
+						wrDataCnt	<=	wrDataCnt+1;
+					end
+				end
+			end	else	begin
+				wrDataCnt	<=	0;
+			end
+		end	else	begin
+			wrDataCnt	<=	0;
+		end
+	end
+
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(OscWind_i)	begin
+				if	(AdcDataVal_i)	begin
+					// oscDataBusReg	<=	{adcDataExt,oscDataBusReg[OutDataWidth-1:AdcDataWidth+2]};	//first points
+					oscDataBusReg	<=	{AdcData_i,oscDataBusReg[OutDataWidth-1:AdcDataWidth]};	//first points
+				end
+			end	else	begin
+				oscDataBusReg		<=	0;
+			end
+		end	else	begin
+			oscDataBusReg		<=	0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(cycleCnt	==	DataValCycles-1	&	AdcDataVal_i)	begin
+				oscDataBusValReg	<=	1'b1;
+			end	else	begin
+				oscDataBusValReg	<=	1'b0;
+			end
+		end	else	begin
+			oscDataBusValReg	<=	1'b0;
+		end
+	end
+	
+endmodule

src/src/PgenDecription.txt

@@ -0,0 +1,54 @@
+Чтобы попасть в режим "Точка в импульсе" нужно:
+1. Установить, для генератора являющегося модулятором, шаблон "1 импульс", значения задержки и длительности импульса.
+2. Колличество измерений установить = 1.
+3. Колличество импульсов SampleStrobeGen  установить = 1.
+3. Сконфигурировать период следования импульсов для RefSequencer.
+
+
+Чтобы попасть в режим "Профиль импульса с конфигурируемым колличеством импульсов" нужно:
+1. Установить, для генератора являющегося модулятором, шаблон "1 импульс", значения задержки и длительности импульса.
+2. Колличество измерений установить = N.
+3. Сконфигурировать период следования импульсов для RefSequencer.
+4. Сконфигурировать колличество импульсов для SampleStrobeGen.
+
+
+Чтобы попасть в режим "Профиль импульса с шаблонами" нужно:
+1. Установить, для генератора являющегося модулятором, шаблон "1,2 или 3 импульса", значения задержки и длительности импульсов.
+2. Колличество измерений установить = N.
+3. Сконфигурировать период следования импульсов для RefSequencer.
+4. Сконфигурировать колличество импульсов для SampleStrobeGen.
+
+
+Чтобы попасть в режим "От импульса к импульсу" нужно:
+1. Установить, для генератора являющегося модулятором, шаблон "Burst", значения задержки и длительности импульса.
+2. Колличество измерений установить = N.
+3. Сконфигурировать период следования импульсов для RefSequencer.
+4. Сконфигурировать колличество импульсов для SampleStrobeGen.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

src/src/PulseMeas/ActivePortSelector.v

@@ -0,0 +1,152 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    mult_module 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	ActivePortSelector	
+#(	
+	parameter	PortsNum	=	4
+)
+(
+	input	Rst_i,
+	
+	input	Mod_i,
+	input	[PortsNum-1:0]	Ctrl_i,
+	
+	output	reg	[PortsNum-1:0]	Ctrl_o
+);	
+
+//================================================================================
+//  LOCALPARAM
+//================================================================================
+	localparam	LutNum		=	2**PortsNum;
+	localparam	PortsNone	=	4'b0000;
+	localparam	Ports_1		=	4'b0001;
+	localparam	Ports_2		=	4'b0010;
+	localparam	Ports_21	=	4'b0011;
+	localparam	Ports_3		=	4'b0100;
+	localparam	Ports_31	=	4'b0101;
+	localparam	Ports_32	=	4'b0110;
+	localparam	Ports_321	=	4'b0111;
+	localparam	Ports_4		=	4'b1000;
+	localparam	Ports_41	=	4'b1001;
+	localparam	Ports_42	=	4'b1010;
+	localparam	Ports_421	=	4'b1011;
+	localparam	Ports_43	=	4'b1100;
+	localparam	Ports_431	=	4'b1101;
+	localparam	Ports_432	=	4'b1110;
+	localparam	Ports_4321	=	4'b1111;
+	
+//================================================================================
+//	REG/WIRE
+//================================================================================
+	wire		[PortsNum-1:0]	Lut	[LutNum-1:0];
+
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+	assign	Lut	[0]		=	~(4'b0000);
+	assign	Lut	[1]		=	~({3'b000,Mod_i});
+	assign	Lut	[2]		=	~({2'b00,Mod_i,1'b0});
+	assign	Lut	[3]		=	~({2'b00,Mod_i,Mod_i});
+	assign	Lut	[4]		=	~({1'b0,Mod_i,2'b0});
+	assign	Lut	[5]		=	~({1'b0,Mod_i,1'b0,Mod_i});
+	assign	Lut	[6]		=	~({1'b0,Mod_i,Mod_i,1'b0});
+	assign	Lut	[7]		=	~({1'b0,Mod_i,Mod_i,Mod_i});
+	assign	Lut	[8]		=	~({Mod_i,3'b000});
+	assign	Lut	[9]		=	~({Mod_i,2'b00,Mod_i});
+	assign	Lut	[10]	=	~({Mod_i,1'b0,Mod_i,1'd0});
+	assign	Lut	[11]	=	~({Mod_i,1'b0,Mod_i,Mod_i});
+	assign	Lut	[12]	=	~({Mod_i,Mod_i,2'b00});
+	assign	Lut	[13]	=	~({Mod_i,Mod_i,1'b0,Mod_i});
+	assign	Lut	[14]	=	~({Mod_i,Mod_i,Mod_i,1'b0});
+	assign	Lut	[15]	=	~({Mod_i,Mod_i,Mod_i,Mod_i});
+
+//================================================================================
+//  CODING
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		case	(Ctrl_i)
+			PortsNone:	begin
+							Ctrl_o	=	Lut[0];
+						end
+			Ports_1:	begin
+							Ctrl_o	=	Lut[1];
+						end	
+			Ports_2:	begin
+							Ctrl_o	=	Lut[2];
+						end
+			Ports_21:	begin
+							Ctrl_o	=	Lut[3];
+						end	
+			Ports_3:	begin
+							Ctrl_o	=	Lut[4];
+						end		
+			Ports_31:	begin
+							Ctrl_o	=	Lut[5];
+						end	
+			Ports_32:	begin
+							Ctrl_o	=	Lut[6];
+						end	
+			Ports_321:	begin
+							Ctrl_o	=	Lut[7];
+						end
+			Ports_4:	begin
+							Ctrl_o	=	Lut[8];
+						end		
+			Ports_41:	begin
+							Ctrl_o	=	Lut[9];
+						end	
+			Ports_42:	begin
+							Ctrl_o	=	Lut[10];
+						end	
+			Ports_421:	begin
+							Ctrl_o	=	Lut[11];
+						end
+			Ports_43:	begin
+							Ctrl_o	=	Lut[12];
+						end	
+			Ports_431:	begin
+							Ctrl_o	=	Lut[13];
+						end
+			Ports_432:	begin
+							Ctrl_o	=	Lut[14];
+						end
+			Ports_4321:	begin
+							Ctrl_o	=	Lut[15];
+						end
+		endcase
+	end	else	begin
+		Ctrl_o	=	4'd0;
+	end
+end
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+

src/src/PulseMeas/MeasStartEventGen.v

@@ -0,0 +1,109 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    mult_module 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//commands:
+//	ExtTrigUsage: 0 - no, 1 - yes.
+//
+//
+//
+//
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	MeasStartEventGen	
+#(	
+	parameter	CmdRegWidth	=	32
+)
+(
+	input	Clk_i,
+	input	Rst_i,
+
+	input	MeasTrig_i,
+	input	StartMeasDsp_i,
+	
+	output	StartMeasEvent_o,
+	output	InitTrig_o
+);	
+
+//================================================================================
+//  LOCALPARAM
+
+//================================================================================
+	reg		startMeasEvent;
+	reg		initTrig;
+	
+	reg		measTrigReg;
+	wire	measTrigPos;
+//================================================================================
+//  ASSIGNMENTS
+	assign	measTrigPos			=	(!measTrigReg&MeasTrig_i);
+	assign	StartMeasEvent_o	=	startMeasEvent;
+	assign	InitTrig_o			=	initTrig;
+//================================================================================
+//  CODING
+
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			measTrigReg	<=	MeasTrig_i;
+		end	else	begin
+			measTrigReg	=	0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(StartMeasDsp_i)	begin
+				if	(measTrigPos)	begin
+					startMeasEvent	<=	1'b1;
+				end
+			end	else	begin
+				startMeasEvent	<=	0;
+			end
+		end	else	begin
+			startMeasEvent	<=	0;
+		end
+	end
+	
+	always	@(*)	begin
+		if	(!Rst_i)	begin
+			if	(StartMeasDsp_i)	begin
+				if	(measTrigPos)	begin
+					initTrig	=	1'b1;
+				end	else	begin
+					initTrig	=	1'b0;
+				end	
+			end	else	begin
+				initTrig	=	0;
+			end
+		end	else	begin
+			initTrig	=	0;
+		end
+	end
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+

src/src/PulseMeas/Mux.v

@@ -0,0 +1,75 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    mult_module 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	Mux	
+#(	
+	parameter	CmdRegWidth		=	24,
+	parameter	PGenNum			=	7,
+	parameter	TrigPortsNum	=	6
+)
+(
+	input	Rst_i,
+	
+	input	[CmdRegWidth-28:0]	MuxCtrl_i,
+	
+	input	DspTrigOut_i,
+	input	DspStartCmd_i,
+	input	IntTrig_i,
+	input	IntTrig2_i,
+	input	[PGenNum-1:0]		PulseBus_i,
+	input	[TrigPortsNum-1:0]	ExtPortsBus_i,
+	
+	output	MuxOut_o
+);	
+
+//================================================================================
+//  LOCALPARAM
+
+//================================================================================
+//	REG/WIRE
+	reg		muxOut;
+	wire	[PGenNum+TrigPortsNum+5:0]	inputBus	=	{IntTrig2_i,1'b1,1'b0,DspStartCmd_i,DspTrigOut_i,IntTrig_i,ExtPortsBus_i,PulseBus_i};
+//================================================================================
+//  ASSIGNMENTS
+	assign	MuxOut_o	=	muxOut;
+
+//================================================================================
+//  CODING
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		muxOut	=	inputBus[MuxCtrl_i];
+	end	else	begin
+		muxOut	=	1'b0;
+	end
+end
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+

src/src/PulseMeas/PGenRstGenerator.v

@@ -0,0 +1,117 @@
+//`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    PulseGen 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	PGenRstGenerator	
+#(	
+	parameter	PgenNum	=	7
+)
+(
+	input	Rst_i,
+	input	Clk_i,
+	
+	input	[PgenNum-1:0]	PGenRst_i,
+	
+	output	reg	[PgenNum-1:0]	PGenRst_o,
+	output	reg	RstDone_o
+);	
+
+//================================================================================
+//  LOCALPARAM
+//================================================================================
+	localparam	IDLE	=	2'h0;
+	localparam	RST		=	2'h1;
+	localparam	DEL		=	2'h2;
+	
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	reg	[1:0]	currState;
+	
+	reg	[PgenNum-1:0]	pGenRstReg;
+	
+	wire	orPGenRstReg	=	|pGenRstReg;
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+
+//================================================================================
+//  CODING
+//================================================================================
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		pGenRstReg		<=	PGenRst_i;
+	end	else	begin
+		pGenRstReg		<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		case(currState)
+		IDLE	:	begin
+						if (orPGenRstReg)	begin
+							currState 	<= RST;
+							PGenRst_o	<=	pGenRstReg;
+							RstDone_o	<=	1'b1;
+						end	else begin
+							currState <= IDLE;
+							PGenRst_o	<=	0;
+							RstDone_o	<=	0;
+						end
+					end
+					
+		RST	:		begin
+						if	(RstDone_o)	begin
+							PGenRst_o	<=	0;
+							RstDone_o	<=	0;
+							currState 	<= DEL;
+						end	else begin
+							currState 	<= RST;
+							PGenRst_o	<=	0;
+							RstDone_o	<=	0;
+						end
+					end
+					
+		DEL	:		begin
+						PGenRst_o	<=	0;
+						RstDone_o	<=	0;
+						currState 	<= IDLE;
+					end
+		endcase
+	end	else	begin
+		currState	<=	IDLE;
+		PGenRst_o	<=	0;
+		RstDone_o	<=	0;
+	end
+end
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+

src/src/PulseMeas/PulseGen.v

@@ -0,0 +1,314 @@
+//`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    PulseGen 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	PulseGen	
+#(	
+	parameter	CmdRegWidth	=	32
+)
+(
+	input	Rst_i,
+	input	Clk_i,
+	input	EnPulse_i,
+	
+	input	PulsePol_i,
+	input	EnEdge_i,
+	input	[CmdRegWidth-29:0]	Mode_i,
+	input	[CmdRegWidth-1:0]	P1Del_i,
+	input	[CmdRegWidth-1:0]	P2Del_i,
+	input	[CmdRegWidth-1:0]	P3Del_i,
+	input	[CmdRegWidth-1:0]	P1Width_i,
+	input	[CmdRegWidth-1:0]	P2Width_i,
+	input	[CmdRegWidth-1:0]	P3Width_i,
+	
+	output	Pulse_o
+);	
+
+//================================================================================
+//  LOCALPARAM
+
+	localparam	IDLE	=	2'h0;
+	localparam	DELAY	=	2'h1;
+	localparam	PULSE	=	2'h2;
+	
+	localparam	DISABLED	=	8'd0;
+	localparam	SINGLE		=	8'd1;
+	localparam	DOUBLE		=	8'd2;
+	localparam	TRIPPLE		=	8'd3;
+	localparam	BURST		=	8'd4;
+	localparam	CONTINIOUS	=	8'd5;
+	
+//================================================================================
+	reg		pulse;
+	wire	[31:0]	delArray	[2:0];
+	wire	[31:0]	widthArray	[2:0];
+	
+	reg	[31:0]	pulseCnt;
+	reg	[31:0]	delayCnt;
+	reg	[31:0]	widthCnt;
+	
+	reg	[31:0]	currWidthValue;
+	reg	[31:0]	currDelValue;
+
+	reg	[1:0]	currState;
+	reg	[1:0]	nextState;
+	
+	reg		pulseDone;	
+	wire	delayDone	=	(currState	==	DELAY)?	delayCnt==currDelValue-1:1'b0;	
+	
+	wire	zeroDelay	=	(P1Del_i==0);
+	
+	reg	patternDone;
+
+	reg	enPulseR;
+	
+	wire	enPulsePos	=	(!enPulseR&EnPulse_i);
+	wire	enPulseNeg	=	(enPulseR&!EnPulse_i);
+	
+	wire	enPulse		=	(EnEdge_i)?	enPulseNeg:enPulsePos;
+	wire	enPulseEn	=	(Mode_i	!=	0)?	enPulse:1'b0;
+//================================================================================
+//  ASSIGNMENTS
+	assign	delArray	[0]	=	P1Del_i;
+	assign	delArray	[1]	=	P2Del_i;
+	assign	delArray	[2]	=	P3Del_i;
+	
+	assign	widthArray	[0]	=	P1Width_i;
+	assign	widthArray	[1]	=	P2Width_i;
+	assign	widthArray	[2]	=	P3Width_i;
+	
+	assign	Pulse_o	=	(PulsePol_i)?	~pulse:pulse;
+
+//================================================================================
+//  CODING
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		enPulseR	<=	EnPulse_i;
+	end	else	begin
+		enPulseR	<=	1'b0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(Mode_i	>=1 & Mode_i<=3)	begin	
+			if	(currState	!=	IDLE)	begin
+				delayCnt	<=	delayCnt+1;
+			end	else	begin
+				delayCnt	<=	0;
+			end
+		end	else	begin
+			if	(currState	==	DELAY)	begin
+				delayCnt	<=	delayCnt+1;
+			end	else	begin
+				delayCnt	<=	0;
+			end
+		end
+	end	else	begin
+		delayCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(currState	==	PULSE)	begin
+			widthCnt	<=	widthCnt+1;
+		end	else	begin
+			widthCnt	<=	0;
+		end
+	end	else	begin
+		widthCnt	<=	0;
+	end
+end
+
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		if	(currState	==	PULSE)	begin
+			if	(widthCnt==currWidthValue-1)	begin
+				pulseDone	=	1'b1;
+			end	else	begin
+				pulseDone	=	1'b0;
+			end
+		end	else	begin
+			pulseDone	=	1'b0;
+		end
+	end	else	begin
+		pulseDone	=	1'b0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(pulseDone)	begin
+			if	(!patternDone)	begin
+				pulseCnt	<=	pulseCnt+1;
+			end	else	begin
+				pulseCnt	<=	0;
+			end
+		end
+	end	else	begin
+		pulseCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(Mode_i	==	0)	begin
+				currDelValue	<=	0;
+				currWidthValue	<=	0;
+		end	else	begin
+			if	(Mode_i	>=1 & Mode_i<=3)	begin
+				currDelValue	<=	delArray[pulseCnt];
+				currWidthValue	<=	widthArray[pulseCnt];
+			end	else	begin
+				if	(Mode_i	==	4|Mode_i	==	5)	begin
+					if	(currState	==	IDLE)	begin
+						currDelValue	<=	delArray[0];
+						currWidthValue	<=	widthArray[0];
+					end	else	if	(currState	==	PULSE	&	pulseDone)	begin
+						currDelValue	<=	delArray[1];
+						currWidthValue	<=	widthArray[0];
+					end	
+				end
+			end
+		end
+	end	else	begin
+		currDelValue	<=	0;
+		currWidthValue	<=	0;
+	end
+end
+
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		if	(currState	!=	IDLE)	begin
+			case(Mode_i)
+				8'd0:	begin
+							patternDone	=	0;
+						end
+				8'd1:	begin
+							patternDone	=	((pulseCnt==Mode_i-1)&pulseDone);
+						end
+				8'd2:	begin
+							patternDone	=	((pulseCnt==Mode_i-1)&pulseDone);
+						end
+				8'd3:	begin
+							patternDone	=	((pulseCnt==Mode_i-1)&pulseDone);
+						end
+				8'd4:	begin
+							patternDone	=	((pulseCnt==P2Width_i-1)&pulseDone);
+						end
+				8'd5:	begin
+							patternDone	=	0;
+						end
+				default	:begin
+							patternDone	=	0;
+						end
+			endcase
+		end	else	begin
+			patternDone	=	0;
+		end
+	end	else	begin
+		patternDone	=	0;
+	end
+end
+
+	
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		currState	<=	nextState;
+	end	else	begin
+		currState	<=	IDLE;
+	end
+end
+
+always	@(*)	begin
+	nextState	=	IDLE;
+	case(currState)
+	IDLE	:	begin
+					if (enPulseEn)	begin
+						if	(zeroDelay)	begin
+							nextState = PULSE;
+						end	else begin
+							nextState = DELAY;
+						end
+					end	else	begin
+						nextState = IDLE;
+					end
+				end
+				
+	DELAY	:	begin
+					if	(delayDone)	begin
+						nextState = PULSE;
+					end	else begin
+						nextState = DELAY;
+					end
+				end
+
+	PULSE	:	begin
+					if	(pulseDone)	begin
+						if	(!patternDone)	begin
+							nextState  = DELAY;
+						end	else begin
+							nextState  = IDLE;
+						end
+					end	else	begin
+						nextState  = PULSE;
+					end
+				end
+	endcase
+end
+
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		if	(Mode_i	!=	0)	begin
+			case(currState)
+				IDLE:	begin
+							pulse	=	1'b0;
+						end
+				DELAY:	begin
+							pulse	=	1'b0;
+						end
+				PULSE:	begin
+							pulse	=	1'b1;
+						end
+				default:begin
+							pulse	=	1'b0;
+						end
+			endcase
+		end	else	begin
+			pulse	=	1'b0;
+		end	
+	end	else	begin
+		pulse	=	1'b0;
+	end
+end
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+

src/src/PulseMeas/PulseGenV2.v

@@ -0,0 +1,314 @@
+//`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    PulseGen 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	PulseGenV2	
+#(	
+	parameter	CmdRegWidth	=	32
+)
+(
+	input	Rst_i,
+	input	Clk_i,
+	input	EnPulse_i,
+	
+	input	PulsePol_i,
+	input	EnEdge_i,
+	input	[CmdRegWidth-29:0]	Mode_i,
+	input	[CmdRegWidth-1:0]	P1Del_i,
+	input	[CmdRegWidth-1:0]	P2Del_i,
+	input	[CmdRegWidth-1:0]	P3Del_i,
+	input	[CmdRegWidth-1:0]	P1Width_i,
+	input	[CmdRegWidth-1:0]	P2Width_i,
+	input	[CmdRegWidth-1:0]	P3Width_i,
+	
+	output	Pulse_o
+);	
+
+//================================================================================
+//  LOCALPARAM
+
+	localparam	IDLE	=	2'h0;
+	localparam	DELAY	=	2'h1;
+	localparam	PULSE	=	2'h2;
+	
+	localparam	DISABLED	=	8'd0;
+	localparam	SINGLE		=	8'd1;
+	localparam	DOUBLE		=	8'd2;
+	localparam	TRIPPLE		=	8'd3;
+	localparam	BURST		=	8'd4;
+	localparam	CONTINIOUS	=	8'd5;
+	
+//================================================================================
+	reg		pulse;
+	wire	[31:0]	delArray	[2:0];
+	wire	[31:0]	widthArray	[2:0];
+	
+	reg	[31:0]	pulseCnt;
+	reg	[31:0]	delayCnt;
+	reg	[31:0]	widthCnt;
+	
+	reg	[31:0]	currWidthValue;
+	reg	[31:0]	currDelValue;
+
+	reg	[1:0]	currState;
+	reg	[1:0]	nextState;
+	
+	reg		pulseDone;	
+	wire	delayDone	=	(currState	==	DELAY)?	delayCnt==currDelValue-1:1'b0;	
+	
+	wire	zeroDelay	=	(P1Del_i==0);
+	
+	reg	patternDone;
+
+	reg	enPulseR;
+	
+	wire	enPulsePos	=	(!enPulseR&EnPulse_i);
+	wire	enPulseNeg	=	(enPulseR&!EnPulse_i);
+	
+	wire	enPulse		=	(EnEdge_i)?	enPulseNeg:enPulsePos;
+	wire	enPulseEn	=	(Mode_i	!=	0)?	enPulse:1'b0;
+//================================================================================
+//  ASSIGNMENTS
+	assign	delArray	[0]	=	P1Del_i;
+	assign	delArray	[1]	=	P2Del_i;
+	assign	delArray	[2]	=	P3Del_i;
+	
+	assign	widthArray	[0]	=	P1Width_i;
+	assign	widthArray	[1]	=	P2Width_i;
+	assign	widthArray	[2]	=	P3Width_i;
+	
+	assign	Pulse_o	=	(PulsePol_i)?	~pulse:pulse;
+
+//================================================================================
+//  CODING
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		enPulseR	<=	EnPulse_i;
+	end	else	begin
+		enPulseR	<=	1'b0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(Mode_i	>=1 & Mode_i<=3)	begin	
+			if	(currState	!=	IDLE)	begin
+				delayCnt	<=	delayCnt+1;
+			end	else	begin
+				delayCnt	<=	0;
+			end
+		end	else	begin
+			if	(currState	==	DELAY)	begin
+				delayCnt	<=	delayCnt+1;
+			end	else	begin
+				delayCnt	<=	0;
+			end
+		end
+	end	else	begin
+		delayCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(currState	==	PULSE)	begin
+			widthCnt	<=	widthCnt+1;
+		end	else	begin
+			widthCnt	<=	0;
+		end
+	end	else	begin
+		widthCnt	<=	0;
+	end
+end
+
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		if	(currState	==	PULSE)	begin
+			if	(widthCnt==currWidthValue-1)	begin
+				pulseDone	=	1'b1;
+			end	else	begin
+				pulseDone	=	1'b0;
+			end
+		end	else	begin
+			pulseDone	=	1'b0;
+		end
+	end	else	begin
+		pulseDone	=	1'b0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(pulseDone)	begin
+			if	(!patternDone)	begin
+				pulseCnt	<=	pulseCnt+1;
+			end	else	begin
+				pulseCnt	<=	0;
+			end
+		end
+	end	else	begin
+		pulseCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(Mode_i	==	0)	begin
+				currDelValue	<=	0;
+				currWidthValue	<=	0;
+		end	else	begin
+			if	(Mode_i	>=1 & Mode_i<=3)	begin
+				currDelValue	<=	delArray[pulseCnt];
+				currWidthValue	<=	widthArray[pulseCnt];
+			end	else	begin
+				if	(Mode_i	==	4|Mode_i	==	5)	begin
+					if	(currState	==	IDLE)	begin
+						currDelValue	<=	delArray[0];
+						currWidthValue	<=	widthArray[0];
+					end	else	if	(currState	==	PULSE	&	pulseDone)	begin
+						currDelValue	<=	delArray[1];
+						currWidthValue	<=	widthArray[0];
+					end	
+				end
+			end
+		end
+	end	else	begin
+		currDelValue	<=	0;
+		currWidthValue	<=	0;
+	end
+end
+
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		if	(currState	!=	IDLE)	begin
+			case(Mode_i)
+				8'd0:	begin
+							patternDone	=	0;
+						end
+				8'd1:	begin
+							patternDone	=	((pulseCnt==Mode_i-1)&pulseDone);
+						end
+				8'd2:	begin
+							patternDone	=	((pulseCnt==Mode_i-1)&pulseDone);
+						end
+				8'd3:	begin
+							patternDone	=	((pulseCnt==Mode_i-1)&pulseDone);
+						end
+				8'd4:	begin
+							patternDone	=	((pulseCnt==P2Width_i-1)&pulseDone);
+						end
+				8'd5:	begin
+							patternDone	=	0;
+						end
+				default	:begin
+							patternDone	=	0;
+						end
+			endcase
+		end	else	begin
+			patternDone	=	0;
+		end
+	end	else	begin
+		patternDone	=	0;
+	end
+end
+
+	
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		currState	<=	nextState;
+	end	else	begin
+		currState	<=	IDLE;
+	end
+end
+
+always	@(*)	begin
+	nextState	=	IDLE;
+	case(currState)
+	IDLE	:	begin
+					if (enPulseEn)	begin
+						if	(zeroDelay)	begin
+							nextState = PULSE;
+						end	else begin
+							nextState = DELAY;
+						end
+					end	else	begin
+						nextState = IDLE;
+					end
+				end
+				
+	DELAY	:	begin
+					if	(delayDone)	begin
+						nextState = PULSE;
+					end	else begin
+						nextState = DELAY;
+					end
+				end
+
+	PULSE	:	begin
+					if	(pulseDone)	begin
+						if	(!patternDone)	begin
+							nextState  = DELAY;
+						end	else begin
+							nextState  = IDLE;
+						end
+					end	else	begin
+						nextState  = PULSE;
+					end
+				end
+	endcase
+end
+
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		if	(Mode_i	!=	0)	begin
+			case(currState)
+				IDLE:	begin
+							pulse	=	1'b0;
+						end
+				DELAY:	begin
+							pulse	=	1'b0;
+						end
+				PULSE:	begin
+							pulse	=	1'b1;
+						end
+				default:begin
+							pulse	=	1'b0;
+						end
+			endcase
+		end	else	begin
+			pulse	=	1'b0;
+		end	
+	end	else	begin
+		pulse	=	1'b0;
+	end
+end
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+

src/src/PulseMeas/SampleStrobeGenRstDemux.v

@@ -0,0 +1,91 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    mult_module 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	SampleStrobeGenRstDemux	
+#(	
+	parameter	CmdRegWidth		=	24,
+	parameter	PGenNum			=	7,
+	parameter	TrigPortsNum	=	6
+)
+(
+	input	Rst_i,
+	input	[CmdRegWidth-28:0]	MuxCtrl_i,
+	input	GenRst_i,
+	
+	output	[PGenNum-1:0]	RstDemuxOut_o
+);	
+
+//================================================================================
+//  LOCALPARAM
+
+//================================================================================
+//	REG/WIRE
+	reg	[PGenNum-1:0]	demuxOut;
+//================================================================================
+//  ASSIGNMENTS
+	assign	RstDemuxOut_o	=	demuxOut;
+
+//================================================================================
+//  CODING
+
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		case(MuxCtrl_i)
+			5'd0:	begin
+						demuxOut	=	{6'b000000,GenRst_i};
+					end
+			5'd1:	begin
+						demuxOut	=	{5'b00000,GenRst_i,1'b0};
+					end
+			5'd2:	begin
+						demuxOut	=	{5'b0000,GenRst_i,2'b00};
+					end
+			5'd3:	begin
+						demuxOut	=	{3'b000,GenRst_i,3'b000};
+					end
+			5'd4:	begin
+						demuxOut	=	{2'b00,GenRst_i,5'b0000};
+					end
+			5'd5:	begin
+						demuxOut	=	{1'b0,GenRst_i,5'b00000};
+					end
+			5'd6:	begin
+						demuxOut	=	{GenRst_i,6'b000000};
+					end
+			default	:begin
+						demuxOut	=	7'b0000000;
+					end
+		endcase
+	end	else	begin
+		demuxOut	=	0;
+	end
+end
+endmodule
+
+
+
+
+
+
+
+
+
+
+

src/src/PulseMeas/StartAfterGainSel.v

@@ -0,0 +1,103 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 		Churbanov S.
+// 
+// Create Date:    15:24:31 08/20/2019 
+// Design Name: 
+// Module Name:  
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.02 - File Modified
+// Additional Comments: 16.09.2019 file modified in assotiate with task.
+//
+//////////////////////////////////////////////////////////////////////////////////
+module StartAfterGainSel
+#(	
+	parameter	ChNum	=	4
+)	
+(
+	input	Rst_i,	
+	input	[ChNum-1:0]	MeasStart_i,
+	input	[ChNum-1:0]	GainCtrl_i,
+	
+	output	MeasStart_o
+);
+
+//================================================================================
+//  LOCALPARAMS
+
+//================================================================================
+//  REG/WIRE
+	reg	measStart;
+//================================================================================
+//  ASSIGNMENTS
+	assign	MeasStart_o	=	measStart;
+//================================================================================
+//  CODING
+
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		case(GainCtrl_i)
+			4'd0:	begin
+						measStart	=	&MeasStart_i;
+					end
+			4'd1:	begin
+						measStart	=	MeasStart_i[0];
+					end
+			4'd2:	begin
+						measStart	=	MeasStart_i[1];
+					end
+			4'd3:	begin
+						measStart	=	MeasStart_i[0]&MeasStart_i[1];
+					end
+			4'd4:	begin
+						measStart	=	&MeasStart_i[2];
+					end
+			4'd5:	begin
+						measStart	=	MeasStart_i[0]&MeasStart_i[2];
+					end
+			4'd6:	begin
+						measStart	=	MeasStart_i[1]&MeasStart_i[2];
+					end
+			4'd7:	begin
+						measStart	=	MeasStart_i[0]&MeasStart_i[1]&MeasStart_i[2];
+					end
+			4'd8:	begin
+						measStart	=	MeasStart_i[3];
+					end
+			4'd9:	begin
+						measStart	=	MeasStart_i[0]&MeasStart_i[3];
+					end
+			4'd10:	begin
+						measStart	=	MeasStart_i[1]&MeasStart_i[3];
+					end
+			4'd11:	begin
+						measStart	=	MeasStart_i[0]&MeasStart_i[1]&MeasStart_i[3];
+					end
+			4'd12:	begin
+						measStart	=	MeasStart_i[2]&MeasStart_i[3];
+					end
+			4'd13:	begin
+						measStart	=	MeasStart_i[0]&MeasStart_i[2]&MeasStart_i[3];
+					end
+			4'd14:	begin
+						measStart	=	MeasStart_i[1]&MeasStart_i[2]&MeasStart_i[3];
+					end
+			4'd15:	begin
+						measStart	=	&MeasStart_i;
+					end		
+			default:	begin
+							measStart	=	&MeasStart_i;
+						end
+		endcase
+	end
+end
+
+endmodule

src/src/PulseMeas/TrigInt2Mux.v

@@ -0,0 +1,67 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    mult_module 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	TrigInt2Mux	
+#(	
+	parameter	PGenNum			=	7
+)
+(
+	input	Rst_i,
+	
+	input	[3:0]	MuxCtrl_i,
+	input	[PGenNum-1:0]	PulseBus_i,
+	
+	output	MuxOut_o
+);	
+
+//================================================================================
+//  LOCALPARAM
+
+//================================================================================
+//	REG/WIRE
+	reg		muxOut;
+	
+//================================================================================
+//  ASSIGNMENTS
+	assign	MuxOut_o	=	muxOut;
+
+//================================================================================
+//  CODING
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		muxOut	=	PulseBus_i[MuxCtrl_i];
+	end	else	begin
+		muxOut	=	1'b0;
+	end
+end
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+

src/src/Sim/S5243TopPulseProfileTb.v

@@ -0,0 +1,686 @@
+`timescale 1ns / 1ps
+
+//=============================================================================================================
+
+//	Тестовая конфигурация:
+//
+//	Режим измерения "Точка в импульсе".
+//	Количество измерений = 1.
+//	Выбраный фильтр = 2МГц.
+//
+//	PG1	->	Reference Sequense Generator.	|	Шаблон 1 имп.
+//	PG2	->	модулятор.						|	Шаблон 1 имп.
+//	PG3	->	Sample Strobe Generator.		|	Шаблон 1 имп.
+//	PG4	->	Gating Generator.				|	Шаблон 1 имп.
+//	
+//	Настройки мультиплексоров генераторов:
+//	PG1MUX_OUT	->	INT_TRIG.
+//	PG2MUX_OUT	->	PG1. Для всех генераторов кроме PG1 сигналом начала работы является выход PG1.
+//	PG3MUX_OUT	->	PG1.
+//	PG4MUX_OUT	->	PG1.
+//	PG5MUX_OUT	->	PG1.
+//	PG6MUX_OUT	->	PG1.
+//	PG7MUX_OUT	->	PG1.
+//	
+//	Настройки остальных мультиплексоров:
+//	MODMUX_OUT			->	PG2.
+//	GATINGMUX_OUT		->	PG4.
+//	SAMPLSTROBEMUX_OUT	->	PG3.
+//	EXTSTARTMUX			->	DSPSTART.
+
+//=============================================================================================================
+module S5243TopPulseProfileTb;
+	
+	localparam	[4:0]	EP1MUXCMD	=	5'd14;
+	localparam	[4:0]	EP2MUXCMD	=	5'd1;
+	localparam	[4:0]	EP3MUXCMD	=	5'd1;
+	localparam	[4:0]	EP4MUXCMD	=	5'd1;
+	localparam	[4:0]	EP5MUXCMD	=	5'd1;
+	localparam	[4:0]	EP6MUXCMD	=	5'd1;
+	
+	localparam	[4:0]	PG1MUXCMD	=	5'd13;
+	localparam	[4:0]	PG2MUXCMD	=	5'd0;
+	localparam	[4:0]	PG3MUXCMD	=	5'd18;
+	localparam	[4:0]	PG4MUXCMD	=	5'd18;
+	localparam	[4:0]	PG5MUXCMD	=	5'd0;
+	localparam	[4:0]	PG6MUXCMD	=	5'd0;
+	localparam	[4:0]	PG7MUXCMD	=	5'd0;
+	
+	localparam	[2:0]	PG1MODE	=	3'd5;
+	localparam	[2:0]	PG2MODE	=	3'd1;
+	localparam	[2:0]	PG3MODE	=	3'd3;
+	localparam	[2:0]	PG4MODE	=	3'd4;
+	localparam	[2:0]	PG5MODE	=	3'd0;
+	localparam	[2:0]	PG6MODE	=	3'd0;
+	localparam	[2:0]	PG7MODE	=	3'd3;
+	
+	localparam	PG1POL	=	1'b0;
+	localparam	PG2POL	=	1'b0;
+	localparam	PG3POL	=	1'b0;
+	localparam	PG4POL	=	1'b0;
+	localparam	PG5POL	=	1'b0;
+	localparam	PG6POL	=	1'b0;
+	localparam	PG7POL	=	1'b0;
+	
+	localparam	[4:0]	EXTTRIGMUXCMD	=	5'd15;
+	localparam	[4:0]	DSPTRIGINCMD	=	5'h8;
+	localparam	[4:0]	MUXSLOWMODCMD	=	5'd1;
+	localparam	[4:0]	MUXFASTMODCMD	=	5'd1;
+	localparam	[4:0]	GATINGMUXCMD	=	5'd2;
+	localparam	[4:0]	SMPLSTRBMUXCMD	=	5'd3;
+	
+	//COMMANDS	FOR REG_MAP
+	parameter	[31:0]	MeasCmdBypass	=	{8'h11,8'h0,8'h63,8'h1};
+	// parameter	[31:0]	MeasCmdFft 		=	{8'h11,8'h0,8'h63,7'h5,1'b1};
+	// parameter	[31:0]	MeasCmd 		=	{8'h11,8'h0,8'h53,8'h0};
+	// parameter	[31:0]	MeasCmd =	{8'h11,8'h3e,8'h63,8'h0};
+	parameter	[31:0]	AdcCtrl =	{8'h12,24'h2};
+	parameter	[31:0]	SensCtrlCmd =	{1'b0,27'h0,4'b1};
+	// parameter	[31:0]	DitherCmd 	= {8'h0E,24'h100192};
+	parameter	[31:0]	DitherCmd 	= {8'h0E,8'd9,4'h0,4'h1,4'd11,4'h3};
+	parameter	[31:0]	IfFtwH 	=	{8'h15,16'h0,8'h40};
+	parameter	[31:0]	IfFtwL 	=	{8'h16,24'h000000};
+	parameter	[31:0]	FilterCorrCmdH 		=	{8'h17,24'hD70A3D};
+	parameter	[31:0]	FilterCorrCmdL 		=	{8'h18,24'hD70A3D};
+	
+	//PG7 Cmd
+	parameter	[31:0]	PG7P1DelayRegCmd	=	{8'h20,24'd0};
+	parameter	[31:0]	PG7P2DelayRegCmd	=	{8'h21,24'd1};
+	parameter	[31:0]	PG7P3DelayRegCmd	=	{8'h22,24'd5};
+	parameter	[31:0]	PG7P123DelayRegCmd	=	{8'h23,24'd15};
+	parameter	[31:0]	PG7P1WidthRegCmd	=	{8'h24,24'd1};
+	parameter	[31:0]	PG7P2WidthRegCmd	=	{8'h25,24'd3};
+	parameter	[31:0]	PG7P3WidthRegCmd	=	{8'h26,24'd5};
+	parameter	[31:0]	PG7P123WidthRegCmd	=	{8'h27,24'd0};
+
+	//PG1 Cmd
+	parameter	[31:0]	PG1P1DelayRegCmd	=	{8'h28,24'd0};
+	parameter	[31:0]	PG1P2DelayRegCmd	=	{8'h29,24'd400};
+	parameter	[31:0]	PG1P3DelayRegCmd	=	{8'h2a,24'd0};
+	parameter	[31:0]	PG1P123DelayRegCmd	=	{8'h2b,24'd0};
+	parameter	[31:0]	PG1P1WidthRegCmd	=	{8'h2c,24'd1};
+	parameter	[31:0]	PG1P2WidthRegCmd	=	{8'h2d,24'd0};
+	parameter	[31:0]	PG1P3WidthRegCmd	=	{8'h2e,24'd0};
+	parameter	[31:0]	PG1P123WidthRegCmd	=	{8'h2f,24'd0};
+	
+	//PG2 Cmd
+	parameter	[31:0]	PG2P1DelayRegCmd	=	{8'h20,24'd0};
+	parameter	[31:0]	PG2P2DelayRegCmd	=	{8'h21,24'd1};
+	parameter	[31:0]	PG2P3DelayRegCmd	=	{8'h22,24'd5};
+	parameter	[31:0]	PG2P123DelayRegCmd	=	{8'h23,24'd15};
+	parameter	[31:0]	PG2P1WidthRegCmd	=	{8'h24,24'd1};
+	parameter	[31:0]	PG2P2WidthRegCmd	=	{8'h25,24'd3};
+	parameter	[31:0]	PG2P3WidthRegCmd	=	{8'h26,24'd5};
+	parameter	[31:0]	PG2P123WidthRegCmd	=	{8'h27,24'd0};
+	
+	//PG3 Cmd
+	parameter	[31:0]	PG3P1DelayRegCmd	=	{8'h20,24'd0};
+	parameter	[31:0]	PG3P2DelayRegCmd	=	{8'h21,24'd1};
+	parameter	[31:0]	PG3P3DelayRegCmd	=	{8'h22,24'd5};
+	parameter	[31:0]	PG3P123DelayRegCmd	=	{8'h23,24'd15};
+	parameter	[31:0]	PG3P1WidthRegCmd	=	{8'h24,24'd1};
+	parameter	[31:0]	PG3P2WidthRegCmd	=	{8'h25,24'd3};
+	parameter	[31:0]	PG3P3WidthRegCmd	=	{8'h26,24'd5};
+	parameter	[31:0]	PG3P123WidthRegCmd	=	{8'h27,24'd0};
+	
+	//PG4 Cmd
+	parameter	[31:0]	PG4P1DelayRegCmd	=	{8'h40,24'd0};
+	parameter	[31:0]	PG4P2DelayRegCmd	=	{8'h41,24'd18};
+	parameter	[31:0]	PG4P3DelayRegCmd	=	{8'h42,24'd0};
+	parameter	[31:0]	PG4P123DelayRegCmd	=	{8'h43,24'd0};
+	parameter	[31:0]	PG4P1WidthRegCmd	=	{8'h44,24'd1};
+	parameter	[31:0]	PG4P2WidthRegCmd	=	{8'h45,24'd10};
+	parameter	[31:0]	PG4P3WidthRegCmd	=	{8'h46,24'd7};
+	parameter	[31:0]	PG4P123WidthRegCmd	=	{8'h47,24'd0};
+	
+	//PG5 Cmd
+	parameter	[31:0]	PG5P1DelayRegCmd	=	{8'h48,24'd0};
+	parameter	[31:0]	PG5P2DelayRegCmd	=	{8'h49,24'd0};
+	parameter	[31:0]	PG5P3DelayRegCmd	=	{8'h4a,24'd0};
+	parameter	[31:0]	PG5P123DelayRegCmd	=	{8'h4b,24'd0};
+	parameter	[31:0]	PG5P1WidthRegCmd	=	{8'h4c,24'd0};
+	parameter	[31:0]	PG5P2WidthRegCmd	=	{8'h4d,24'd0};
+	parameter	[31:0]	PG5P3WidthRegCmd	=	{8'h4e,24'd0};
+	parameter	[31:0]	PG5P123WidthRegCmd	=	{8'h4f,24'd0};
+	
+	//PG6 Cmd
+	parameter	[31:0]	PG6P1DelayRegCmd	=	{8'h50,24'd0};
+	parameter	[31:0]	PG6P2DelayRegCmd	=	{8'h51,24'd5};
+	parameter	[31:0]	PG6P3DelayRegCmd	=	{8'h52,24'd15};
+	parameter	[31:0]	PG6P123DelayRegCmd	=	{8'h53,24'd0};
+	parameter	[31:0]	PG6P1WidthRegCmd	=	{8'h54,24'd1};
+	parameter	[31:0]	PG6P2WidthRegCmd	=	{8'h55,24'd3};
+	parameter	[31:0]	PG6P3WidthRegCmd	=	{8'h56,24'd5};
+	parameter	[31:0]	PG6P123WidthRegCmd	=	{8'h57,24'd0};
+	
+	parameter	[31:0]	MeasNum0RegCmd		=	{8'h58,24'd10};
+	parameter	[31:0]	MeasNum1RegCmd		=	{8'h59,MUXSLOWMODCMD,MUXFASTMODCMD,DSPTRIGINCMD,25'd0};
+	parameter	[31:0]	PGMode0RegCmd		=	{8'h0b,3'b0,PG7MODE,PG6MODE,PG5MODE,PG4MODE,PG3MODE,PG2MODE,PG1MODE};
+	parameter	[31:0]	PGMode1RegCmd		=	{8'h1b,7'b0000000,PG7POL,PG6POL,PG5POL,PG4POL,PG3POL,PG2POL,PG1POL,10'h0};
+	
+	parameter	[31:0]	MuxCtrl1RegCmd	=	{8'h1c,4'h0,PG7MUXCMD,PG6MUXCMD,PG5MUXCMD,PG4MUXCMD};
+	parameter	[31:0]	MuxCtrl2RegCmd	=	{8'h1d,4'h0,PG3MUXCMD,PG2MUXCMD,PG1MUXCMD,SMPLSTRBMUXCMD};
+	parameter	[31:0]	MuxCtrl3RegCmd	=	{8'h1e,4'h0,GATINGMUXCMD,EXTTRIGMUXCMD,EP2MUXCMD,EP1MUXCMD};
+	parameter	[31:0]	MuxCtrl4RegCmd	=	{8'h1f,4'h0,EP6MUXCMD,EP5MUXCMD,EP4MUXCMD,EP3MUXCMD};
+	
+	//=================================================================================================================================================================================================================
+	
+	reg		Clk41;
+	reg		Clk50;
+	reg		Clk70;
+	
+	reg	[31:0]	tb_cnt=4'd0;
+	reg	rst;
+	reg	mosi_i	=	1'b0;
+	reg	Miso_i	=	1'b0;
+	reg	ss_i;
+	reg	clk_i	=	1'b0;
+	
+	
+	reg	[31:0]	DspSpiData;
+	reg		startCalcCmdReg;
+						
+	wire	[17:0]	cos_value;	
+	wire	[17:0]	sin_value;				
+
+	wire	ExtDspTrigPos0	=	(tb_cnt	>=	180	&&	tb_cnt	<=	181)?	1'b1:1'b0;
+	wire	ExtDspTrigNeg0	=	(tb_cnt	>=	180	&&	tb_cnt	<=	181)?	1'b0:1'b1;
+	
+	wire	ExtTrigger0		=	ExtDspTrigNeg0;
+	
+	wire	TrigFromDsp		=	(tb_cnt	>=	1100	&&	tb_cnt	<=	1101)?	1'b1:1'b0;
+	wire	endMeas;
+	reg	[31:0]	cmdCnt;
+	
+	reg	trig0;
+	reg	trig1;
+	
+	wire	trig0R;
+    wire	trig1R;
+	
+	assign	trig0R	=	trig0;
+    assign	trig1R	=	trig1;
+	
+//==========================================================================================
+//clocks gen
+	always	#10 Clk50	=	~Clk50;
+	always	#(14.285714285714/2) Clk70	=	~Clk70;
+	always	#10 clk_i	=	~clk_i;
+	always	#(24.390243902439/2)	Clk41	=	~Clk41;
+	
+	wire	sck_i;	
+//==========================================================================================
+initial begin
+	Clk50	=	1'b1;
+	Clk70	=	1'b1;
+	rst		=	1'b1;
+	Clk41	=	1'b0;
+	trig0	=	1'b0;
+	trig1	=	1'b0;
+#100;
+	rst		=	1'b0;
+#400;
+	Clk41	=	1'b0;
+end		
+	
+reg	endMeasReg;
+always	@(posedge	Clk41)	begin
+	endMeasReg	<=	endMeas;
+end
+
+wire	endMeasNeg	=	!endMeas&endMeasReg;
+
+always	@(posedge	Clk70)	begin
+	if	(!rst)	begin
+		if	(!endMeas)	begin
+			// if	(tb_cnt	==	3550	|	tb_cnt	==	3950	|tb_cnt	==	4505)	begin
+			if	(tb_cnt	==	3550)	begin
+				startCalcCmdReg	<=	1'b1;
+			end	
+		end	else	begin
+			startCalcCmdReg	<=	1'b0;
+		end
+	end	else	begin
+		startCalcCmdReg	<=	1'b0;
+	end
+end
+
+always	@(negedge	Clk41)	begin
+	if	(!rst)		begin
+		tb_cnt	<=	tb_cnt+1;
+	end	else	begin
+		tb_cnt	<=	0;
+	end
+end
+
+wire	Adc1DataDa0P;
+wire	Adc1DataDa1P;
+
+// wire	[31:0]	test	=	32'h2351eb85;
+wire	[31:0]	test	=	32'h40000000;
+CordicNco		
+#(	.ODatWidth	(18),
+	.PhIncWidth	(32),
+	.IterNum	(10),
+	.EnSinN		(0))
+ncoInst
+(
+	.Clk_i				(Clk50),
+	.Rst_i				(rst),
+	.Val_i				(1'b1),
+	.PhaseInc_i			(test),
+	.WindVal_i			(1'b1),
+	.WinType_i			(),
+	.Wind_o				(),
+	.Sin_o				(sin_value),
+	.Cos_o				(cos_value),
+	.Val_o				()
+);
+
+
+S5243Top MasterFpga 
+(
+	.ClkP_i				(Clk50),
+	.ClkN_i				(~Clk50),
+	.Led_o				(),
+//------------------------------------------	
+    .Adc1FclkP_i		(),		
+    .Adc1FclkN_i		(),		
+
+    .Adc1DataDa0P_i		(Adc1DataDa0P),
+	.Adc1DataDa0N_i		(~Adc1DataDa0P),		
+    .Adc1DataDa1P_i		(Adc1DataDa1P),
+    .Adc1DataDa1N_i		(~Adc1DataDa1P),
+
+	.Adc1DataDb0P_i		(Adc1DataDa0P),
+    .Adc1DataDb0N_i		(~Adc1DataDa0P),		
+    .Adc1DataDb1P_i		(Adc1DataDa1P),
+    .Adc1DataDb1N_i		(~Adc1DataDa1P),
+//------------------------------------------	
+    .Adc2FclkP_i		(),		
+    .Adc2FclkN_i		(),		
+
+    .Adc2DataDa0P_i		(1'b1),
+    .Adc2DataDa0N_i		(1'b0),		
+    .Adc2DataDa1P_i		(1'b1),
+    .Adc2DataDa1N_i		(1'b0),
+  
+	.Adc2DataDb0P_i		(1'b1),
+    .Adc2DataDb0N_i		(1'b0),		
+    .Adc2DataDb1P_i		(1'b1),
+    .Adc2DataDb1N_i		(1'b0),
+//------------------------------------------
+	.Adc1InitMosi_o		(),
+	.Adc2InitMosi_o		(),
+	
+	.Adc1InitClk_o		(),
+	.Adc2InitClk_o		(),
+	
+	.Adc1InitCs_o		(),
+	.Adc2InitCs_o		(),
+	
+	.Adc1InitRst_o		(),
+	.Adc2InitRst_o		(),
+	
+	
+	.DitherCtrlCh1_o	(),
+	.DitherCtrlCh2_o	(),
+//------------------------------------------	
+	
+	.Mosi_i				(mosi_i),
+	.Sck_i				(~sck_i),
+	.Ss_i				(ss_i),
+	.Miso_i				(),
+	.Miso_o				(),
+	
+	.LpOutClk_o			(),
+	.LpOutFs_o			(),			
+	.LpOutData_o		(),
+	
+	//fpga-dsp signals
+	.StartMeas_i		(startCalcCmdReg),
+	.EndMeas_o			(endMeas),
+	
+	.TimersClk_o		(),
+	
+	.Trig6to1_io		(),	
+	.Trig6to1Dir_o		(),	
+	
+	.DspTrigOut_i		(),				//Trig from DSP
+	.DspTrigIn_o		(),				//Trig To DSP
+	
+	.Overload_o			(),
+	
+	.PortSel_o			(),
+	
+	//mod out line
+	
+	.Mod_o				(),	
+	
+	//gain lines
+	.DspReadyForRx_i		(1'b0),
+	.AmpEn_o				(),	//	0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
+	.AdcData_i				(sin_value[17-:14])
+	// .AdcData_i			(Data_i)
+);
+
+parameter	IDLE	=	2'h0;
+parameter	CMD		=	2'h1;
+parameter	TX		=	2'h2;
+parameter	PAUSE	=	2'h3;
+
+reg	[1:0]	txCurrState;
+reg	[1:0]	txNextState;
+
+wire	txWork	=	tb_cnt	>=	23;
+// wire	txStop	=	(cmdCnt	>=	90)	&	(cmdCnt	>=	70)	&	(cmdCnt	>=	71);
+wire	txStop	=	(cmdCnt	>=	251);
+
+
+reg	[6:0]	txCnt;
+reg	[3:0]	pauseCnt;
+
+always	@(posedge	Clk41)	begin
+	if	(!rst)	begin
+		if	(txCurrState	==	CMD)	begin
+			if	(!txStop)	begin
+				cmdCnt	<=	cmdCnt+1;
+			end
+		end
+	end	else	begin
+		cmdCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk41)	begin
+	if	(!rst)	begin
+		if	(txCurrState	==	TX)	begin
+			txCnt	<=	txCnt+1;
+		end	else	begin
+			txCnt	<=	0;
+		end
+	end	else	begin
+		txCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk41)	begin
+	if	(!rst)	begin
+		if	(txCurrState	==	PAUSE)	begin
+			pauseCnt	<=	pauseCnt+1;
+		end	else	begin
+			pauseCnt	<=	0;
+		end
+	end	else	begin
+		pauseCnt	<=	0;
+	end
+end
+	
+
+always	@(posedge	Clk41)	begin
+	if	(txCurrState	==	CMD)	begin
+		if	(cmdCnt	==	0)	begin
+			DspSpiData		<=	MeasCmdBypass;
+		end	else	if	(cmdCnt	==	1)	begin
+			DspSpiData		<=	IfFtwH;
+		end	else	if	(cmdCnt	==	2)	begin
+			DspSpiData		<=	IfFtwL;
+		end	else	if	(cmdCnt	==	3)	begin
+			DspSpiData		<=	FilterCorrCmdH;
+		end	else	if	(cmdCnt	==	4)	begin
+			DspSpiData		<=	FilterCorrCmdL;
+		end	else	if	(cmdCnt	==	5)	begin
+			DspSpiData		<=	PG1P1DelayRegCmd;
+		end	else	if	(cmdCnt	==	6)	begin
+			DspSpiData		<=	PG1P2DelayRegCmd;
+		end	else	if	(cmdCnt	==	7)	begin
+			DspSpiData		<=	PG1P3DelayRegCmd;
+		end	else	if	(cmdCnt	==	8)	begin
+			DspSpiData		<=	PG1P123DelayRegCmd;
+		end	else	if	(cmdCnt	==	9)	begin
+			DspSpiData		<=	PG1P1WidthRegCmd;
+		end	else	if	(cmdCnt	==	10)	begin
+			DspSpiData		<=	PG1P2WidthRegCmd;
+		end	else	if	(cmdCnt	==	11)	begin
+			DspSpiData		<=	PG1P3WidthRegCmd;
+		end	else	if	(cmdCnt	==	12)	begin
+			DspSpiData		<=	PG1P123WidthRegCmd;
+		end	else	if	(cmdCnt	==	13)	begin
+			DspSpiData		<=	PG2P1DelayRegCmd;
+		end	else	if	(cmdCnt	==	14)	begin
+			DspSpiData		<=	PG2P2DelayRegCmd;
+		end	else	if	(cmdCnt	==	15)	begin
+			DspSpiData		<=	PG2P3DelayRegCmd;	
+		end	else	if	(cmdCnt	==	16)	begin
+			DspSpiData		<=	PG2P123DelayRegCmd;
+		end	else	if	(cmdCnt	==	17)	begin
+			DspSpiData		<=	PG2P1WidthRegCmd;
+		end	else	if	(cmdCnt	==	18)	begin
+			DspSpiData		<=	PG2P2WidthRegCmd;
+		end	else	if	(cmdCnt	==	19)	begin
+			DspSpiData		<=	PG2P3WidthRegCmd;
+		end	else	if	(cmdCnt	==	20)	begin
+			DspSpiData		<=	PG2P123WidthRegCmd;
+		end	else	if	(cmdCnt	==	21)	begin
+			DspSpiData		<=	PG3P1DelayRegCmd;
+		end	else	if	(cmdCnt	==	22)	begin
+			DspSpiData		<=	PG3P2DelayRegCmd;
+		end	else	if	(cmdCnt	==	23)	begin
+			DspSpiData		<=	PG3P3DelayRegCmd;	
+		end	else	if	(cmdCnt	==	24)	begin
+			DspSpiData		<=	PG3P123DelayRegCmd;
+		end	else	if	(cmdCnt	==	25)	begin
+			DspSpiData		<=	PG3P1WidthRegCmd;
+		end	else	if	(cmdCnt	==	26)	begin
+			DspSpiData		<=	PG3P2WidthRegCmd;
+		end	else	if	(cmdCnt	==	27)	begin
+			DspSpiData		<=	PG3P3WidthRegCmd;
+		end	else	if	(cmdCnt	==	28)	begin
+			DspSpiData		<=	PG3P123WidthRegCmd;
+		end	else	if	(cmdCnt	==	29)	begin
+			DspSpiData		<=	PG4P1DelayRegCmd;
+		end	else	if	(cmdCnt	==	30)	begin
+			DspSpiData		<=	PG4P2DelayRegCmd;
+		end	else	if	(cmdCnt	==	31)	begin
+			DspSpiData		<=	PG4P3DelayRegCmd;	
+		end	else	if	(cmdCnt	==	32)	begin
+			DspSpiData		<=	PG4P123DelayRegCmd;
+		end	else	if	(cmdCnt	==	33)	begin
+			DspSpiData		<=	PG4P1WidthRegCmd;
+		end	else	if	(cmdCnt	==	34)	begin
+			DspSpiData		<=	PG4P2WidthRegCmd;
+		end	else	if	(cmdCnt	==	35)	begin
+			DspSpiData		<=	PG4P3WidthRegCmd;
+		end	else	if	(cmdCnt	==	36)	begin
+			DspSpiData		<=	PG4P123WidthRegCmd;
+		end	else	if	(cmdCnt	==	37)	begin
+			DspSpiData		<=	PG5P1DelayRegCmd;
+		end	else	if	(cmdCnt	==	38)	begin
+			DspSpiData		<=	PG5P2DelayRegCmd;
+		end	else	if	(cmdCnt	==	39)	begin
+			DspSpiData		<=	PG5P3DelayRegCmd;	
+		end	else	if	(cmdCnt	==	40)	begin
+			DspSpiData		<=	PG5P123DelayRegCmd;
+		end	else	if	(cmdCnt	==	41)	begin
+			DspSpiData		<=	PG5P1WidthRegCmd;
+		end	else	if	(cmdCnt	==	42)	begin
+			DspSpiData		<=	PG5P2WidthRegCmd;
+		end	else	if	(cmdCnt	==	43)	begin
+			DspSpiData		<=	PG5P3WidthRegCmd;
+		end	else	if	(cmdCnt	==	44)	begin
+			DspSpiData		<=	PG5P123WidthRegCmd;
+		end	else	if	(cmdCnt	==	45)	begin
+			DspSpiData		<=	PG6P1DelayRegCmd;
+		end	else	if	(cmdCnt	==	46)	begin
+			DspSpiData		<=	PG6P2DelayRegCmd;
+		end	else	if	(cmdCnt	==	47)	begin
+			DspSpiData		<=	PG6P3DelayRegCmd;	
+		end	else	if	(cmdCnt	==	48)	begin
+			DspSpiData		<=	PG6P123DelayRegCmd;
+		end	else	if	(cmdCnt	==	49)	begin
+			DspSpiData		<=	PG6P1WidthRegCmd;
+		end	else	if	(cmdCnt	==	50)	begin
+			DspSpiData		<=	PG6P2WidthRegCmd;
+		end	else	if	(cmdCnt	==	51)	begin
+			DspSpiData		<=	PG6P3WidthRegCmd;
+		end	else	if	(cmdCnt	==	52)	begin
+			DspSpiData		<=	PG6P123WidthRegCmd;
+		end	else	if	(cmdCnt	==	53)	begin
+			DspSpiData		<=	PG7P1DelayRegCmd;
+		end	else	if	(cmdCnt	==	54)	begin
+			DspSpiData		<=	PG7P2DelayRegCmd;
+		end	else	if	(cmdCnt	==	55)	begin
+			DspSpiData		<=	PG7P3DelayRegCmd;	
+		end	else	if	(cmdCnt	==	56)	begin
+			DspSpiData		<=	PG7P123DelayRegCmd;
+		end	else	if	(cmdCnt	==	57)	begin
+			DspSpiData		<=	PG7P1WidthRegCmd;
+		end	else	if	(cmdCnt	==	58)	begin
+			DspSpiData		<=	PG7P2WidthRegCmd;
+		end	else	if	(cmdCnt	==	59)	begin
+			DspSpiData		<=	PG7P3WidthRegCmd;
+		end	else	if	(cmdCnt	==	60)	begin
+			DspSpiData		<=	DitherCmd;
+		end	else	if	(cmdCnt	==	61)	begin
+			DspSpiData		<=	MeasNum0RegCmd;
+		end else	if	(cmdCnt	==	62)	begin
+			DspSpiData		<=	MeasNum1RegCmd;
+		end else	if	(cmdCnt	==	63)	begin
+			DspSpiData		<=	PGMode0RegCmd;
+		end	else	if	(cmdCnt	==	64)	begin
+			DspSpiData		<=	PGMode1RegCmd;
+		end	else	if	(cmdCnt	==	65)	begin
+			DspSpiData		<=	MuxCtrl1RegCmd;
+		end	else	if	(cmdCnt	==	66)	begin
+			DspSpiData		<=	MuxCtrl2RegCmd;
+		end	else	if	(cmdCnt	==	67)	begin
+			DspSpiData		<=	MuxCtrl3RegCmd;
+		end	else	if	(cmdCnt	==	68)	begin
+			DspSpiData		<=	AdcCtrl;
+		end	else	if	(cmdCnt	==	99)	begin
+			DspSpiData		<=	{8'h58,24'd100};
+		end	else	begin
+			DspSpiData	<=	32'hfffffff;
+		end
+	end	else	if	(txCurrState	==	TX)	begin
+		DspSpiData	<=	DspSpiData<<1;
+	end
+end
+
+always	@(posedge Clk41)	begin
+	if	(txCurrState	==	TX)	begin
+		if	(txCnt	>=	7'd0)	begin
+			mosi_i	<=	DspSpiData[31];
+		end	else	begin
+			mosi_i	<=	1'b1;
+		end
+	end	else	begin
+		mosi_i	<=	1'b1;
+	end
+end
+
+always	@(posedge	Clk41)	begin
+	if	(txCurrState	==	TX)	begin
+		ss_i	<=	1'b0;
+	end	else	begin
+		ss_i	<=	1'b1;
+	end
+end
+
+assign	sck_i	=	Clk41;
+
+always	@(posedge	Clk41)	begin
+	if	(rst)	begin
+		txCurrState	<=	IDLE;
+	end	else	begin
+		txCurrState	<=	txNextState;
+	end
+end
+
+
+always @(*) begin
+	txNextState	=	IDLE;
+	case(txCurrState)
+	IDLE	:	begin
+					if (txWork)	begin
+						txNextState = CMD;
+					end	else begin
+						txNextState = IDLE;
+					end
+				end
+				
+	CMD	:		begin
+					if (!txStop)	begin
+						txNextState = TX;
+					end	else begin
+						txNextState = IDLE;
+					end
+				end
+
+	TX		:	begin
+					if (txCnt==6'd31) begin
+						txNextState  = PAUSE;
+					end	else begin
+						txNextState  = TX;
+					end
+				end
+        
+	PAUSE	:	begin
+					if (pauseCnt==4'd10) begin
+						txNextState  = CMD;
+					end	else begin
+						txNextState  = PAUSE;
+					end
+				end
+	endcase
+end
+
+	reg [13:0] Data_i;
+	real pi = 3.14159265358;
+	real phase = 0;
+	real phaseInc = 0.001;
+	real signal;
+	always @ (posedge Clk50)
+		begin
+			if (tb_cnt >= 4505)
+				begin
+					phase = phase + phaseInc;
+					phaseInc <= phaseInc + 0.0005;
+					signal = $sin(2*pi*phase);
+					Data_i = 2**12 * signal;
+				end
+			else
+				Data_i = 0;
+		end
+		
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

src/src/Sim/S5243TopSpectrumTb.v

@@ -0,0 +1,494 @@
+`timescale 1ns / 1ps
+
+//=============================================================================================================
+
+//	Тестовая конфигурация:
+//
+//	Режим измерения "Точка в импульсе".
+//	Количество измерений = 1.
+//	Выбраный фильтр = 2МГц.
+//
+//	PG1	->	Reference Sequense Generator.	|	Шаблон 1 имп.
+//	PG2	->	модулятор.						|	Шаблон 1 имп.
+//	PG3	->	Sample Strobe Generator.		|	Шаблон 1 имп.
+//	PG4	->	Gating Generator.				|	Шаблон 1 имп.
+//	
+//	Настройки мультиплексоров генераторов:
+//	PG1MUX_OUT	->	INT_TRIG.
+//	PG2MUX_OUT	->	PG1. Для всех генераторов кроме PG1 сигналом начала работы является выход PG1.
+//	PG3MUX_OUT	->	PG1.
+//	PG4MUX_OUT	->	PG1.
+//	PG5MUX_OUT	->	PG1.
+//	PG6MUX_OUT	->	PG1.
+//	PG7MUX_OUT	->	PG1.
+//	
+//	Настройки остальных мультиплексоров:
+//	MODMUX_OUT			->	PG2.
+//	GATINGMUX_OUT		->	PG4.
+//	SAMPLSTROBEMUX_OUT	->	PG3.
+//	EXTSTARTMUX			->	DSPSTART.
+
+//=============================================================================================================
+module S5243TopSpectrumTb;
+
+	localparam	[4:0]	EXTTRIGMUXCMD	=	5'd15;
+	localparam	[4:0]	DSPTRIGINCMD	=	5'h8;
+	localparam	[4:0]	MUXSLOWMODCMD	=	5'd1;
+	localparam	[4:0]	MUXFASTMODCMD	=	5'd1;
+	localparam	[4:0]	GATINGMUXCMD	=	5'd2;
+	localparam	[4:0]	SMPLSTRBMUXCMD	=	5'd3;
+	
+	localparam	[1:0]	CURRADCCHANNEL	=	2'h3;
+	//COMMANDS	FOR REG_MAP
+	// parameter	[31:0]	MeasCmdBypass	=	{8'h11,8'h0,8'h63,7'h1,1'h1};
+	parameter	[31:0]	MeasCmdFft 		=	{8'h11,8'h0,8'h63,7'h4,1'b1};
+	parameter	[31:0]	AdcCtrl =	{8'h12,24'h2};
+	parameter	[31:0]	SensCtrlCmd =	{1'b0,21'h0,CURRADCCHANNEL,4'h0,4'h1};
+	parameter	[31:0]	DitherCmd 	= {8'h0E,8'd9,4'h0,4'h1,4'd11,4'h3};
+	parameter	[31:0]	IfFtwH 	=	{8'h15,16'h0,8'h40};
+	parameter	[31:0]	IfFtwL 	=	{8'h16,24'h000000};
+	parameter	[31:0]	FilterCorrCmdH 		=	{8'h17,24'hD70A3D};
+	parameter	[31:0]	FilterCorrCmdL 		=	{8'h18,24'hD70A3D};
+	parameter	[31:0]	MeasNum0RegCmd		=	{8'h58,24'd10};
+	parameter	[31:0]	MeasNum1RegCmd		=	{8'h59,MUXSLOWMODCMD,MUXFASTMODCMD,DSPTRIGINCMD,25'd0};
+	//===========================================================================================
+	
+	reg		Clk41;
+	reg		Clk50;
+	reg		Clk70;
+	
+	reg	[31:0]	tb_cnt=4'd0;
+	reg	rst;
+	reg	mosi_i	=	1'b0;
+	reg	Miso_i	=	1'b0;
+	reg	ss_i;
+	reg	clk_i	=	1'b0;
+	
+	
+	reg	[31:0]	DspSpiData;
+	reg		startCalcCmdReg;
+						
+	wire	[17:0]	cos_value;	
+	wire	[17:0]	sin_value;				
+
+	wire	ExtDspTrigPos0	=	(tb_cnt	>=	180	&&	tb_cnt	<=	181)?	1'b1:1'b0;
+	wire	ExtDspTrigNeg0	=	(tb_cnt	>=	180	&&	tb_cnt	<=	181)?	1'b0:1'b1;
+	
+	wire	ExtTrigger0		=	ExtDspTrigNeg0;
+	
+	wire	TrigFromDsp		=	(tb_cnt	>=	1100	&&	tb_cnt	<=	1101)?	1'b1:1'b0;
+	wire	endMeas;
+	reg	[31:0]	cmdCnt;
+	
+	reg	trig0;
+	reg	trig1;
+	
+	wire	trig0R;
+    wire	trig1R;
+	
+	// wire	[13:0]	DelpaPulse	=	(tb_cnt>=4508	&	tb_cnt	<=	4518)	?	14'h1fff:14'h0;
+	wire	[13:0]	DelpaPulse	=	(tb_cnt==4508)	?	14'h1fff:14'h0;
+		
+	assign	trig0R	=	trig0;
+    assign	trig1R	=	trig1;
+	
+	wire	signed	[13:0]	ncoSin1;
+	wire	signed	[13:0]	ncoCos1;
+	wire	signed	[13:0]	ncoSin2;
+	wire	signed	[13:0]	ncoCos2;
+	
+	wire	signed	[13:0]	sinAdd	=	(ncoSin1>>>1)+(ncoSin2>>>1);
+	
+//==========================================================================================
+//clocks gen
+	always	#10 Clk50	=	~Clk50;
+	always	#(14.285714285714/2) Clk70	=	~Clk70;
+	always	#10 clk_i	=	~clk_i;
+	always	#(24.390243902439/2)	Clk41	=	~Clk41;
+
+	
+	wire	sck_i;	
+//==========================================================================================
+initial begin
+	Clk50	=	1'b1;
+	Clk70	=	1'b1;
+	rst		=	1'b1;
+	Clk41	=	1'b0;
+	trig0	=	1'b0;
+	trig1	=	1'b0;
+#100;
+	rst		=	1'b0;
+#400;
+	Clk41	=	1'b0;
+end		
+	
+reg	endMeasReg;
+always	@(posedge	Clk41)	begin
+	endMeasReg	<=	endMeas;
+end
+
+wire	endMeasNeg	=	!endMeas&endMeasReg;
+
+always	@(posedge	Clk70)	begin
+	if	(!rst)	begin
+		if	(!endMeas)	begin
+			if	(tb_cnt	==	4505)	begin
+				startCalcCmdReg	<=	1'b1;
+			end	
+		end	else	begin
+			startCalcCmdReg	<=	1'b0;
+		end
+	end	else	begin
+		startCalcCmdReg	<=	1'b0;
+	end
+end
+
+always	@(negedge	Clk41)	begin
+	if	(!rst)		begin
+		tb_cnt	<=	tb_cnt+1;
+	end	else	begin
+		tb_cnt	<=	0;
+	end
+end
+
+wire	Adc1DataDa0P;
+wire	Adc1DataDa1P;
+
+reg [13:0] Data_i;
+real pi = 3.14159265358;
+real phase = 0;
+real phaseInc = 0.001;
+real signal;
+always @ (posedge Clk50)
+	begin
+		if (tb_cnt >= 4505)
+			begin
+				phase = phase + phaseInc;
+				phaseInc <= phaseInc + 0.0005;
+				signal = $sin(2*pi*phase);
+				Data_i = 2**12 * signal;
+			end
+		else
+			Data_i = 0;
+	end
+		
+wire	[31:0]	test	=	32'h2351eb85;
+// wire	[31:0]	test	=	32'h40000000;
+
+CordicNco		
+#(	
+	.ODatWidth	(14),
+	.PhIncWidth	(32),
+	.IterNum	(10),
+	.EnSinN		(1)
+)
+ncoInst1
+(
+	.Clk_i		(Clk50),
+	.Rst_i		(rst),
+	.Val_i		(1'b1),
+	.PhaseInc_i	(32'h51eb851),
+	.WindVal_i	(1'b1),
+	.WinType_i	(),
+	.Wind_o		(),
+	.Sin_o		(ncoSin1),
+	.Cos_o		(ncoCos1),
+	.Val_o		()
+);
+
+CordicNco		
+#(	
+	.ODatWidth	(14),
+	.PhIncWidth	(32),
+	.IterNum	(10),
+	.EnSinN		(1)
+)
+ncoInst2
+(
+	.Clk_i		(Clk50),
+	.Rst_i		(rst),
+	.Val_i		(1'b1),
+	.PhaseInc_i	(32'h33333333),
+	.WindVal_i	(1'b1),
+	.WinType_i	(),
+	.Wind_o		(),
+	.Sin_o		(ncoSin2),
+	.Cos_o		(ncoCos2),
+	.Val_o		()
+);
+
+CordicNco		
+#(	.ODatWidth	(18),
+	.PhIncWidth	(32),
+	.IterNum	(10),
+	.EnSinN		(0))
+ncoInst
+(
+	.Clk_i				(Clk50),
+	.Rst_i				(rst),
+	.Val_i				(1'b1),
+	.PhaseInc_i			(test),
+	.WindVal_i			(1'b1),
+	.WinType_i			(),
+	.Wind_o				(),
+	.Sin_o				(sin_value),
+	.Cos_o				(cos_value),
+	.Val_o				()
+);
+
+S5243Top MasterFpga 
+(
+	.ClkP_i				(Clk50),
+	.ClkN_i				(~Clk50),
+	.Led_o				(),
+//------------------------------------------	
+    .Adc1FclkP_i		(),		
+    .Adc1FclkN_i		(),		
+
+    .Adc1DataDa0P_i		(Adc1DataDa0P),
+	.Adc1DataDa0N_i		(~Adc1DataDa0P),		
+    .Adc1DataDa1P_i		(Adc1DataDa1P),
+    .Adc1DataDa1N_i		(~Adc1DataDa1P),
+
+	.Adc1DataDb0P_i		(Adc1DataDa0P),
+    .Adc1DataDb0N_i		(~Adc1DataDa0P),		
+    .Adc1DataDb1P_i		(Adc1DataDa1P),
+    .Adc1DataDb1N_i		(~Adc1DataDa1P),
+//------------------------------------------	
+    .Adc2FclkP_i		(),		
+    .Adc2FclkN_i		(),		
+
+    .Adc2DataDa0P_i		(1'b1),
+    .Adc2DataDa0N_i		(1'b0),		
+    .Adc2DataDa1P_i		(1'b1),
+    .Adc2DataDa1N_i		(1'b0),
+  
+	.Adc2DataDb0P_i		(1'b1),
+    .Adc2DataDb0N_i		(1'b0),		
+    .Adc2DataDb1P_i		(1'b1),
+    .Adc2DataDb1N_i		(1'b0),
+//------------------------------------------
+	.Adc1InitMosi_o		(),
+	.Adc2InitMosi_o		(),
+	
+	.Adc1InitClk_o		(),
+	.Adc2InitClk_o		(),
+	
+	.Adc1InitCs_o		(),
+	.Adc2InitCs_o		(),
+	
+	.Adc1InitRst_o		(),
+	.Adc2InitRst_o		(),
+	
+	
+	.DitherCtrlCh1_o	(),
+	.DitherCtrlCh2_o	(),
+//------------------------------------------	
+	
+	.Mosi_i				(mosi_i),
+	.Sck_i				(~sck_i),
+	.Ss_i				(ss_i),
+	.Miso_i				(),
+	.Miso_o				(),
+	
+	.LpOutClk_o			(),
+	.LpOutFs_o			(),			
+	.LpOutData_o		(),
+	
+	//fpga-dsp signals
+	.StartMeas_i		(startCalcCmdReg),
+	.EndMeas_o			(endMeas),
+	
+	.TimersClk_o		(),
+	
+	.Trig6to1_io		(),	
+	.Trig6to1Dir_o		(),	
+	
+	.DspTrigOut_i		(),				//Trig from DSP
+	.DspTrigIn_o		(),				//Trig To DSP
+	
+	.Overload_o			(),
+	
+	.PortSel_o			(),
+	
+	//mod out line
+	
+	.Mod_o				(),	
+	
+	//gain lines
+	.DspReadyForRx_i		(1'b0),
+	.AmpEn_o				(),	//	0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
+	// .AdcData_i				(sin_value[17-:14])
+	// .AdcData_i			(DelpaPulse)
+	.AdcData_i			(sinAdd)
+);
+parameter	IDLE	=	2'h0;
+parameter	CMD		=	2'h1;
+parameter	TX		=	2'h2;
+parameter	PAUSE	=	2'h3;
+
+reg	[1:0]	txCurrState;
+reg	[1:0]	txNextState;
+
+wire	txWork	=	tb_cnt	>=	23;
+// wire	txStop	=	(cmdCnt	>=	90)	&	(cmdCnt	>=	70)	&	(cmdCnt	>=	71);
+wire	txStop	=	(cmdCnt	>=	251);
+
+
+
+reg	[6:0]	txCnt;
+reg	[3:0]	pauseCnt;
+
+always	@(posedge	Clk41)	begin
+	if	(!rst)	begin
+		if	(txCurrState	==	CMD)	begin
+			if	(!txStop)	begin
+				cmdCnt	<=	cmdCnt+1;
+			end
+		end
+	end	else	begin
+		cmdCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk41)	begin
+	if	(!rst)	begin
+		if	(txCurrState	==	TX)	begin
+			txCnt	<=	txCnt+1;
+		end	else	begin
+			txCnt	<=	0;
+		end
+	end	else	begin
+		txCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk41)	begin
+	if	(!rst)	begin
+		if	(txCurrState	==	PAUSE)	begin
+			pauseCnt	<=	pauseCnt+1;
+		end	else	begin
+			pauseCnt	<=	0;
+		end
+	end	else	begin
+		pauseCnt	<=	0;
+	end
+end
+	
+always	@(posedge	Clk41)	begin
+	if	(txCurrState	==	CMD)	begin
+		if	(cmdCnt	==	0)	begin
+			DspSpiData		<=	MeasCmdFft;
+		end	else	if	(cmdCnt	==	1)	begin
+			DspSpiData		<=	MeasNum0RegCmd;
+		end	else	if	(cmdCnt	==	2)	begin
+			DspSpiData		<=	MeasNum1RegCmd;
+		end else	if	(cmdCnt	==	3)	begin
+			DspSpiData		<=	SensCtrlCmd;
+		end
+	end	else	if	(txCurrState	==	TX)	begin
+		DspSpiData	<=	DspSpiData<<1;
+	end
+end
+
+always	@(posedge Clk41)	begin
+	if	(txCurrState	==	TX)	begin
+		if	(txCnt	>=	7'd0)	begin
+			mosi_i	<=	DspSpiData[31];
+		end	else	begin
+			mosi_i	<=	1'b1;
+		end
+	end	else	begin
+		mosi_i	<=	1'b1;
+	end
+end
+
+always	@(posedge	Clk41)	begin
+	if	(txCurrState	==	TX)	begin
+		ss_i	<=	1'b0;
+	end	else	begin
+		ss_i	<=	1'b1;
+	end
+end
+
+assign	sck_i	=	Clk41;
+
+always	@(posedge	Clk41)	begin
+	if	(rst)	begin
+		txCurrState	<=	IDLE;
+	end	else	begin
+		txCurrState	<=	txNextState;
+	end
+end
+
+
+always @(*) begin
+	txNextState	=	IDLE;
+	case(txCurrState)
+	IDLE	:	begin
+					if (txWork)	begin
+						txNextState = CMD;
+					end	else begin
+						txNextState = IDLE;
+					end
+				end
+				
+	CMD	:		begin
+					if (!txStop)	begin
+						txNextState = TX;
+					end	else begin
+						txNextState = IDLE;
+					end
+				end
+
+	TX		:	begin
+					if (txCnt==6'd31) begin
+						txNextState  = PAUSE;
+					end	else begin
+						txNextState  = TX;
+					end
+				end
+        
+	PAUSE	:	begin
+					if (pauseCnt==4'd10) begin
+						txNextState  = CMD;
+					end	else begin
+						txNextState  = PAUSE;
+					end
+				end
+	endcase
+end
+
+
+		
+endmodule
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