#==========================================================================
#   TIMING CONSTRAINTS


#==========================================================================
#	INPUT CLOCKS
set_property PACKAGE_PIN C15 [get_ports Clk_i]
set_property IOSTANDARD LVCMOS25 [get_ports Clk_i]
create_clock -period 20.000 [get_ports Clk_i]

#==========================================================================
#	ADC1

set_property PACKAGE_PIN H1 [get_ports Adc1FclkP_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc1FclkP_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc1FclkN_i]

set_property PACKAGE_PIN C1 [get_ports Adc1DataDa0P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDa0P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDa0N_i]

set_property PACKAGE_PIN D2 [get_ports Adc1DataDa1P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDa1P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDa1N_i]

set_property PACKAGE_PIN E2 [get_ports Adc1DataDb0P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDb0P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDb0N_i]

set_property PACKAGE_PIN F2 [get_ports Adc1DataDb1P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDb1P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDb1N_i]

#==========================================================================
#	ADC2

set_property PACKAGE_PIN A11 [get_ports Adc2FclkP_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc2FclkP_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc2FclkN_i]

set_property PACKAGE_PIN B9 [get_ports Adc2DataDa0P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDa0P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDa0N_i]

set_property PACKAGE_PIN A8 [get_ports Adc2DataDa1P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDa1P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDa1N_i]

set_property PACKAGE_PIN B6 [get_ports Adc2DataDb0P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDb0P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDb0N_i]

set_property PACKAGE_PIN A5 [get_ports Adc2DataDb1P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDb1P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDb1N_i]

#==========================================================================
# DSP interface

set_property PACKAGE_PIN H14 [get_ports Miso_o]
set_property IOSTANDARD LVCMOS33 [get_ports Miso_o]

set_property PACKAGE_PIN H15 [get_ports Mosi_i]
set_property IOSTANDARD LVCMOS33 [get_ports Mosi_i]

set_property PACKAGE_PIN J12 [get_ports Ss_i]
set_property IOSTANDARD LVCMOS33 [get_ports Ss_i]

set_property PACKAGE_PIN M9 [get_ports Sck_i]
set_property IOSTANDARD LVCMOS33 [get_ports Sck_i]
create_clock -period 16.000 [get_ports Sck_i]

set_property PACKAGE_PIN P14 [get_ports LpOutClk_o]
set_property IOSTANDARD LVCMOS33 [get_ports LpOutClk_o]

set_property PACKAGE_PIN R14 [get_ports LpOutFs_o]
set_property IOSTANDARD LVCMOS33 [get_ports LpOutFs_o]

set_property PACKAGE_PIN R5 [get_ports {LpOutData_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[0]}]
set_property PACKAGE_PIN P6 [get_ports {LpOutData_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[1]}]
set_property PACKAGE_PIN R6 [get_ports {LpOutData_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[2]}]
set_property PACKAGE_PIN P7 [get_ports {LpOutData_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[3]}]
set_property PACKAGE_PIN R7 [get_ports {LpOutData_o[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[4]}]
set_property PACKAGE_PIN R8 [get_ports {LpOutData_o[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[5]}]
set_property PACKAGE_PIN N9 [get_ports {LpOutData_o[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[6]}]
set_property PACKAGE_PIN R9 [get_ports {LpOutData_o[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[7]}]
set_property PACKAGE_PIN P10 [get_ports {LpOutData_o[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[8]}]
set_property PACKAGE_PIN R10 [get_ports {LpOutData_o[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[9]}]
set_property PACKAGE_PIN P11 [get_ports {LpOutData_o[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[10]}]
set_property PACKAGE_PIN R11 [get_ports {LpOutData_o[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[11]}]
set_property PACKAGE_PIN P12 [get_ports {LpOutData_o[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[12]}]
set_property PACKAGE_PIN R12 [get_ports {LpOutData_o[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[13]}]
set_property PACKAGE_PIN R13 [get_ports {LpOutData_o[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[14]}]
set_property PACKAGE_PIN N13 [get_ports {LpOutData_o[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[15]}]

#==========================================================================
#  ADC SPI

set_property PACKAGE_PIN F14 [get_ports AdcInitMosi_o]
set_property IOSTANDARD LVCMOS25 [get_ports AdcInitMosi_o]
set_property PACKAGE_PIN E15 [get_ports AdcInitClk_o]
set_property IOSTANDARD LVCMOS25 [get_ports AdcInitClk_o]
set_property PACKAGE_PIN F15 [get_ports Adc2InitCs_o]
set_property IOSTANDARD LVCMOS25 [get_ports Adc2InitCs_o]
set_property PACKAGE_PIN E14 [get_ports Adc1InitCs_o]
set_property IOSTANDARD LVCMOS25 [get_ports Adc1InitCs_o]
set_property PACKAGE_PIN D15 [get_ports AdcInitRst_o]
set_property IOSTANDARD LVCMOS25 [get_ports AdcInitRst_o]

#==========================================================================
#  OTHER

set_property PACKAGE_PIN M14 [get_ports Overload_o]
set_property IOSTANDARD LVCMOS33 [get_ports Overload_o]

set_property PACKAGE_PIN M15 [get_ports StartMeasEvent_i]
set_property IOSTANDARD LVCMOS33 [get_ports StartMeasEvent_i]

#set_property PACKAGE_PIN M8 [get_ports EndMeas_o]
#set_property IOSTANDARD LVCMOS33 [get_ports EndMeas_o]

set_property PACKAGE_PIN A14 [get_ports {AmpEn_o[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[0]}]
set_property PACKAGE_PIN A13 [get_ports {AmpEn_o[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[1]}]
set_property PACKAGE_PIN B14 [get_ports {AmpEn_o[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[2]}]
set_property PACKAGE_PIN B15 [get_ports {AmpEn_o[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[3]}]

set_property PACKAGE_PIN N15 [get_ports SensEnS_io]
set_property IOSTANDARD LVCMOS33 [get_ports SensEnS_io]

set_property PACKAGE_PIN L15 [get_ports StartMeasDsp_i]
set_property IOSTANDARD LVCMOS33 [get_ports StartMeasDsp_i]

##set_property PACKAGE_PIN E14	[get_ports Mod_o];
##set_property IOSTANDARD LVCMOS25 [get_ports Mod_o];

set_property PACKAGE_PIN R2 [get_ports DitherCtrlCh1_o]
set_property IOSTANDARD LVCMOS25 [get_ports DitherCtrlCh1_o]

set_property PACKAGE_PIN P2 [get_ports DitherCtrlCh2_o]
set_property IOSTANDARD LVCMOS25 [get_ports DitherCtrlCh2_o]

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Ss_i_IBUF]










create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list gclk_BUFG]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 14 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {adc2ChR2Data[0]} {adc2ChR2Data[1]} {adc2ChR2Data[2]} {adc2ChR2Data[3]} {adc2ChR2Data[4]} {adc2ChR2Data[5]} {adc2ChR2Data[6]} {adc2ChR2Data[7]} {adc2ChR2Data[8]} {adc2ChR2Data[9]} {adc2ChR2Data[10]} {adc2ChR2Data[11]} {adc2ChR2Data[12]} {adc2ChR2Data[13]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 14 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {adc1ChR1Data[0]} {adc1ChR1Data[1]} {adc1ChR1Data[2]} {adc1ChR1Data[3]} {adc1ChR1Data[4]} {adc1ChR1Data[5]} {adc1ChR1Data[6]} {adc1ChR1Data[7]} {adc1ChR1Data[8]} {adc1ChR1Data[9]} {adc1ChR1Data[10]} {adc1ChR1Data[11]} {adc1ChR1Data[12]} {adc1ChR1Data[13]}]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets gclk_BUFG]
