set_property PACKAGE_PIN C1 [get_ports Adc1DataDa0P_i]
set_property PACKAGE_PIN D2 [get_ports Adc1DataDa1P_i]
set_property PACKAGE_PIN E2 [get_ports Adc1DataDb0P_i]
set_property PACKAGE_PIN F2 [get_ports Adc1DataDb1P_i]
set_property PACKAGE_PIN B9 [get_ports Adc2DataDa0P_i]
set_property PACKAGE_PIN A8 [get_ports Adc2DataDa1P_i]
set_property PACKAGE_PIN B6 [get_ports Adc2DataDb0P_i]
set_property PACKAGE_PIN A5 [get_ports Adc2DataDb1P_i]


#==========================================================================
#   TIMING CONSTRAINTS


#==========================================================================
#	INPUT CLOCKS
set_property PACKAGE_PIN C15 [get_ports Clk_i]
set_property IOSTANDARD LVCMOS25 [get_ports Clk_i]
create_clock -period 20.000 [get_ports Clk_i]

#==========================================================================
#	ADC1

set_property PACKAGE_PIN H1 [get_ports Adc1FclkP_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc1FclkP_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc1FclkN_i]

set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDa0P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDa0N_i]

set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDa1P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDa1N_i]

set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDb0P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDb0N_i]

set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDb1P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDb1N_i]

#==========================================================================
#	ADC2

set_property PACKAGE_PIN A11 [get_ports Adc2FclkP_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc2FclkP_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc2FclkN_i]

set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDa0P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDa0N_i]

set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDa1P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDa1N_i]

set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDb0P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDb0N_i]

set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDb1P_i]
set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDb1N_i]

#==========================================================================
# DSP interface

set_property PACKAGE_PIN H14 [get_ports Miso_o]
set_property IOSTANDARD LVCMOS33 [get_ports Miso_o]

set_property PACKAGE_PIN H15 [get_ports Mosi_i]
set_property IOSTANDARD LVCMOS33 [get_ports Mosi_i]

set_property PACKAGE_PIN J12 [get_ports Ss_i]
set_property IOSTANDARD LVCMOS33 [get_ports Ss_i]

set_property PACKAGE_PIN M9 [get_ports Sck_i]
set_property IOSTANDARD LVCMOS33 [get_ports Sck_i]
#create_clock -period 24.000 [get_ports Sck_i]
create_clock -period 16.000 [get_ports Sck_i]

set_property PACKAGE_PIN N12 [get_ports LpOutClk_o]
set_property IOSTANDARD LVCMOS33 [get_ports LpOutClk_o]

set_property PACKAGE_PIN P12 [get_ports LpOutFs_o]
set_property IOSTANDARD LVCMOS33 [get_ports LpOutFs_o]

set_property PACKAGE_PIN L15 [get_ports {LpOutData_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[0]}]
set_property PACKAGE_PIN L14 [get_ports {LpOutData_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[1]}]
set_property PACKAGE_PIN M15 [get_ports {LpOutData_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[2]}]
set_property PACKAGE_PIN M13 [get_ports {LpOutData_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[3]}]
set_property PACKAGE_PIN N15 [get_ports {LpOutData_o[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[4]}]
set_property PACKAGE_PIN M14 [get_ports {LpOutData_o[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[5]}]
set_property PACKAGE_PIN P15 [get_ports {LpOutData_o[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[6]}]
set_property PACKAGE_PIN N14 [get_ports {LpOutData_o[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[7]}]
set_property PACKAGE_PIN P14 [get_ports {LpOutData_o[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[8]}]
set_property PACKAGE_PIN R14 [get_ports {LpOutData_o[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[9]}]
set_property PACKAGE_PIN N13 [get_ports {LpOutData_o[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[10]}]
set_property PACKAGE_PIN R13 [get_ports {LpOutData_o[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[11]}]
set_property PACKAGE_PIN R11 [get_ports {LpOutData_o[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[12]}]
set_property PACKAGE_PIN P11 [get_ports {LpOutData_o[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[13]}]
set_property PACKAGE_PIN R10 [get_ports {LpOutData_o[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[14]}]
set_property PACKAGE_PIN P10 [get_ports {LpOutData_o[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[15]}]

#==========================================================================
#  ADC SPI

set_property PACKAGE_PIN B15 [get_ports AdcInitMosi_o]
set_property IOSTANDARD LVCMOS25 [get_ports AdcInitMosi_o]
set_property PACKAGE_PIN A13 [get_ports AdcInitClk_o]
set_property IOSTANDARD LVCMOS25 [get_ports AdcInitClk_o]
set_property PACKAGE_PIN B14 [get_ports Adc2InitCs_o]
set_property IOSTANDARD LVCMOS25 [get_ports Adc2InitCs_o]
set_property PACKAGE_PIN C14 [get_ports Adc1InitCs_o]
set_property IOSTANDARD LVCMOS25 [get_ports Adc1InitCs_o]
set_property PACKAGE_PIN A14 [get_ports AdcInitRst_o]
set_property IOSTANDARD LVCMOS25 [get_ports AdcInitRst_o]
#
#==========================================================================
#  OTHER

set_property PACKAGE_PIN R6 [get_ports Led_o]
set_property IOSTANDARD LVCMOS33 [get_ports Led_o]

set_property PACKAGE_PIN N11 [get_ports Overload_o]
set_property IOSTANDARD LVCMOS33 [get_ports Overload_o]

set_property PACKAGE_PIN R8 [get_ports OverloadS_i]
set_property IOSTANDARD LVCMOS33 [get_ports OverloadS_i]

set_property PACKAGE_PIN M10 [get_ports StartMeas_i]
set_property IOSTANDARD LVCMOS33 [get_ports StartMeas_i]

set_property PACKAGE_PIN M8 [get_ports EndMeas_o]
set_property IOSTANDARD LVCMOS33 [get_ports EndMeas_o]

set_property PACKAGE_PIN R9 [get_ports StartMeas_o]
set_property IOSTANDARD LVCMOS33 [get_ports StartMeas_o]

set_property PACKAGE_PIN L13 [get_ports TimersClk_o]
set_property IOSTANDARD LVCMOS33 [get_ports TimersClk_o]

set_property PACKAGE_PIN A2 [get_ports {AmpEn_o[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[0]}]
set_property PACKAGE_PIN B2 [get_ports {AmpEn_o[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[1]}]
set_property PACKAGE_PIN A3 [get_ports {AmpEn_o[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[2]}]
set_property PACKAGE_PIN A4 [get_ports {AmpEn_o[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[3]}]

set_property PACKAGE_PIN J1 [get_ports {PortSel_o[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {PortSel_o[0]}]
set_property PACKAGE_PIN J2 [get_ports {PortSel_o[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {PortSel_o[1]}]
set_property PACKAGE_PIN R3 [get_ports {PortSel_o[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {PortSel_o[2]}]
set_property PACKAGE_PIN P3 [get_ports {PortSel_o[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {PortSel_o[3]}]

set_property PACKAGE_PIN F14 [get_ports {PortSelDir_o[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {PortSelDir_o[0]}]
set_property PACKAGE_PIN F15 [get_ports {PortSelDir_o[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {PortSelDir_o[1]}]
set_property PACKAGE_PIN R4 [get_ports {PortSelDir_o[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {PortSelDir_o[2]}]
set_property PACKAGE_PIN M4 [get_ports {PortSelDir_o[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {PortSelDir_o[3]}]

set_property PACKAGE_PIN R7 [get_ports SensEnM_io]
set_property IOSTANDARD LVCMOS33 [get_ports SensEnM_io]

set_property PACKAGE_PIN P7 [get_ports StartMeasDsp_o]
set_property IOSTANDARD LVCMOS33 [get_ports StartMeasDsp_o]

set_property PACKAGE_PIN E14 [get_ports Mod_o]
set_property IOSTANDARD LVCMOS25 [get_ports Mod_o]


set_property PACKAGE_PIN K15 [get_ports DspTrigOut_i]
set_property IOSTANDARD LVCMOS33 [get_ports DspTrigOut_i]
set_property PACKAGE_PIN K14 [get_ports DspTrigIn_o]
set_property IOSTANDARD LVCMOS33 [get_ports DspTrigIn_o]

set_property PACKAGE_PIN D15 [get_ports {Trig6to1_io[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1_io[0]}]
set_property PACKAGE_PIN E15 [get_ports {Trig6to1_io[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1_io[1]}]
set_property PACKAGE_PIN N4 [get_ports {Trig6to1_io[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1_io[2]}]
set_property PACKAGE_PIN P1 [get_ports {Trig6to1_io[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1_io[3]}]
set_property PACKAGE_PIN N2 [get_ports {Trig6to1_io[4]}]
set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1_io[4]}]
set_property PACKAGE_PIN P2 [get_ports {Trig6to1_io[5]}]
set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1_io[5]}]

set_property PACKAGE_PIN C13 [get_ports {Trig6to1Dir_o[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1Dir_o[0]}]
set_property PACKAGE_PIN B13 [get_ports {Trig6to1Dir_o[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1Dir_o[1]}]
set_property PACKAGE_PIN R2 [get_ports {Trig6to1Dir_o[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1Dir_o[2]}]
set_property PACKAGE_PIN N1 [get_ports {Trig6to1Dir_o[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1Dir_o[3]}]
set_property PACKAGE_PIN M3 [get_ports {Trig6to1Dir_o[4]}]
set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1Dir_o[4]}]
set_property PACKAGE_PIN N3 [get_ports {Trig6to1Dir_o[5]}]
set_property IOSTANDARD LVCMOS25 [get_ports {Trig6to1Dir_o[5]}]

set_property PACKAGE_PIN M1 [get_ports DitherCtrlCh1_o]
set_property IOSTANDARD LVCMOS25 [get_ports DitherCtrlCh1_o]

set_property PACKAGE_PIN M2 [get_ports DitherCtrlCh2_o]
set_property IOSTANDARD LVCMOS25 [get_ports DitherCtrlCh2_o]

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Ss_i_IBUF]

set_false_path -from [get_clocks -of_objects [get_pins Clk200Gen/rx_plle2_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins Clk200Gen/rx_plle2_adv_inst/CLKOUT0]]








connect_debug_port u_ila_0/probe1 [get_nets [list {ExternalDspInterface/filteredDecimDataQ[0]} {ExternalDspInterface/filteredDecimDataQ[1]} {ExternalDspInterface/filteredDecimDataQ[2]} {ExternalDspInterface/filteredDecimDataQ[3]} {ExternalDspInterface/filteredDecimDataQ[4]} {ExternalDspInterface/filteredDecimDataQ[5]} {ExternalDspInterface/filteredDecimDataQ[6]} {ExternalDspInterface/filteredDecimDataQ[7]} {ExternalDspInterface/filteredDecimDataQ[8]} {ExternalDspInterface/filteredDecimDataQ[9]} {ExternalDspInterface/filteredDecimDataQ[10]} {ExternalDspInterface/filteredDecimDataQ[11]} {ExternalDspInterface/filteredDecimDataQ[12]} {ExternalDspInterface/filteredDecimDataQ[13]} {ExternalDspInterface/filteredDecimDataQ[14]} {ExternalDspInterface/filteredDecimDataQ[15]}]]






connect_debug_port u_ila_0/probe1 [get_nets [list ExternalDspInterface/dataForFifoVal]]










connect_debug_port u_ila_0/probe3 [get_nets [list {InternalDsp/DspChannel[0].AdcCalibrationInst/calValue[0]} {InternalDsp/DspChannel[0].AdcCalibrationInst/calValue[1]} {InternalDsp/DspChannel[0].AdcCalibrationInst/calValue[2]} {InternalDsp/DspChannel[0].AdcCalibrationInst/calValue[3]} {InternalDsp/DspChannel[0].AdcCalibrationInst/calValue[4]} {InternalDsp/DspChannel[0].AdcCalibrationInst/calValue[5]} {InternalDsp/DspChannel[0].AdcCalibrationInst/calValue[6]} {InternalDsp/DspChannel[0].AdcCalibrationInst/calValue[7]} {InternalDsp/DspChannel[0].AdcCalibrationInst/calValue[8]} {InternalDsp/DspChannel[0].AdcCalibrationInst/calValue[9]} {InternalDsp/DspChannel[0].AdcCalibrationInst/calValue[10]} {InternalDsp/DspChannel[0].AdcCalibrationInst/calValue[11]} {InternalDsp/DspChannel[0].AdcCalibrationInst/calValue[12]} {InternalDsp/DspChannel[0].AdcCalibrationInst/calValue[13]} {InternalDsp/DspChannel[0].AdcCalibrationInst/calValue[14]} {InternalDsp/DspChannel[0].AdcCalibrationInst/calValue[15]} {InternalDsp/DspChannel[0].AdcCalibrationInst/calValue[16]} {InternalDsp/DspChannel[0].AdcCalibrationInst/calValue[17]} {InternalDsp/DspChannel[0].AdcCalibrationInst/calValue[18]} {InternalDsp/DspChannel[0].AdcCalibrationInst/calValue[19]}]]
































connect_debug_port u_ila_0/probe4 [get_nets [list intTrig]]
connect_debug_port u_ila_0/probe7 [get_nets [list startMeasEventR]]


connect_debug_port u_ila_0/probe3 [get_nets [list {InternalDsp/adcDataBusExt[0][0]} {InternalDsp/adcDataBusExt[0][1]} {InternalDsp/adcDataBusExt[0][2]} {InternalDsp/adcDataBusExt[0][3]} {InternalDsp/adcDataBusExt[0][4]} {InternalDsp/adcDataBusExt[0][5]} {InternalDsp/adcDataBusExt[0][6]} {InternalDsp/adcDataBusExt[0][7]} {InternalDsp/adcDataBusExt[0][8]} {InternalDsp/adcDataBusExt[0][9]} {InternalDsp/adcDataBusExt[0][10]} {InternalDsp/adcDataBusExt[0][11]} {InternalDsp/adcDataBusExt[0][12]} {InternalDsp/adcDataBusExt[0][13]} {InternalDsp/adcDataBusExt[0][14]} {InternalDsp/adcDataBusExt[0][15]} {InternalDsp/adcDataBusExt[0][16]} {InternalDsp/adcDataBusExt[0][17]} {InternalDsp/adcDataBusExt[0][18]} {InternalDsp/adcDataBusExt[0][19]}]]




connect_debug_port u_ila_0/probe2 [get_nets [list {InternalDsp/DspChannel[1].ComplPrngAdderInst/dataPrngCut[0]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/dataPrngCut[1]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/dataPrngCut[2]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/dataPrngCut[3]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/dataPrngCut[4]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/dataPrngCut[5]}]]




connect_debug_port u_ila_0/probe1 [get_nets [list {InternalDsp/DspChannel[1].ComplPrngAdderInst/dataPrng0[26]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/dataPrng0[27]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/dataPrng0[28]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/dataPrng0[29]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/dataPrng0[30]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/dataPrng0[31]}]]
connect_debug_port u_ila_0/probe2 [get_nets [list {InternalDsp/DspChannel[1].ComplPrngAdderInst/Data_i[0]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/Data_i[1]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/Data_i[2]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/Data_i[3]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/Data_i[4]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/Data_i[5]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/Data_i[6]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/Data_i[7]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/Data_i[8]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/Data_i[9]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/Data_i[10]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/Data_i[11]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/Data_i[12]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/Data_i[13]}]]

connect_debug_port u_ila_0/probe2 [get_nets [list {InternalDsp/gatedAdcDataBus[1][0]} {InternalDsp/gatedAdcDataBus[1][1]} {InternalDsp/gatedAdcDataBus[1][2]} {InternalDsp/gatedAdcDataBus[1][3]} {InternalDsp/gatedAdcDataBus[1][4]} {InternalDsp/gatedAdcDataBus[1][5]} {InternalDsp/gatedAdcDataBus[1][6]} {InternalDsp/gatedAdcDataBus[1][7]} {InternalDsp/gatedAdcDataBus[1][8]} {InternalDsp/gatedAdcDataBus[1][9]} {InternalDsp/gatedAdcDataBus[1][10]} {InternalDsp/gatedAdcDataBus[1][11]} {InternalDsp/gatedAdcDataBus[1][12]} {InternalDsp/gatedAdcDataBus[1][13]} {InternalDsp/gatedAdcDataBus[1][14]} {InternalDsp/gatedAdcDataBus[1][15]} {InternalDsp/gatedAdcDataBus[1][16]} {InternalDsp/gatedAdcDataBus[1][17]} {InternalDsp/gatedAdcDataBus[1][18]} {InternalDsp/gatedAdcDataBus[1][19]}]]








connect_debug_port u_ila_0/probe1 [get_nets [list {InternalDsp/DspChannel[1].ComplPrngAdderInst/dataPrngCutExtended[0]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/dataPrngCutExtended[1]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/dataPrngCutExtended[2]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/dataPrngCutExtended[3]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/dataPrngCutExtended[4]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/dataPrngCutExtended[5]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/dataPrngCutExtended[6]} {InternalDsp/DspChannel[1].ComplPrngAdderInst/dataPrngCutExtended[19]}]]
connect_debug_port u_ila_0/probe9 [get_nets [list {InternalDsp/adcDataBusExt[1][0]} {InternalDsp/adcDataBusExt[1][1]} {InternalDsp/adcDataBusExt[1][2]} {InternalDsp/adcDataBusExt[1][3]} {InternalDsp/adcDataBusExt[1][4]} {InternalDsp/adcDataBusExt[1][5]} {InternalDsp/adcDataBusExt[1][6]} {InternalDsp/adcDataBusExt[1][7]} {InternalDsp/adcDataBusExt[1][8]} {InternalDsp/adcDataBusExt[1][9]} {InternalDsp/adcDataBusExt[1][10]} {InternalDsp/adcDataBusExt[1][11]} {InternalDsp/adcDataBusExt[1][12]} {InternalDsp/adcDataBusExt[1][13]} {InternalDsp/adcDataBusExt[1][14]} {InternalDsp/adcDataBusExt[1][15]} {InternalDsp/adcDataBusExt[1][16]} {InternalDsp/adcDataBusExt[1][17]} {InternalDsp/adcDataBusExt[1][18]} {InternalDsp/adcDataBusExt[1][19]}]]




create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 2048 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list gclk_BUFG]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 32 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {InternalDsp/Adc1ReR1Data_o[0]} {InternalDsp/Adc1ReR1Data_o[1]} {InternalDsp/Adc1ReR1Data_o[2]} {InternalDsp/Adc1ReR1Data_o[3]} {InternalDsp/Adc1ReR1Data_o[4]} {InternalDsp/Adc1ReR1Data_o[5]} {InternalDsp/Adc1ReR1Data_o[6]} {InternalDsp/Adc1ReR1Data_o[7]} {InternalDsp/Adc1ReR1Data_o[8]} {InternalDsp/Adc1ReR1Data_o[9]} {InternalDsp/Adc1ReR1Data_o[10]} {InternalDsp/Adc1ReR1Data_o[11]} {InternalDsp/Adc1ReR1Data_o[12]} {InternalDsp/Adc1ReR1Data_o[13]} {InternalDsp/Adc1ReR1Data_o[14]} {InternalDsp/Adc1ReR1Data_o[15]} {InternalDsp/Adc1ReR1Data_o[16]} {InternalDsp/Adc1ReR1Data_o[17]} {InternalDsp/Adc1ReR1Data_o[18]} {InternalDsp/Adc1ReR1Data_o[19]} {InternalDsp/Adc1ReR1Data_o[20]} {InternalDsp/Adc1ReR1Data_o[21]} {InternalDsp/Adc1ReR1Data_o[22]} {InternalDsp/Adc1ReR1Data_o[23]} {InternalDsp/Adc1ReR1Data_o[24]} {InternalDsp/Adc1ReR1Data_o[25]} {InternalDsp/Adc1ReR1Data_o[26]} {InternalDsp/Adc1ReR1Data_o[27]} {InternalDsp/Adc1ReR1Data_o[28]} {InternalDsp/Adc1ReR1Data_o[29]} {InternalDsp/Adc1ReR1Data_o[30]} {InternalDsp/Adc1ReR1Data_o[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 32 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {InternalDsp/Adc1ImR1Data_o[0]} {InternalDsp/Adc1ImR1Data_o[1]} {InternalDsp/Adc1ImR1Data_o[2]} {InternalDsp/Adc1ImR1Data_o[3]} {InternalDsp/Adc1ImR1Data_o[4]} {InternalDsp/Adc1ImR1Data_o[5]} {InternalDsp/Adc1ImR1Data_o[6]} {InternalDsp/Adc1ImR1Data_o[7]} {InternalDsp/Adc1ImR1Data_o[8]} {InternalDsp/Adc1ImR1Data_o[9]} {InternalDsp/Adc1ImR1Data_o[10]} {InternalDsp/Adc1ImR1Data_o[11]} {InternalDsp/Adc1ImR1Data_o[12]} {InternalDsp/Adc1ImR1Data_o[13]} {InternalDsp/Adc1ImR1Data_o[14]} {InternalDsp/Adc1ImR1Data_o[15]} {InternalDsp/Adc1ImR1Data_o[16]} {InternalDsp/Adc1ImR1Data_o[17]} {InternalDsp/Adc1ImR1Data_o[18]} {InternalDsp/Adc1ImR1Data_o[19]} {InternalDsp/Adc1ImR1Data_o[20]} {InternalDsp/Adc1ImR1Data_o[21]} {InternalDsp/Adc1ImR1Data_o[22]} {InternalDsp/Adc1ImR1Data_o[23]} {InternalDsp/Adc1ImR1Data_o[24]} {InternalDsp/Adc1ImR1Data_o[25]} {InternalDsp/Adc1ImR1Data_o[26]} {InternalDsp/Adc1ImR1Data_o[27]} {InternalDsp/Adc1ImR1Data_o[28]} {InternalDsp/Adc1ImR1Data_o[29]} {InternalDsp/Adc1ImR1Data_o[30]} {InternalDsp/Adc1ImR1Data_o[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 1 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list InternalDsp/MeasDataRdy_o]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets gclk_BUFG]
