`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:02:35 04/20/2020 
// Design Name: 
// Module Name:    mult_module 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module	MultModule	
#(	
	parameter	AdcDataWidth	=	14,
	parameter	IfNcoOutWidth	=	18,
	parameter	MultDataWidth	=	36
)	
(
	input	Rst_i,
	input	Clk_i,
	input	signed	[AdcDataWidth-1:0]	AdcData_i,
	input	signed	[IfNcoOutWidth-1:0]	Sin_i,
	input	signed	[IfNcoOutWidth-1:0]	Cos_i,
	output	signed	[MultDataWidth-1:0]	AdcSin_o,
	output	signed	[MultDataWidth-1:0]	AdcCos_o
);

//================================================================================
//  LOCALPARAM

//================================================================================
//  REG/WIRE
	reg	signed	[IfNcoOutWidth-1:0]	adcDataCompl;
	reg	signed	[IfNcoOutWidth-1:0]	sinReg;
	reg	signed	[IfNcoOutWidth-1:0]	cosReg;
	
	reg	signed	[MultDataWidth-1:0]	AdcSinReg;
	reg	signed	[MultDataWidth-1:0]	AdcCosReg;
//================================================================================
//  ASSIGNMENTS
	assign	AdcSin_o	=	AdcSinReg;
	assign	AdcCos_o	=	AdcCosReg;
//================================================================================
//  CODING
	always	@(posedge	Clk_i)	begin
		if	(!Rst_i)	begin
			adcDataCompl	<=	{AdcData_i,4'b0};
			sinReg	<=	Sin_i;
			cosReg	<=	Cos_i;
		end	else	begin
			adcDataCompl	<=	0;
			sinReg	<=	0;
			cosReg	<=	0;
		end
	end
	
	always	@(posedge	Clk_i)	begin
		if	(!Rst_i)	begin
			AdcSinReg	<=	adcDataCompl*sinReg;
			AdcCosReg	<=	adcDataCompl*cosReg;
		end	else	begin
			AdcSinReg	<=	{MultDataWidth{1'b0}};
			AdcCosReg	<=	{MultDataWidth{1'b0}};
		end
	end
	
endmodule
