module AdcDataGating
#(	
	parameter	AdcDataWidth	=	14
)
(
    input	Clk_i,
    input	Rst_i,
	input	GatingPulse_i,
	
	input	[AdcDataWidth-1:0]	Adc1ChT1Data_i,
	input	[AdcDataWidth-1:0]	Adc1ChR1Data_i,
	input	[AdcDataWidth-1:0]	Adc2ChR2Data_i,
	input	[AdcDataWidth-1:0]	Adc2ChT2Data_i,
	
	output	[AdcDataWidth-1:0]	Adc1ChT1Data_o,
	output	[AdcDataWidth-1:0]	Adc1ChR1Data_o,
	output	[AdcDataWidth-1:0]	Adc2ChR2Data_o,
	output	[AdcDataWidth-1:0]	Adc2ChT2Data_o
);

//================================================================================
//  CODING
//================================================================================
	wire	[AdcDataWidth-1:0]	adc1ChT1DataGated	=	(GatingPulse_i)?	Adc1ChT1Data_i:{AdcDataWidth{1'b0}};
	wire	[AdcDataWidth-1:0]	adc1ChR1DataGated	=	(GatingPulse_i)?	Adc1ChR1Data_i:{AdcDataWidth{1'b0}};
	wire	[AdcDataWidth-1:0]	adc2ChR2DataGated	=	(GatingPulse_i)?	Adc2ChR2Data_i:{AdcDataWidth{1'b0}};
	wire	[AdcDataWidth-1:0]	adc2ChT2DataGated	=	(GatingPulse_i)?	Adc2ChT2Data_i:{AdcDataWidth{1'b0}};
	
	reg		[AdcDataWidth-1:0]	dataDelPipeT1	[18:0];
	reg		[AdcDataWidth-1:0]	dataDelPipeR1	[18:0];
	reg		[AdcDataWidth-1:0]	dataDelPipeR2	[18:0];
	reg		[AdcDataWidth-1:0]	dataDelPipeT2	[18:0];

//================================================================================
//  ASSIGNMENTS
//================================================================================
	assign	Adc1ChT1Data_o	=	dataDelPipeT1[18];
	assign	Adc1ChR1Data_o	=	dataDelPipeR1[18];
	assign	Adc2ChR2Data_o	=	dataDelPipeR2[18];
	assign	Adc2ChT2Data_o	=	dataDelPipeT2[18];

//================================================================================
//  CODING
//================================================================================
integer	m;

always	@(posedge Clk_i) begin
	if	(!Rst_i)	begin
		dataDelPipeT1[0]  <= adc1ChT1DataGated;
		for(m=1; m<19; m=m+1) begin
			dataDelPipeT1	[m]<=dataDelPipeT1[m-1];
		end
	end	else	begin
		for(m=1; m<19; m=m+1) begin
			dataDelPipeT1	[m]<=0;
		end
	end
end

always	@(posedge Clk_i) begin
	if	(!Rst_i)	begin
		dataDelPipeR1[0]  <= adc1ChR1DataGated;
		for(m=1; m<19; m=m+1) begin
			dataDelPipeR1	[m]<=dataDelPipeR1[m-1];
		end
	end	else	begin
		for(m=1; m<19; m=m+1) begin
			dataDelPipeR1	[m]<=0;
		end
	end
end

always	@(posedge Clk_i) begin
	if	(!Rst_i)	begin
		dataDelPipeR2[0]  <= adc2ChR2DataGated;
		for(m=1; m<19; m=m+1) begin
			dataDelPipeR2	[m]<=dataDelPipeR2[m-1];
		end
	end	else	begin
		for(m=1; m<19; m=m+1) begin
			dataDelPipeR2	[m]<=0;
		end
	end
end

always	@(posedge Clk_i) begin
	if	(!Rst_i)	begin
		dataDelPipeT2[0]  <= adc2ChT2DataGated;
		for(m=1; m<19; m=m+1) begin
			dataDelPipeT2	[m]<=dataDelPipeT2[m-1];
		end
	end	else	begin
		for(m=1; m<19; m=m+1) begin
			dataDelPipeT2	[m]<=0;
		end	
	end
end

endmodule













