`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:02:35 04/20/2020 
// Design Name: 
// Module Name:    mult_module 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//commands:
//	ExtTrigUsage: 0 - no, 1 - yes.
//
//
//
//
//
//////////////////////////////////////////////////////////////////////////////////
module	MeasStartEventGen	
#(	
	parameter	CmdRegWidth	=	32
)
(
	input	Clk_i,
	input	Rst_i,

	input	MeasTrig_i,
	input	StartMeasDsp_i,
	
	output	StartMeasEvent_o,
	output	InitTrig_o
);	

//================================================================================
//  LOCALPARAM

//================================================================================
	reg		startMeasEvent;
	reg		initTrig;
	
	reg		measTrigReg;
	wire	measTrigPos;
//================================================================================
//  ASSIGNMENTS
	assign	measTrigPos			=	(!measTrigReg&MeasTrig_i);
	assign	StartMeasEvent_o	=	startMeasEvent;
	assign	InitTrig_o			=	initTrig;
//================================================================================
//  CODING

	always	@(posedge	Clk_i)	begin
		if	(!Rst_i)	begin
			measTrigReg	<=	MeasTrig_i;
		end	else	begin
			measTrigReg	=	0;
		end
	end
	
	always	@(posedge	Clk_i)	begin
		if	(!Rst_i)	begin
			if	(StartMeasDsp_i)	begin
				if	(measTrigPos)	begin
					startMeasEvent	<=	1'b1;
				end
			end	else	begin
				startMeasEvent	<=	0;
			end
		end	else	begin
			startMeasEvent	<=	0;
		end
	end
	
	always	@(*)	begin
		if	(!Rst_i)	begin
			if	(StartMeasDsp_i)	begin
				if	(measTrigPos)	begin
					initTrig	=	1'b1;
				end	else	begin
					initTrig	=	1'b0;
				end	
			end	else	begin
				initTrig	=	0;
			end
		end	else	begin
			initTrig	=	0;
		end
	end

endmodule











