`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:02:35 04/20/2020 
// Design Name: 
// Module Name:    mult_module 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module	ExtTrigMux	
#(	
	parameter	CmdDataRegWith	=	24
)	
(
	input	Rst_i,
	input	Clk_i,
	
	input	ExtTrig0_i,
	input	ExtTrig1_i,

	input	[CmdDataRegWith-1:0]	TrigCtrl0_i,
	input	[CmdDataRegWith-1:0]	TrigCtrl1_i,
	
	output	MeasTrig_o,
	output	MeasTrigVal_o
);	

//================================================================================
//  LOCALPARAM

//================================================================================
	reg	measTrig;
	reg	measTrigVal;
	
	wire	trig0En		=	TrigCtrl0_i[0];
	wire	trig1En		=	TrigCtrl1_i[0];
	wire	trig0Type	=	TrigCtrl0_i[4];
	wire	trig1Type	=	TrigCtrl1_i[4];
//================================================================================
//  ASSIGNMENTS
	assign	MeasTrig_o		=	measTrig;
	assign	MeasTrigVal_o	=	measTrigVal;
//================================================================================
//  CODING

	always	@(posedge	Clk_i)	begin
		if	(!Rst_i)	begin
			if	(trig0En&trig0Type)	begin
				measTrig	<=	ExtTrig0_i;
				measTrigVal	<=	trig0En;
			end	else	if	(trig1En&trig1Type)	begin
				measTrig	<=	ExtTrig1_i;
				measTrigVal	<=	trig1En;
			end	else	begin
				measTrig	<=0;
				measTrigVal	<=0;
			end
		end	else	begin
			measTrig	<=0;
			measTrigVal	<=0;
		end
	end

endmodule











