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@@ -0,0 +1,676 @@
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+`timescale 1ns / 1ps
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+
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+//=============================================================================================================
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+
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+// Тестовая конфигурация:
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+//
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+// Режим измерения "Точка в импульсе".
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+// Количество измерений = 1.
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+// Выбраный фильтр = 2МГц.
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+//
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+// PG1 -> Reference Sequense Generator. | Шаблон 1 имп.
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+// PG2 -> модулятор. | Шаблон 1 имп.
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+// PG3 -> Sample Strobe Generator. | Шаблон 1 имп.
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+// PG4 -> Gating Generator. | Шаблон 1 имп.
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+//
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+// Настройки мультиплексоров генераторов:
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+// PG1MUX_OUT -> INT_TRIG.
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+// PG2MUX_OUT -> PG1. Для всех генераторов кроме PG1 сигналом начала работы является выход PG1.
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+// PG3MUX_OUT -> PG1.
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+// PG4MUX_OUT -> PG1.
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+// PG5MUX_OUT -> PG1.
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+// PG6MUX_OUT -> PG1.
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+// PG7MUX_OUT -> PG1.
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+//
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+// Настройки остальных мультиплексоров:
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+// MODMUX_OUT -> PG2.
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+// GATINGMUX_OUT -> PG4.
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+// SAMPLSTROBEMUX_OUT -> PG3.
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+// EXTSTARTMUX -> DSPSTART.
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+
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+//=============================================================================================================
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+module S5443TopPulseProfileHighResTb;
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+
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+ localparam [4:0] EP1MUXCMD = 5'd14;
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+ localparam [4:0] EP2MUXCMD = 5'd1;
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+ localparam [4:0] EP3MUXCMD = 5'd1;
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+ localparam [4:0] EP4MUXCMD = 5'd1;
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+ localparam [4:0] EP5MUXCMD = 5'd1;
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+ localparam [4:0] EP6MUXCMD = 5'd1;
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+
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+ localparam [4:0] PG1MUXCMD = 5'd13;
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+ localparam [4:0] PG2MUXCMD = 5'd0;
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+ localparam [4:0] PG3MUXCMD = 5'd18;
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+ localparam [4:0] PG4MUXCMD = 5'd18;
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+ localparam [4:0] PG5MUXCMD = 5'd0;
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+ localparam [4:0] PG6MUXCMD = 5'd0;
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+ localparam [4:0] PG7MUXCMD = 5'd0;
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+
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+ localparam [2:0] PG1MODE = 3'd5;
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+ localparam [2:0] PG2MODE = 3'd1;
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+ localparam [2:0] PG3MODE = 3'd4;
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+ localparam [2:0] PG4MODE = 3'd4;
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+ localparam [2:0] PG5MODE = 3'd0;
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+ localparam [2:0] PG6MODE = 3'd0;
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+ localparam [2:0] PG7MODE = 3'd0;
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+
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+ localparam PG1POL = 1'b0;
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+ localparam PG2POL = 1'b0;
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+ localparam PG3POL = 1'b0;
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+ localparam PG4POL = 1'b0;
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+ localparam PG5POL = 1'b0;
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+ localparam PG6POL = 1'b0;
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+ localparam PG7POL = 1'b0;
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+
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+ localparam [4:0] EXTTRIGMUXCMD = 5'd15;
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+ localparam [4:0] DSPTRIGINCMD = 5'h8;
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+ localparam [4:0] MUXSLOWMODCMD = 5'd1;
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+ localparam [4:0] MUXFASTMODCMD = 5'd18;
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+ localparam [4:0] GATINGMUXCMD = 5'd3;
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+ localparam [4:0] SMPLSTRBMUXCMD = 5'd2;
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+
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+ //COMMANDS FOR REG_MAP
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+ parameter [31:0] MeasCmdBypass = {8'h11,8'h0,8'h63,8'h1};
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+ // parameter [31:0] MeasCmdFft = {8'h11,8'h0,8'h63,7'h3,1'b1};
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+ // parameter [31:0] MeasCmd = {8'h11,8'h0,8'h53,8'h0};
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+ parameter [31:0] MeasCmd = {8'h11,8'h3e,8'h45,8'h0};
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+ parameter [31:0] AdcCtrl = {8'h12,24'h2};
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+ parameter [31:0] SensCtrlCmd = {1'b0,27'h0,4'b1};
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+ // parameter [31:0] DitherCmd = {8'h0E,24'h100192};
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+ parameter [31:0] DitherCmd = {8'h0E,8'd9,4'h0,4'h1,4'd11,4'h3};
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+ parameter [31:0] IfFtwH = {8'h15,16'h0,8'h3e};
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+ parameter [31:0] IfFtwL = {8'h16,24'hb851eb};
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+ parameter [31:0] FilterCorrCmdH = {8'h17,24'hD70A3D};
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+ parameter [31:0] FilterCorrCmdL = {8'h18,24'hD70A3D};
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+
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+ //PG1 Cmd
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+ parameter [31:0] PG1P1DelayRegCmd = {8'h28,24'd0};
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+ parameter [31:0] PG1P2DelayRegCmd = {8'h29,24'd95};
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+ parameter [31:0] PG1P3DelayRegCmd = {8'h2a,24'd0};
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+ parameter [31:0] PG1P123DelayRegCmd = {8'h2b,24'd0};
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+ parameter [31:0] PG1P1WidthRegCmd = {8'h2c,24'd5};
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+ parameter [31:0] PG1P2WidthRegCmd = {8'h2d,24'd0};
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+ parameter [31:0] PG1P3WidthRegCmd = {8'h2e,24'd0};
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+ parameter [31:0] PG1P123WidthRegCmd = {8'h2f,24'd0};
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+
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+ //PG2 Cmd
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+ parameter [31:0] PG2P1DelayRegCmd = {8'h30,24'd0};
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+ parameter [31:0] PG2P2DelayRegCmd = {8'h31,24'd0};
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+ parameter [31:0] PG2P3DelayRegCmd = {8'h32,24'd0};
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+ parameter [31:0] PG2P123DelayRegCmd = {8'h33,24'd0};
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+ parameter [31:0] PG2P1WidthRegCmd = {8'h34,24'd50};
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+ parameter [31:0] PG2P2WidthRegCmd = {8'h35,24'd0};
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+ parameter [31:0] PG2P3WidthRegCmd = {8'h36,24'd0};
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+ parameter [31:0] PG2P123WidthRegCmd = {8'h37,24'd0};
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+
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+ //PG3 Cmd
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+ parameter [31:0] PG3P1DelayRegCmd = {8'h38,24'd0};
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+ parameter [31:0] PG3P2DelayRegCmd = {8'h39,24'd900};
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+ parameter [31:0] PG3P3DelayRegCmd = {8'h3a,24'd0};
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+ parameter [31:0] PG3P123DelayRegCmd = {8'h3b,24'd0};
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+ parameter [31:0] PG3P1WidthRegCmd = {8'h3c,24'd5};
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+ parameter [31:0] PG3P2WidthRegCmd = {8'h3d,24'd21};
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+ parameter [31:0] PG3P3WidthRegCmd = {8'h3e,24'd0};
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+ parameter [31:0] PG3P123WidthRegCmd = {8'h3f,24'd0};
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+
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+ //PG4 Cmd
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+ parameter [31:0] PG4P1DelayRegCmd = {8'h40,24'd0};
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+ parameter [31:0] PG4P2DelayRegCmd = {8'h41,24'd90};
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+ parameter [31:0] PG4P3DelayRegCmd = {8'h42,24'd0};
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+ parameter [31:0] PG4P123DelayRegCmd = {8'h43,24'd0};
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+ parameter [31:0] PG4P1WidthRegCmd = {8'h44,24'd10};
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+ parameter [31:0] PG4P2WidthRegCmd = {8'h45,24'd8};
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+ parameter [31:0] PG4P3WidthRegCmd = {8'h46,24'd0};
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+ parameter [31:0] PG4P123WidthRegCmd = {8'h47,24'd0};
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+
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+ //PG5 Cmd
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+ parameter [31:0] PG5P1DelayRegCmd = {8'h48,24'd0};
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+ parameter [31:0] PG5P2DelayRegCmd = {8'h49,24'd0};
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+ parameter [31:0] PG5P3DelayRegCmd = {8'h4a,24'd0};
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+ parameter [31:0] PG5P123DelayRegCmd = {8'h4b,24'd0};
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+ parameter [31:0] PG5P1WidthRegCmd = {8'h4c,24'd0};
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+ parameter [31:0] PG5P2WidthRegCmd = {8'h4d,24'd0};
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+ parameter [31:0] PG5P3WidthRegCmd = {8'h4e,24'd0};
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+ parameter [31:0] PG5P123WidthRegCmd = {8'h4f,24'd0};
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+
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+ //PG6 Cmd
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+ parameter [31:0] PG6P1DelayRegCmd = {8'h50,24'd0};
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+ parameter [31:0] PG6P2DelayRegCmd = {8'h51,24'd5};
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+ parameter [31:0] PG6P3DelayRegCmd = {8'h52,24'd15};
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+ parameter [31:0] PG6P123DelayRegCmd = {8'h53,24'd0};
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+ parameter [31:0] PG6P1WidthRegCmd = {8'h54,24'd1};
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+ parameter [31:0] PG6P2WidthRegCmd = {8'h55,24'd3};
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+ parameter [31:0] PG6P3WidthRegCmd = {8'h56,24'd5};
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+ parameter [31:0] PG6P123WidthRegCmd = {8'h57,24'd0};
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+
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+ //PG7 Cmd
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+ parameter [31:0] PG7P1DelayRegCmd = {8'h20,24'd0};
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+ parameter [31:0] PG7P2DelayRegCmd = {8'h21,24'd1};
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+ parameter [31:0] PG7P3DelayRegCmd = {8'h22,24'd5};
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+ parameter [31:0] PG7P123DelayRegCmd = {8'h23,24'd15};
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+ parameter [31:0] PG7P1WidthRegCmd = {8'h24,24'd1};
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+ parameter [31:0] PG7P2WidthRegCmd = {8'h25,24'd3};
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+ parameter [31:0] PG7P3WidthRegCmd = {8'h26,24'd5};
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+ parameter [31:0] PG7P123WidthRegCmd = {8'h27,24'd0};
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+
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+
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+ parameter [31:0] MeasNum0RegCmd = {8'h58,24'd21};
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+ parameter [31:0] MeasNum1RegCmd = {8'h59,MUXSLOWMODCMD,MUXFASTMODCMD,DSPTRIGINCMD,25'd0};
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+ parameter [31:0] PGMode0RegCmd = {8'h0b,3'b0,PG7MODE,PG6MODE,PG5MODE,PG4MODE,PG3MODE,PG2MODE,PG1MODE};
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+ parameter [31:0] PGMode1RegCmd = {8'h1b,7'b0000000,PG7POL,PG6POL,PG5POL,PG4POL,PG3POL,PG2POL,PG1POL,10'h0};
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+
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+ parameter [31:0] MuxCtrl1RegCmd = {8'h1c,4'h0,PG7MUXCMD,PG6MUXCMD,PG5MUXCMD,PG4MUXCMD};
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+ parameter [31:0] MuxCtrl2RegCmd = {8'h1d,4'h0,PG3MUXCMD,PG2MUXCMD,PG1MUXCMD,SMPLSTRBMUXCMD};
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+ parameter [31:0] MuxCtrl3RegCmd = {8'h1e,4'h0,GATINGMUXCMD,EXTTRIGMUXCMD,EP2MUXCMD,EP1MUXCMD};
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+ parameter [31:0] MuxCtrl4RegCmd = {8'h1f,4'h0,EP6MUXCMD,EP5MUXCMD,EP4MUXCMD,EP3MUXCMD};
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+
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+ //=================================================================================================================================================================================================================
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+
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+ reg Clk41;
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+ reg Clk50;
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+ reg Clk70;
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+
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+ reg [31:0] tb_cnt=4'd0;
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+ reg rst;
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+ reg mosi_i = 1'b0;
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+ reg Miso_i = 1'b0;
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+ reg ss_i;
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+ reg clk_i = 1'b0;
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+
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+
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+ reg [31:0] DspSpiData;
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+ reg startCalcCmdReg;
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+
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+ wire [17:0] cos_value;
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+ wire [17:0] sin_value;
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+
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+ wire ExtDspTrigPos0 = (tb_cnt >= 180 && tb_cnt <= 181)? 1'b1:1'b0;
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+ wire ExtDspTrigNeg0 = (tb_cnt >= 180 && tb_cnt <= 181)? 1'b0:1'b1;
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+
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+ wire ExtTrigger0 = ExtDspTrigNeg0;
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+
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+ wire TrigFromDsp = (tb_cnt >= 1100 && tb_cnt <= 1101)? 1'b1:1'b0;
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+ wire endMeas;
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+ reg [31:0] cmdCnt;
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+
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+ reg trig0;
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+ reg trig1;
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+
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+ wire trig0R;
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+ wire trig1R;
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+
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+ assign trig0R = trig0;
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+ assign trig1R = trig1;
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+
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+//==========================================================================================
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+//clocks gen
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+ always #10 Clk50 = ~Clk50;
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+ always #(14.285714285714/2) Clk70 = ~Clk70;
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+ always #10 clk_i = ~clk_i;
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+ always #(24.390243902439/2) Clk41 = ~Clk41;
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+
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+ wire sck_i;
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+//==========================================================================================
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+initial begin
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+ Clk50 = 1'b1;
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+ Clk70 = 1'b1;
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+ rst = 1'b1;
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+ Clk41 = 1'b0;
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+ trig0 = 1'b0;
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+ trig1 = 1'b0;
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+#100;
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+ rst = 1'b0;
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+#400;
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+ Clk41 = 1'b0;
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+end
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+
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+reg endMeasReg;
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+always @(posedge Clk41) begin
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+ endMeasReg <= endMeas;
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+end
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+
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+wire endMeasNeg = !endMeas&endMeasReg;
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+
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+always @(posedge Clk70) begin
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+ if (!rst) begin
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+ if (!endMeas) begin
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+ if (tb_cnt == 3550 | tb_cnt == 3950 |tb_cnt == 4505) begin
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+ startCalcCmdReg <= 1'b1;
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+ end
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+ end else begin
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+ startCalcCmdReg <= 1'b0;
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+ end
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+ end else begin
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+ startCalcCmdReg <= 1'b0;
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+ end
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+end
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+
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+always @(negedge Clk41) begin
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+ if (!rst) begin
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+ tb_cnt <= tb_cnt+1;
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+ end else begin
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+ tb_cnt <= 0;
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+ end
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+end
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+
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+wire Adc1DataDa0P;
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+wire Adc1DataDa1P;
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+
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+// wire [31:0] test = 32'h2351eb85;
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+wire [31:0] test = 32'h3eb851eb;
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+CordicNco
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+#( .ODatWidth (18),
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+ .PhIncWidth (32),
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+ .IterNum (10),
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+ .EnSinN (0))
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+ncoInst
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+(
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+ .Clk_i (Clk50),
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+ .Rst_i (rst),
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+ .Val_i (1'b1),
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+ .PhaseInc_i (test),
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+ .WindVal_i (1'b1),
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+ .WinType_i (),
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+ .Wind_o (),
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+ .Sin_o (sin_value),
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+ .Cos_o (cos_value),
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+ .Val_o ()
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+);
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+
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+
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+S5443Top MasterFpga
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+(
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+ .Clk_i (Clk50),
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+ .Led_o (),
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+//------------------------------------------
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+ .Adc1FclkP_i (),
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+ .Adc1FclkN_i (),
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+
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+ .Adc1DataDa0P_i (Adc1DataDa0P),
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+ .Adc1DataDa0N_i (~Adc1DataDa0P),
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+ .Adc1DataDa1P_i (Adc1DataDa1P),
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+ .Adc1DataDa1N_i (~Adc1DataDa1P),
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+
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+ .Adc1DataDb0P_i (Adc1DataDa0P),
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+ .Adc1DataDb0N_i (~Adc1DataDa0P),
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+ .Adc1DataDb1P_i (Adc1DataDa1P),
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+ .Adc1DataDb1N_i (~Adc1DataDa1P),
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+//------------------------------------------
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+ .Adc2FclkP_i (),
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+ .Adc2FclkN_i (),
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+
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+ .Adc2DataDa0P_i (1'b1),
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+ .Adc2DataDa0N_i (1'b0),
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+ .Adc2DataDa1P_i (1'b1),
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+ .Adc2DataDa1N_i (1'b0),
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+
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+ .Adc2DataDb0P_i (1'b1),
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+ .Adc2DataDb0N_i (1'b0),
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+ .Adc2DataDb1P_i (1'b1),
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+ .Adc2DataDb1N_i (1'b0),
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+//------------------------------------------
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+ .AdcInitMosi_o (),
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+ .AdcInitClk_o (),
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+ .Adc1InitCs_o (),
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+ .Adc2InitCs_o (),
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+ .AdcInitRst_o (),
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+//------------------------------------------
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+
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+ .Mosi_i (mosi_i),
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+ .Sck_i (~sck_i),
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+ .Ss_i (ss_i),
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+
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+ .LpOutClk_o (),
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+ .LpOutFs_o (),
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+ .LpOutData_o (),
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+
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|
+ //fpga-dsp signals
|
|
|
+ .StartMeas_i (startCalcCmdReg),
|
|
|
+ .StartMeasEvent_o (startMeasS),
|
|
|
+ .EndMeas_o (endMeas),
|
|
|
+ .TimersClk_o (),
|
|
|
+
|
|
|
+ .Trig6to1_io (),
|
|
|
+ .Trig6to1Dir_o (),
|
|
|
+
|
|
|
+ .DspTrigOut_i (Clk41), //Trig from DSP
|
|
|
+ .DspTrigIn_o (), //Trig To DSP
|
|
|
+
|
|
|
+ .OverloadS_i (1'b0),
|
|
|
+ .Overload_o (),
|
|
|
+
|
|
|
+ .PortSel_o (),
|
|
|
+ .PortSelDir_o (),
|
|
|
+
|
|
|
+ //mod out line
|
|
|
+
|
|
|
+ .Mod_o (),
|
|
|
+
|
|
|
+ //gain lines
|
|
|
+ .DspReadyForRx_i (1'b0),
|
|
|
+ .DspReadyForRxToFpgaS_o (),
|
|
|
+ .AmpEn_o (), // 0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
|
|
|
+ .AdcData_i (sin_value[17-:14])
|
|
|
+ // .AdcData_i (Data_i)
|
|
|
+);
|
|
|
+
|
|
|
+parameter IDLE = 2'h0;
|
|
|
+parameter CMD = 2'h1;
|
|
|
+parameter TX = 2'h2;
|
|
|
+parameter PAUSE = 2'h3;
|
|
|
+
|
|
|
+reg [1:0] txCurrState;
|
|
|
+reg [1:0] txNextState;
|
|
|
+
|
|
|
+wire txWork = tb_cnt >= 23;
|
|
|
+// wire txStop = (cmdCnt >= 90) & (cmdCnt >= 70) & (cmdCnt >= 71);
|
|
|
+wire txStop = (cmdCnt >= 251);
|
|
|
+
|
|
|
+
|
|
|
+reg [6:0] txCnt;
|
|
|
+reg [3:0] pauseCnt;
|
|
|
+
|
|
|
+always @(posedge Clk41) begin
|
|
|
+ if (!rst) begin
|
|
|
+ if (txCurrState == CMD) begin
|
|
|
+ if (!txStop) begin
|
|
|
+ cmdCnt <= cmdCnt+1;
|
|
|
+ end
|
|
|
+ end
|
|
|
+ end else begin
|
|
|
+ cmdCnt <= 0;
|
|
|
+ end
|
|
|
+end
|
|
|
+
|
|
|
+always @(posedge Clk41) begin
|
|
|
+ if (!rst) begin
|
|
|
+ if (txCurrState == TX) begin
|
|
|
+ txCnt <= txCnt+1;
|
|
|
+ end else begin
|
|
|
+ txCnt <= 0;
|
|
|
+ end
|
|
|
+ end else begin
|
|
|
+ txCnt <= 0;
|
|
|
+ end
|
|
|
+end
|
|
|
+
|
|
|
+always @(posedge Clk41) begin
|
|
|
+ if (!rst) begin
|
|
|
+ if (txCurrState == PAUSE) begin
|
|
|
+ pauseCnt <= pauseCnt+1;
|
|
|
+ end else begin
|
|
|
+ pauseCnt <= 0;
|
|
|
+ end
|
|
|
+ end else begin
|
|
|
+ pauseCnt <= 0;
|
|
|
+ end
|
|
|
+end
|
|
|
+
|
|
|
+
|
|
|
+always @(posedge Clk41) begin
|
|
|
+ if (txCurrState == CMD) begin
|
|
|
+ if (cmdCnt == 0) begin
|
|
|
+ DspSpiData <= MeasCmd;
|
|
|
+ end else if (cmdCnt == 1) begin
|
|
|
+ DspSpiData <= IfFtwH;
|
|
|
+ end else if (cmdCnt == 2) begin
|
|
|
+ DspSpiData <= IfFtwL;
|
|
|
+ end else if (cmdCnt == 3) begin
|
|
|
+ DspSpiData <= FilterCorrCmdH;
|
|
|
+ end else if (cmdCnt == 4) begin
|
|
|
+ DspSpiData <= FilterCorrCmdL;
|
|
|
+ end else if (cmdCnt == 5) begin
|
|
|
+ DspSpiData <= PG1P1DelayRegCmd;
|
|
|
+ end else if (cmdCnt == 6) begin
|
|
|
+ DspSpiData <= PG1P2DelayRegCmd;
|
|
|
+ end else if (cmdCnt == 7) begin
|
|
|
+ DspSpiData <= PG1P3DelayRegCmd;
|
|
|
+ end else if (cmdCnt == 8) begin
|
|
|
+ DspSpiData <= PG1P123DelayRegCmd;
|
|
|
+ end else if (cmdCnt == 9) begin
|
|
|
+ DspSpiData <= PG1P1WidthRegCmd;
|
|
|
+ end else if (cmdCnt == 10) begin
|
|
|
+ DspSpiData <= PG1P2WidthRegCmd;
|
|
|
+ end else if (cmdCnt == 11) begin
|
|
|
+ DspSpiData <= PG1P3WidthRegCmd;
|
|
|
+ end else if (cmdCnt == 12) begin
|
|
|
+ DspSpiData <= PG1P123WidthRegCmd;
|
|
|
+ end else if (cmdCnt == 13) begin
|
|
|
+ DspSpiData <= PG2P1DelayRegCmd;
|
|
|
+ end else if (cmdCnt == 14) begin
|
|
|
+ DspSpiData <= PG2P2DelayRegCmd;
|
|
|
+ end else if (cmdCnt == 15) begin
|
|
|
+ DspSpiData <= PG2P3DelayRegCmd;
|
|
|
+ end else if (cmdCnt == 16) begin
|
|
|
+ DspSpiData <= PG2P123DelayRegCmd;
|
|
|
+ end else if (cmdCnt == 17) begin
|
|
|
+ DspSpiData <= PG2P1WidthRegCmd;
|
|
|
+ end else if (cmdCnt == 18) begin
|
|
|
+ DspSpiData <= PG2P2WidthRegCmd;
|
|
|
+ end else if (cmdCnt == 19) begin
|
|
|
+ DspSpiData <= PG2P3WidthRegCmd;
|
|
|
+ end else if (cmdCnt == 20) begin
|
|
|
+ DspSpiData <= PG2P123WidthRegCmd;
|
|
|
+ end else if (cmdCnt == 21) begin
|
|
|
+ DspSpiData <= PG3P1DelayRegCmd;
|
|
|
+ end else if (cmdCnt == 22) begin
|
|
|
+ DspSpiData <= PG3P2DelayRegCmd;
|
|
|
+ end else if (cmdCnt == 23) begin
|
|
|
+ DspSpiData <= PG3P3DelayRegCmd;
|
|
|
+ end else if (cmdCnt == 24) begin
|
|
|
+ DspSpiData <= PG3P123DelayRegCmd;
|
|
|
+ end else if (cmdCnt == 25) begin
|
|
|
+ DspSpiData <= PG3P1WidthRegCmd;
|
|
|
+ end else if (cmdCnt == 26) begin
|
|
|
+ DspSpiData <= PG3P2WidthRegCmd;
|
|
|
+ end else if (cmdCnt == 27) begin
|
|
|
+ DspSpiData <= PG3P3WidthRegCmd;
|
|
|
+ end else if (cmdCnt == 28) begin
|
|
|
+ DspSpiData <= PG3P123WidthRegCmd;
|
|
|
+ end else if (cmdCnt == 29) begin
|
|
|
+ DspSpiData <= PG4P1DelayRegCmd;
|
|
|
+ end else if (cmdCnt == 30) begin
|
|
|
+ DspSpiData <= PG4P2DelayRegCmd;
|
|
|
+ end else if (cmdCnt == 31) begin
|
|
|
+ DspSpiData <= PG4P3DelayRegCmd;
|
|
|
+ end else if (cmdCnt == 32) begin
|
|
|
+ DspSpiData <= PG4P123DelayRegCmd;
|
|
|
+ end else if (cmdCnt == 33) begin
|
|
|
+ DspSpiData <= PG4P1WidthRegCmd;
|
|
|
+ end else if (cmdCnt == 34) begin
|
|
|
+ DspSpiData <= PG4P2WidthRegCmd;
|
|
|
+ end else if (cmdCnt == 35) begin
|
|
|
+ DspSpiData <= PG4P3WidthRegCmd;
|
|
|
+ end else if (cmdCnt == 36) begin
|
|
|
+ DspSpiData <= PG4P123WidthRegCmd;
|
|
|
+ end else if (cmdCnt == 37) begin
|
|
|
+ DspSpiData <= PG5P1DelayRegCmd;
|
|
|
+ end else if (cmdCnt == 38) begin
|
|
|
+ DspSpiData <= PG5P2DelayRegCmd;
|
|
|
+ end else if (cmdCnt == 39) begin
|
|
|
+ DspSpiData <= PG5P3DelayRegCmd;
|
|
|
+ end else if (cmdCnt == 40) begin
|
|
|
+ DspSpiData <= PG5P123DelayRegCmd;
|
|
|
+ end else if (cmdCnt == 41) begin
|
|
|
+ DspSpiData <= PG5P1WidthRegCmd;
|
|
|
+ end else if (cmdCnt == 42) begin
|
|
|
+ DspSpiData <= PG5P2WidthRegCmd;
|
|
|
+ end else if (cmdCnt == 43) begin
|
|
|
+ DspSpiData <= PG5P3WidthRegCmd;
|
|
|
+ end else if (cmdCnt == 44) begin
|
|
|
+ DspSpiData <= PG5P123WidthRegCmd;
|
|
|
+ end else if (cmdCnt == 45) begin
|
|
|
+ DspSpiData <= PG6P1DelayRegCmd;
|
|
|
+ end else if (cmdCnt == 46) begin
|
|
|
+ DspSpiData <= PG6P2DelayRegCmd;
|
|
|
+ end else if (cmdCnt == 47) begin
|
|
|
+ DspSpiData <= PG6P3DelayRegCmd;
|
|
|
+ end else if (cmdCnt == 48) begin
|
|
|
+ DspSpiData <= PG6P123DelayRegCmd;
|
|
|
+ end else if (cmdCnt == 49) begin
|
|
|
+ DspSpiData <= PG6P1WidthRegCmd;
|
|
|
+ end else if (cmdCnt == 50) begin
|
|
|
+ DspSpiData <= PG6P2WidthRegCmd;
|
|
|
+ end else if (cmdCnt == 51) begin
|
|
|
+ DspSpiData <= PG6P3WidthRegCmd;
|
|
|
+ end else if (cmdCnt == 52) begin
|
|
|
+ DspSpiData <= PG6P123WidthRegCmd;
|
|
|
+ end else if (cmdCnt == 53) begin
|
|
|
+ DspSpiData <= PG7P1DelayRegCmd;
|
|
|
+ end else if (cmdCnt == 54) begin
|
|
|
+ DspSpiData <= PG7P2DelayRegCmd;
|
|
|
+ end else if (cmdCnt == 55) begin
|
|
|
+ DspSpiData <= PG7P3DelayRegCmd;
|
|
|
+ end else if (cmdCnt == 56) begin
|
|
|
+ DspSpiData <= PG7P123DelayRegCmd;
|
|
|
+ end else if (cmdCnt == 57) begin
|
|
|
+ DspSpiData <= PG7P1WidthRegCmd;
|
|
|
+ end else if (cmdCnt == 58) begin
|
|
|
+ DspSpiData <= PG7P2WidthRegCmd;
|
|
|
+ end else if (cmdCnt == 59) begin
|
|
|
+ DspSpiData <= PG7P3WidthRegCmd;
|
|
|
+ end else if (cmdCnt == 60) begin
|
|
|
+ DspSpiData <= DitherCmd;
|
|
|
+ end else if (cmdCnt == 61) begin
|
|
|
+ DspSpiData <= MeasNum0RegCmd;
|
|
|
+ end else if (cmdCnt == 62) begin
|
|
|
+ DspSpiData <= MeasNum1RegCmd;
|
|
|
+ end else if (cmdCnt == 63) begin
|
|
|
+ DspSpiData <= PGMode0RegCmd;
|
|
|
+ end else if (cmdCnt == 64) begin
|
|
|
+ DspSpiData <= PGMode1RegCmd;
|
|
|
+ end else if (cmdCnt == 65) begin
|
|
|
+ DspSpiData <= MuxCtrl1RegCmd;
|
|
|
+ end else if (cmdCnt == 66) begin
|
|
|
+ DspSpiData <= MuxCtrl2RegCmd;
|
|
|
+ end else if (cmdCnt == 67) begin
|
|
|
+ DspSpiData <= MuxCtrl3RegCmd;
|
|
|
+ end else if (cmdCnt == 68) begin
|
|
|
+ DspSpiData <= AdcCtrl;
|
|
|
+ // end else if (cmdCnt == 99) begin
|
|
|
+ // DspSpiData <= {8'h58,24'd100};
|
|
|
+ end else begin
|
|
|
+ DspSpiData <= 32'hfffffff;
|
|
|
+ end
|
|
|
+ end else if (txCurrState == TX) begin
|
|
|
+ DspSpiData <= DspSpiData<<1;
|
|
|
+ end
|
|
|
+end
|
|
|
+
|
|
|
+always @(posedge Clk41) begin
|
|
|
+ if (txCurrState == TX) begin
|
|
|
+ if (txCnt >= 7'd0) begin
|
|
|
+ mosi_i <= DspSpiData[31];
|
|
|
+ end else begin
|
|
|
+ mosi_i <= 1'b1;
|
|
|
+ end
|
|
|
+ end else begin
|
|
|
+ mosi_i <= 1'b1;
|
|
|
+ end
|
|
|
+end
|
|
|
+
|
|
|
+always @(posedge Clk41) begin
|
|
|
+ if (txCurrState == TX) begin
|
|
|
+ ss_i <= 1'b0;
|
|
|
+ end else begin
|
|
|
+ ss_i <= 1'b1;
|
|
|
+ end
|
|
|
+end
|
|
|
+
|
|
|
+assign sck_i = Clk41;
|
|
|
+
|
|
|
+always @(posedge Clk41) begin
|
|
|
+ if (rst) begin
|
|
|
+ txCurrState <= IDLE;
|
|
|
+ end else begin
|
|
|
+ txCurrState <= txNextState;
|
|
|
+ end
|
|
|
+end
|
|
|
+
|
|
|
+
|
|
|
+always @(*) begin
|
|
|
+ txNextState = IDLE;
|
|
|
+ case(txCurrState)
|
|
|
+ IDLE : begin
|
|
|
+ if (txWork) begin
|
|
|
+ txNextState = CMD;
|
|
|
+ end else begin
|
|
|
+ txNextState = IDLE;
|
|
|
+ end
|
|
|
+ end
|
|
|
+
|
|
|
+ CMD : begin
|
|
|
+ if (!txStop) begin
|
|
|
+ txNextState = TX;
|
|
|
+ end else begin
|
|
|
+ txNextState = IDLE;
|
|
|
+ end
|
|
|
+ end
|
|
|
+
|
|
|
+ TX : begin
|
|
|
+ if (txCnt==6'd31) begin
|
|
|
+ txNextState = PAUSE;
|
|
|
+ end else begin
|
|
|
+ txNextState = TX;
|
|
|
+ end
|
|
|
+ end
|
|
|
+
|
|
|
+ PAUSE : begin
|
|
|
+ if (pauseCnt==4'd10) begin
|
|
|
+ txNextState = CMD;
|
|
|
+ end else begin
|
|
|
+ txNextState = PAUSE;
|
|
|
+ end
|
|
|
+ end
|
|
|
+ endcase
|
|
|
+end
|
|
|
+
|
|
|
+ reg [13:0] Data_i;
|
|
|
+ real pi = 3.14159265358;
|
|
|
+ real phase = 0;
|
|
|
+ real phaseInc = 0.001;
|
|
|
+ real signal;
|
|
|
+ always @ (posedge Clk50)
|
|
|
+ begin
|
|
|
+ if (tb_cnt >= 4505)
|
|
|
+ begin
|
|
|
+ phase = phase + phaseInc;
|
|
|
+ phaseInc <= phaseInc + 0.0005;
|
|
|
+ signal = $sin(2*pi*phase);
|
|
|
+ Data_i = 2**12 * signal;
|
|
|
+ end
|
|
|
+ else
|
|
|
+ Data_i = 0;
|
|
|
+ end
|
|
|
+
|
|
|
+endmodule
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
Mihail Zaytsev