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@@ -32,18 +32,29 @@ module Win_calc (
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output signed [17:0] win_o,
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output reg signed [17:0] sinWin_o
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);
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+
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//================================================================================
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-// REG/WIRE
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+// PARAMETERS
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//================================================================================
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+ localparam signed A3_1 = 18'h15584;
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+// ????????? ??? ?????????? SIN
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+ localparam signed [17:0] A1 = 18'h12400; // a-1
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+ localparam signed [17:0] A2 = 18'h002C0; // b
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+ localparam signed [17:0] A3 = ~A3_1 + 1'b1; // c
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+ localparam signed [17:0] A4 = 18'h0126C; // d
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+ localparam signed [17:0] A5 = 18'h01C5C; // e
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- reg [2:0] calc_cycle;
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- reg signed [17:0] a1;
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- reg signed [17:0] b;
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- reg signed [17:0] c1;
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- reg signed [17:0] c2;
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- wire [47:0] p2;
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- wire [47:0] p1;
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+ localparam CalcWidth = 10;
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+ localparam CalcWidthR = 18;
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+ localparam b2Width = CalcWidth*2;
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+ localparam b3Width = CalcWidth*3;
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+ localparam b4Width = CalcWidth*4;
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+ localparam b5Width = CalcWidth*5;
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+ localparam [31:0] testArg = 32'h12492492;
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+//================================================================================
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+// REG/WIRE
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+//================================================================================
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reg signed [17:0] sinWind;
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reg signed [17:0] tukeyWind;
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@@ -55,10 +66,9 @@ module Win_calc (
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wire sinFilterFlag = (filterCmd_i>=8'h54 & filterCmd_i<=8'h62);
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wire rectFilterFlag = (filterCmd_i>=8'h63 & filterCmd_i!=8'h70);
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- wire [17:0] bSin = win_value_i[31] ? 18'h3FFFF - win_value_i[31:14] : win_value_i [31:14];
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- wire [17:0] bTukey = win_value_i[31] ? 18'h3FFFF - win_value_i[31:14] : win_value_i [31:14];
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+ wire [CalcWidth-1:0] bCurr = win_value_i[31] ? 10'h3FF - win_value_i[31-:CalcWidth] : win_value_i [31-:CalcWidth];
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- wire [17:0] bCurr = sinFilterFlag ? bSin:bTukey;
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+ wire [CalcWidthR-1:0] bNew = win_value_i[31] ? 18'h3FFFF - win_value_i[31:14] : win_value_i [31:14];
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wire signed [17:0] constOne = 18'b011111111111111111;
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@@ -69,43 +79,62 @@ module Win_calc (
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wire signed [17:0] windMux1;
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wire signed [17:0] windMux2;
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+ wire signed [b2Width-1:0] b2 = bCurr**2;
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+ wire signed [b3Width-1:0] b3 = bCurr**3;
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+ wire signed [b4Width-1:0] b4 = bCurr**4;
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+ wire signed [b5Width-1:0] b5 = bCurr**5;
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+
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+ wire signed [CalcWidthR-1:0] b2Cut = b2[b2Width-2-:CalcWidthR];
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+ wire signed [CalcWidthR-1:0] b3Cut = b3[b3Width-3-:CalcWidthR];
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+ wire signed [CalcWidthR-1:0] b4Cut = b4[b4Width-4-:CalcWidthR];
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+ wire signed [CalcWidthR-1:0] b5Cut = b5[b5Width-5-:CalcWidthR];
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+
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+ reg signed [CalcWidthR*2-1:0] a1b;
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+ reg signed [CalcWidthR*2-1:0] a2b2;
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+ reg signed [CalcWidthR*2-1:0] a3b3;
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+ reg signed [CalcWidthR*2-1:0] a4b4;
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+ reg signed [CalcWidthR*2-1:0] a5b5;
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+
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+ wire signed [CalcWidthR-1:0] a1bCut = a1b [CalcWidthR*2-2-:CalcWidthR];
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+ wire signed [CalcWidthR-1:0] a2b2Cut = a2b2[CalcWidthR*2-2-:CalcWidthR];
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+ wire signed [CalcWidthR-1:0] a3b3Cut = a3b3[CalcWidthR*2-2-:CalcWidthR];
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+ wire signed [CalcWidthR-1:0] a4b4Cut = a4b4[CalcWidthR*2-2-:CalcWidthR];
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+ wire signed [CalcWidthR-1:0] a5b5Cut = a5b5[CalcWidthR*2-2-:CalcWidthR];
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+
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+ reg signed [CalcWidthR-1:0] bPrevSh;
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+
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+ wire signed [CalcWidthR-1:0] approxSin = a5b5Cut+a4b4Cut+a3b3Cut+a2b2Cut+a1bCut+bPrevSh;
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- wire [18*2-1:0] b2 = bCurr**2;
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- wire [18*3-1:0] b3 = bCurr**3;
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- wire [18*4-1:0] b4 = bCurr**4;
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- wire [18*5-1:0] b5 = bCurr**5;
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-
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-
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- wire [17:0] b2Cut = b2[18*2-1-:18];
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- wire [17:0] b3Cut = b3[18*3-1-:18];
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- wire [17:0] b4Cut = b4[18*4-1-:18];
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- wire [17:0] b5Cut = b5[18*5-1-:18];
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-//================================================================================
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-// PARAMETERS
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-//================================================================================
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- localparam signed A3_1 = 18'h15584;
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-// ????????? ??? ?????????? SIN
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- localparam signed [17:0] A1 = 18'h12400; // a-1
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- localparam signed [17:0] A2 = 18'h002C0; // b
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- localparam signed [17:0] A3 = ~A3_1 + 1'b1; // c
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- localparam signed [17:0] A4 = 18'h0126C; // d
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- localparam signed [17:0] A5 = 18'h01C5C; // e
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-
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+ wire signed [CalcWidthR-1:0] resultSin = approxSin[17]? 18'h1ffff:approxSin;
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//================================================================================
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// ASSIGNMENTS
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// ================================================================================
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-
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- // assign win_o = (sinFilterFlag) ? sinWindPow2[34-:18]:tukeyWindOut;
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-
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- assign win_o = windMux2;
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assign windMux1 = (sinFilterFlag) ? sinWindPow2[34-:18]:tukeyWindOut;
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assign windMux2 = (rectFilterFlag)? 18'h1ffff:windMux1;
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+ assign win_o = windMux2;
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// ================================================================================
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// CODING
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//================================================================================
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+always @(posedge clk_i) begin
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+ if (!reset_i) begin
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+ a5b5 <= A5*b5Cut;
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+ a4b4 <= A4*b4Cut;
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+ a3b3 <= A3*b3Cut;
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+ a2b2 <= A2*b2Cut;
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+ a1b <= A1*bNew;
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+ bPrevSh <= bNew;
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+ end else begin
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+ a5b5 <= 0;
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+ a4b4 <= 0;
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+ a3b3 <= 0;
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+ a2b2 <= 0;
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+ a1b <= 0;
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+ bPrevSh <= 0;
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+ end
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+end
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always @(posedge clk_i) begin
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if (!reset_i) begin
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@@ -117,19 +146,19 @@ always @(posedge clk_i) begin
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end
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end
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-always @(posedge clk_i) begin
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+always @(*) begin
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if (!reset_i) begin
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- tukeyCorr <= (tukeyWind+constOne);
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- sinWindPow2 <= sinWind**2;
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+ tukeyCorr = (tukeyWind+constOne);
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+ sinWindPow2 = resultSin**2;
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end else begin
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- tukeyCorr <= 18'h0;
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- sinWindPow2 <= 18'h0;
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+ tukeyCorr = 18'h0;
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+ sinWindPow2 = 18'h0;
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end
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end
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always @(*) begin
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if (!reset_i) begin
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- case(tukeyCtrlRR)
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+ case(tukeyCtrlR)
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2'h0: begin
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tukeyWindOut = 0;
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end
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@@ -148,267 +177,20 @@ always @(*) begin
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end
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end
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-always @(posedge wind_clk) begin
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- if (!reset_i) begin
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- case (calc_cycle)
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- 3'd0:
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- begin
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- a1 <= A5;
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- c1 <= A4;
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- c2 <= A3;
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- // b <= win_value_i[31] ? 18'h3FFFF - win_value_i[31:14] : win_value_i [31:14];
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- b <= bCurr;
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- end
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-
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- 3'd1:
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- begin
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- a1 <= p2[34:17];
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- c1 <= A2;
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- c2 <= A1;
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- end
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- 3'd2:
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- begin
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- a1 <= p2[34:17];
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- c1 <= b;
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- end
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- endcase
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- end else begin
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- a1 <= 18'b0;
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- c1 <= 18'b0;
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- c2 <= 18'b0;
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- b <= 18'b0;
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- end
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-end
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-
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-always @(posedge wind_clk) begin
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- if (!reset_i) begin
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- if (!win_type_i) begin
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- if (calc_cycle == 3'd0) begin
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- if (p1[47:34] == 0) begin
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- sinWind <= p1[34-:18];//1.0.17
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- end else begin
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- sinWind <= 18'h1FFFF;
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- end
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-
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- end
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- end else begin
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- sinWind <= 18'h0;
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- end
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- end else begin
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- sinWind <= 18'h0;
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- end
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-end
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-always @(posedge wind_clk) begin
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+always @(*) begin
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if (!reset_i) begin
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if (!win_type_i) begin
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- if (calc_cycle == 3'd0) begin
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- if (!WinCtrl_i) begin
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- tukeyWind <= p1[34-:18];
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- end else begin
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- tukeyWind <= 0-p1[34-:18];
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- end
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- end
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- end else begin
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- tukeyWind <= 18'h0;
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- end
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- end else begin
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- tukeyWind <= 18'h0;
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- end
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-end
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-
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-//??????? "????? ??????? ????????". ???????? [(b*A5+A4) = p1 ? ????????????? ?????? (b*p1+A3)=p2] == 1 ????.
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-
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-always @(posedge wind_clk) begin
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- if (!reset_i) begin
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- if (calc_cycle != 3'd2) begin
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- calc_cycle <= calc_cycle + 3'd1;
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+ if (!WinCtrl_i) begin
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+ tukeyWind = resultSin;
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end else begin
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- calc_cycle <= 3'd0;
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+ tukeyWind = 0-resultSin;
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end
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+ end else begin
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+ tukeyWind = 18'h0;
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+ end
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end else begin
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- calc_cycle <= 3'd0;
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+ tukeyWind = 18'h0;
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end
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end
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-
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-DSP48E1 #(
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- // Feature Control Attributes: Data Path Selection
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- .A_INPUT("DIRECT"), // Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
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- .B_INPUT("DIRECT"), // Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
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- .USE_DPORT("FALSE"), // Select D port usage (TRUE or FALSE)
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- .USE_MULT("MULTIPLY"), // Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
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- .USE_SIMD("ONE48"), // SIMD selection ("ONE48", "TWO24", "FOUR12")
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- // Pattern Detector Attributes: Pattern Detection Configuration
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- .AUTORESET_PATDET("NO_RESET"), // "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
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- .MASK(48'h3fffffffffff), // 48-bit mask value for pattern detect (1=ignore)
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- .PATTERN(48'h000000000000), // 48-bit pattern match for pattern detect
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- .SEL_MASK("MASK"), // "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
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- .SEL_PATTERN("PATTERN"), // Select pattern value ("PATTERN" or "C")
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- .USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect ("PATDET" or "NO_PATDET")
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- // Register Control Attributes: Pipeline Register Configuration
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- .ACASCREG(0), // Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
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- .ADREG(0), // Number of pipeline stages for pre-adder (0 or 1)
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- .ALUMODEREG(0), // Number of pipeline stages for ALUMODE (0 or 1)
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- .AREG(0), // Number of pipeline stages for A (0, 1 or 2)
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- .BCASCREG(0), // Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
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- .BREG(0), // Number of pipeline stages for B (0, 1 or 2)
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- .CARRYINREG(0), // Number of pipeline stages for CARRYIN (0 or 1)
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- .CARRYINSELREG(0), // Number of pipeline stages for CARRYINSEL (0 or 1)
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- .CREG(0), // Number of pipeline stages for C (0 or 1)
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- .DREG(0), // Number of pipeline stages for D (0 or 1)
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- .INMODEREG(0), // Number of pipeline stages for INMODE (0 or 1)
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- .MREG(0), // Number of multiplier pipeline stages (0 or 1)
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- .OPMODEREG(0), // Number of pipeline stages for OPMODE (0 or 1)
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- .PREG(0) // Number of pipeline stages for P (0 or 1)
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- )
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-DSP48E1_1inst (
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- // Cascade: 30-bit (each) output: Cascade Ports
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- .ACOUT(), // 30-bit output: A port cascade output
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- .BCOUT(), // 18-bit output: B port cascade output
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- .CARRYCASCOUT(), // 1-bit output: Cascade carry output
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- .MULTSIGNOUT(), // 1-bit output: Multiplier sign cascade output
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- .PCOUT(), // 48-bit output: Cascade output
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- // Control: 1-bit (each) output: Control Inputs/Status Bits
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- .OVERFLOW(), // 1-bit output: Overflow in add/acc output
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- .PATTERNBDETECT(), // 1-bit output: Pattern bar detect output
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- .PATTERNDETECT(), // 1-bit output: Pattern detect output
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- .UNDERFLOW(), // 1-bit output: Underflow in add/acc output
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- // Data: 4-bit (each) output: Data Ports
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- .CARRYOUT(), // 4-bit output: Carry output
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- .P(p1), // 48-bit output: Primary data output
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- // Cascade: 30-bit (each) input: Cascade Ports
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- .ACIN(), // 30-bit input: A cascade data input
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- .BCIN(), // 18-bit input: B cascade input
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- .CARRYCASCIN(), // 1-bit input: Cascade carry input
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- .MULTSIGNIN(), // 1-bit input: Multiplier sign input
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- .PCIN(48'b0), // 48-bit input: P cascade input
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- // Control: 4-bit (each) input: Control Inputs/Status Bits
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- .ALUMODE(4'b0000), // 4-bit input: ALU control input
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- .CARRYINSEL(3'b000), // 3-bit input: Carry select input
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- .CLK(1'b0), // 1-bit input: Clock input
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- // .CLK(wind_clk), // 1-bit input: Clock input
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- .INMODE(5'b00000), // 5-bit input: INMODE control input
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- .OPMODE(7'b0110101), // 7-bit input: Operation mode input
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- // Data: 30-bit (each) input: Data Ports
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- .A({{12{a1[17]}},a1}), // 30-bit input: A data input
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- .B(b), // 18-bit input: B data input
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- .C({ {13{c1[17]}}, c1[17:0],17'b0 }), // 48-bit input: C data input
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- .CARRYIN(1'b0), // 1-bit input: Carry input signal
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- .D(25'b0), // 25-bit input: D data input
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- // Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
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- .CEA1(1'b1), // 1-bit input: Clock enable input for 1st stage AREG
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- .CEA2(1'b1), // 1-bit input: Clock enable input for 2nd stage AREG
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- .CEAD(1'b1), // 1-bit input: Clock enable input for ADREG
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- .CEALUMODE(1'b1), // 1-bit input: Clock enable input for ALUMODE
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- .CEB1(1'b1), // 1-bit input: Clock enable input for 1st stage BREG
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- .CEB2(1'b1), // 1-bit input: Clock enable input for 2nd stage BREG
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- .CEC(1'b1), // 1-bit input: Clock enable input for CREG
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- .CECARRYIN(1'b1), // 1-bit input: Clock enable input for CARRYINREG
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- .CECTRL(1'b1), // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
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- .CED(1'b1), // 1-bit input: Clock enable input for DREG
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- .CEINMODE(1'b1), // 1-bit input: Clock enable input for INMODEREG
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- .CEM(1'b1), // 1-bit input: Clock enable input for MREG
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- .CEP(1'b1), // 1-bit input: Clock enable input for PREG
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- .RSTA(1'b0), // 1-bit input: Reset input for AREG
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- .RSTALLCARRYIN(1'b0), // 1-bit input: Reset input for CARRYINREG
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- .RSTALUMODE(1'b0), // 1-bit input: Reset input for ALUMODEREG
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- .RSTB(1'b0), // 1-bit input: Reset input for BREG
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- .RSTC(1'b0), // 1-bit input: Reset input for CREG
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- .RSTCTRL(1'b0), // 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
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- .RSTD(1'b0), // 1-bit input: Reset input for DREG and ADREG
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- .RSTINMODE(1'b0), // 1-bit input: Reset input for INMODEREG
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- .RSTM(1'b0), // 1-bit input: Reset input for MREG
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- .RSTP(1'b0) // 1-bit input: Reset input for PREG
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-);
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-
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-DSP48E1 #(
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- // Feature Control Attributes: Data Path Selection
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- .A_INPUT("DIRECT"), // Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
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- .B_INPUT("DIRECT"), // Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
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- .USE_DPORT("FALSE"), // Select D port usage (TRUE or FALSE)
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- .USE_MULT("MULTIPLY"), // Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
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- .USE_SIMD("ONE48"), // SIMD selection ("ONE48", "TWO24", "FOUR12")
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- // Pattern Detector Attributes: Pattern Detection Configuration
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- .AUTORESET_PATDET("NO_RESET"), // "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
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- .MASK(48'h1), // 48-bit mask value for pattern detect (1=ignore)
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- .PATTERN(48'h000000000000), // 48-bit pattern match for pattern detect
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- .SEL_MASK("MASK"), // "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
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- .SEL_PATTERN("PATTERN"), // Select pattern value ("PATTERN" or "C")
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- .USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect ("PATDET" or "NO_PATDET")
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- // Register Control Attributes: Pipeline Register Configuration
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- .ACASCREG(0), // Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
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- .ADREG(0), // Number of pipeline stages for pre-adder (0 or 1)
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- .ALUMODEREG(0), // Number of pipeline stages for ALUMODE (0 or 1)
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- .AREG(0), // Number of pipeline stages for A (0, 1 or 2)
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- .BCASCREG(0), // Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
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- .BREG(0), // Number of pipeline stages for B (0, 1 or 2)
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- .CARRYINREG(0), // Number of pipeline stages for CARRYIN (0 or 1)
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- .CARRYINSELREG(0), // Number of pipeline stages for CARRYINSEL (0 or 1)
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- .CREG(0), // Number of pipeline stages for C (0 or 1)
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- .DREG(0), // Number of pipeline stages for D (0 or 1)
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- .INMODEREG(0), // Number of pipeline stages for INMODE (0 or 1)
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- .MREG(0), // Number of multiplier pipeline stages (0 or 1)
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- .OPMODEREG(0), // Number of pipeline stages for OPMODE (0 or 1)
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- .PREG(0) // Number of pipeline stages for P (0 or 1)
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- )
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-DSP48E1_2inst (
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- // Cascade: 30-bit (each) output: Cascade Ports
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- .ACOUT(), // 30-bit output: A port cascade output
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- .BCOUT(), // 18-bit output: B port cascade output
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- .CARRYCASCOUT(), // 1-bit output: Cascade carry output
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- .MULTSIGNOUT(), // 1-bit output: Multiplier sign cascade output
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- .PCOUT(), // 48-bit output: Cascade output
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- // Control: 1-bit (each) output: Control Inputs/Status Bits
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- .OVERFLOW(), // 1-bit output: Overflow in add/acc output
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- .PATTERNBDETECT(), // 1-bit output: Pattern bar detect output
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- .PATTERNDETECT(), // 1-bit output: Pattern detect output
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- .UNDERFLOW(), // 1-bit output: Underflow in add/acc output
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- // Data: 4-bit (each) output: Data Ports
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- .CARRYOUT(), // 4-bit output: Carry output
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- .P(p2), // 48-bit output: Primary data output
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- // Cascade: 30-bit (each) input: Cascade Ports
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- .ACIN(), // 30-bit input: A cascade data input
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- .BCIN(), // 18-bit input: B cascade input
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- .CARRYCASCIN(), // 1-bit input: Cascade carry input
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- .MULTSIGNIN(), // 1-bit input: Multiplier sign input
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- .PCIN(48'b0), // 48-bit input: P cascade input
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- // Control: 4-bit (each) input: Control Inputs/Status Bits
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- .ALUMODE(4'b0000), // 4-bit input: ALU control input
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- .CARRYINSEL(3'b000), // 3-bit input: Carry select input
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- .CLK(1'b0), // 1-bit input: Clock input
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- // .CLK(wind_clk), // 1-bit input: Clock input
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- .INMODE(5'b00000), // 5-bit input: INMODE control input
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- .OPMODE(7'b0110101), // 7-bit input: Operation mode input
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- // Data: 30-bit (each) input: Data Ports
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- .A({{12{p1[47]}},p1[34:17]}), // 30-bit input: A data input
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- .B(b), // 18-bit input: B data input
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- .C({ {13{c2[17]}}, c2[17:0],17'b0 }), // 48-bit input: C data input
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- .CARRYIN(1'b0), // 1-bit input: Carry input signal
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- .D(25'b0), // 25-bit input: D data input
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- // Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
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- .CEA1(1'b1), // 1-bit input: Clock enable input for 1st stage AREG
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- .CEA2(1'b1), // 1-bit input: Clock enable input for 2nd stage AREG
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- .CEAD(1'b1), // 1-bit input: Clock enable input for ADREG
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- .CEALUMODE(1'b1), // 1-bit input: Clock enable input for ALUMODE
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- .CEB1(1'b1), // 1-bit input: Clock enable input for 1st stage BREG
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- .CEB2(1'b1), // 1-bit input: Clock enable input for 2nd stage BREG
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- .CEC(1'b1), // 1-bit input: Clock enable input for CREG
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- .CECARRYIN(1'b1), // 1-bit input: Clock enable input for CARRYINREG
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- .CECTRL(1'b1), // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
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- .CED(1'b1), // 1-bit input: Clock enable input for DREG
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- .CEINMODE(1'b1), // 1-bit input: Clock enable input for INMODEREG
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- .CEM(1'b1), // 1-bit input: Clock enable input for MREG
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- .CEP(1'b1), // 1-bit input: Clock enable input for PREG
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- .RSTA(1'b0), // 1-bit input: Reset input for AREG
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- .RSTALLCARRYIN(1'b0), // 1-bit input: Reset input for CARRYINREG
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- .RSTALUMODE(1'b0), // 1-bit input: Reset input for ALUMODEREG
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|
- .RSTB(1'b0), // 1-bit input: Reset input for BREG
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- .RSTC(1'b0), // 1-bit input: Reset input for CREG
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- .RSTCTRL(1'b0), // 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
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|
- .RSTD(1'b0), // 1-bit input: Reset input for DREG and ADREG
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- .RSTINMODE(1'b0), // 1-bit input: Reset input for INMODEREG
|
|
|
- .RSTM(1'b0), // 1-bit input: Reset input for MREG
|
|
|
- .RSTP(1'b0) // 1-bit input: Reset input for PREG
|
|
|
-);
|
|
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-
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|
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endmodule
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Shalambala