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@@ -62,17 +62,17 @@ module S5443TopPulseProfileTb;
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localparam PG6POL = 1'b0;
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localparam PG7POL = 1'b0;
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- localparam [4:0] EXTTRIGMUXCMD = 5'd15;
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+ localparam [4:0] EXTTRIGMUXCMD = 5'd7;
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localparam [4:0] DSPTRIGINCMD = 5'h8;
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localparam [4:0] MUXSLOWMODCMD = 5'd1;
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localparam [4:0] MUXFASTMODCMD = 5'd1;
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localparam [4:0] GATINGMUXCMD = 5'd2;
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- localparam [4:0] SMPLSTRBMUXCMD = 5'd3;
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+ localparam [4:0] SMPLSTRBMUXCMD = 5'd8;
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//COMMANDS FOR REG_MAP
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parameter [31:0] MeasCmdBypass = {8'h11,8'h0,8'h63,8'h1};
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parameter [31:0] MeasCmdFft = {8'h11,8'h0,8'h63,7'h5,1'b1};
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- parameter [31:0] MeasCmd = {8'h11,8'h0,8'h53,8'h0};
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+ parameter [31:0] MeasCmd = {8'h11,8'h1,8'h53,8'h0};
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// parameter [31:0] MeasCmd = {8'h11,8'h3e,8'h63,8'h0};
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parameter [31:0] AdcCtrl = {8'h12,24'h2};
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parameter [31:0] SensCtrlCmd = {1'b0,27'h0,4'b1};
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@@ -201,6 +201,11 @@ module S5443TopPulseProfileTb;
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assign trig0R = trig0;
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assign trig1R = trig1;
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+ reg [32:0] extPulseTrigCnt;
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+ wire extPulseTrig = extPulseTrigCnt==32'd50;
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+
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+ wire [5:0] extTrigBus;
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+ wire [5:0] extTrigDir;
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//==========================================================================================
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//clocks gen
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always #10 Clk50 = ~Clk50;
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@@ -209,6 +214,21 @@ module S5443TopPulseProfileTb;
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always #(24.390243902439/2) Clk41 = ~Clk41;
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wire sck_i;
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+
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+ assign extTrigDir [0] = !MeasCmd[16];
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+ assign extTrigDir [1] = !MeasCmd[17];
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+ assign extTrigDir [2] = !MeasCmd[18];
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+ assign extTrigDir [3] = !MeasCmd[19];
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+ assign extTrigDir [4] = !MeasCmd[20];
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+ assign extTrigDir [5] = !MeasCmd[21];
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+
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+ assign extTrigBus [0] = (MeasCmd[16]) ? extPulseTrig:1'bz; //1 - in, 0 - out
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+ assign extTrigBus [1] = (MeasCmd[17]) ? 0:1'bz; //1 - in, 0 - out
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+ assign extTrigBus [2] = (MeasCmd[18]) ? 0:1'bz; //1 - in, 0 - out
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+ assign extTrigBus [3] = (MeasCmd[19]) ? 0:1'bz; //1 - in, 0 - out
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+ assign extTrigBus [4] = (MeasCmd[20]) ? 0:1'bz; //1 - in, 0 - out
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+ assign extTrigBus [5] = (MeasCmd[21]) ? 0:1'bz; //1 - in, 0 - out
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+
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//==========================================================================================
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initial begin
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Clk50 = 1'b1;
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@@ -223,6 +243,18 @@ initial begin
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Clk41 = 1'b0;
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end
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+always @(posedge Clk50) begin
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+ if (!rst) begin
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+ if (extPulseTrigCnt!=32'd50) begin
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+ extPulseTrigCnt <= extPulseTrigCnt+32'd1;
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+ end else begin
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+ extPulseTrigCnt <= 32'd0;
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+ end
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+ end else begin
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+ extPulseTrigCnt <= 32'd0;
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+ end
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+end
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+
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reg endMeasReg;
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always @(posedge Clk41) begin
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endMeasReg <= endMeas;
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@@ -330,8 +362,8 @@ S5243Top MasterFpga
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.EndMeas_o (endMeas),
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.TimersClk_o (),
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- .Trig6to1_io (),
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- .Trig6to1Dir_o (),
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+ .Trig6to1_io (extTrigBus),
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+ .Trig6to1Dir_o (extTrigDir),
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.DspTrigOut_i (Clk41), //Trig from DSP
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.DspTrigIn_o (), //Trig To DSP
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