Доработана модель фильтра. Увеличены разрядности данных. Исправлена ошибка упаковки данных.

S5443_M/S5443.srcs/sources_1/new/AdcDataRx/AdcDataInterface.v

@@ -118,7 +118,7 @@ module	AdcDataInterface
 //  instantiations
 //================================================================================
 
-top5x2_7to1_sdr_rx	Adc1Rx
+TopRx	Adc1Rx
 (                  
 	.reset		(Rst_i),
 	.refclkin	(RefClk_i),
@@ -136,7 +136,7 @@ top5x2_7to1_sdr_rx	Adc1Rx
 	.DivClk_o	(Adc1RxClk)
 );
 
-top5x2_7to1_sdr_rx	Adc2Rx
+TopRx	Adc2Rx
 (                  
 	.reset		(Rst_i),
 	.refclkin	(RefClk_i),

S5443_M/S5443.srcs/sources_1/new/AdcDataRx/Description.v

@@ -0,0 +1,3 @@
+1. Модуль AdcDataInterface просто обертка для модулей приёма данных с двух АЦП.
+2. Модуль TopRx реализовывает приём данных с АЦП в соответствии с XAPP585.
+3. Модуль AdcSync служит для синхронизации данных между клоковых доменов внутри FPGA. Модуль по сути простая синхро цепь из двух последовательных регистров.

S5443_M/S5443.srcs/sources_1/new/AdcDataRx/top5x2_7to1_sdr_rx.v

@@ -56,7 +56,7 @@
 
 `timescale 1ps/1ps
 
-module top5x2_7to1_sdr_rx 
+module TopRx 
 #(
 	parameter	integer	D	=	4,		// Set the number of outputs per channel to be 5 in this example
 	parameter	integer	N	=	1,       // Set the number of channels to be 2 in this example

S5443_M/S5443.srcs/sources_1/new/DitherGen/Description.v

@@ -0,0 +1,17 @@
+1. Модуль генерирует дизер.
+2. Команда настройки генератора описана в S5443v4port_reg.xlsx.
+	2.1 В команде настройки приходят такие параметры как :
+		FR	- регулирует "шаг" по таблице NCO.
+		AM_N- значение амплитуды генерируемого дизера.
+		RAMP_CNTR - максимальное значение счетчика генератора пилообразного сигнала.
+		
+3. Частота на выходе модуля определяется по следующей формуле:
+
+	Fdith = (Fref/(RAMP_CNTR+1))*(FR/256)
+
+где  Fref - опорная частота, в текущей версии прибора Fref = 50*10^6;
+         Fdith - целевая частота дизера.
+
+Например:	 
+	Для частоты дизера 312.5k: FR =16 , RAMP_CNTR=9
+	Для частоты дизера 284.9090....k: FR =16 , RAMP_CNTR=10

S5443_M/S5443.srcs/sources_1/new/DitherGen/DitherGen.v

@@ -1,100 +0,0 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer:		Churbanov S.
-// 
-// Create Date:    10:00:14 13/08/2019 
-// Design Name: 
-// Module Name:    DspPpiOut 
-// Project Name: 
-// Target Devices: 
-// Tool versions: 
-// Description: 
-//
-// Dependencies: 
-//
-// Revision: 
-// Revision 0.01 - File Created
-// Additional Comments: 
-//
-//////////////////////////////////////////////////////////////////////////////////
-module DitherGen
-#(	
-	parameter	CmdDataRegWith		=	24,
-	parameter	FrAmpWordWidth		=	8
-)
-(
-	input	Rst_i,
-	input	Clk_i,	
-	
-	input	[CmdDataRegWith-1:0]	DitherCmd_i,
-	output	DitherCtrlT2R2_o,
-	output	DitherCtrlT1R1_o
-);
-//================================================================================
-//  REG/WIRE
-//================================================================================
-	wire	[FrAmpWordWidth-1:0]	ditherFreq	=	DitherCmd_i[CmdDataRegWith-1-:FrAmpWordWidth];
-	wire	[FrAmpWordWidth-1:0]	ditherAmp	=	DitherCmd_i[CmdDataRegWith-FrAmpWordWidth-1-:FrAmpWordWidth];
-
-	wire	ditherT2R2	=	DitherCmd_i[1];
-	wire	ditherT1R1	=	DitherCmd_i[0];
-	
-	reg	[FrAmpWordWidth-1:0]	freqCnt;
-	reg	[FrAmpWordWidth-1:0]	ampCnt;
-	
-	wire	DitherReg	=	((freqCnt<=ditherFreq/2)&&(ampCnt<=ditherAmp))?	1'b1:1'b0;
-	
-	wire	ClkDiv	=	(freqCnt<=ditherFreq/2)?	1'b1:1'b0;
-//================================================================================
-//  ASSIGNMENTS
-//================================================================================	
-	assign	DitherCtrlT2R2_o	=	(ditherT2R2)?	DitherReg:1'b0;
-	assign	DitherCtrlT1R1_o	=	(ditherT1R1)?	DitherReg:1'b0;
-//================================================================================
-//  CODING
-//================================================================================	
-
-always	@(posedge	Clk_i)	begin
-	if	(!Rst_i)	begin
-		if	(freqCnt!=ditherFreq-1)	begin
-			freqCnt<=freqCnt+1;
-		end	else	begin
-			freqCnt<=0;
-		end
-	end	else	begin
-		freqCnt<=0;
-	end
-end
-
-always	@(posedge	Clk_i)	begin
-	if	(!Rst_i)	begin
-		if	(ampCnt!=ditherFreq-1)	begin
-			ampCnt<=ampCnt+1;
-		end	else	begin
-			ampCnt<=0;
-		end
-	end	else	begin
-		ampCnt<=0;
-	end
-end
-
-endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-

S5443_M/S5443.srcs/sources_1/new/ExtDspInterface/Description.v

@@ -0,0 +1 @@
+Модуль DspInterface вляется оберткой.

S5443_M/S5443.srcs/sources_1/new/FftDataFiltering/DecimFilterWrapper.v

@@ -21,9 +21,9 @@
 module	DecimFilterWrapper
 #(	
 	parameter	AdcDataWidth		=	14,
-	parameter	N	=	4,
+	parameter	N	=	8,
 	parameter	M	=	1,
-	parameter	FilteredDataWidth	=	29,
+	parameter	FilteredDataWidth	=	30,
 	parameter	FirOutDataWidth		=	48,
 	parameter	FirOutCutBit		=	42
 )
@@ -71,7 +71,8 @@ module	DecimFilterWrapper
 	
 	localparam	maxWidthForR2	=	5'd18;	//msb for R = 2;
 	localparam	maxWidthForR3	=	5'd21;	//msb for R = 3;
-	localparam	maxWidthForR4	=	5'd22;	//msb for R = 4;
+	// localparam	maxWidthForR4	=	5'd22;	//msb for R = 4;
+	localparam	maxWidthForR4	=	5'd29;	//msb for R = 4;
 	localparam	maxWidthForR5	=	5'd24;	//msb for R = 5;
 	localparam	maxWidthForR6	=	5'd25;	//msb for R = 6;
 	localparam	maxWidthForR7	=	5'd26;	//msb for R = 7;
@@ -86,7 +87,7 @@ module	DecimFilterWrapper
 	assign	FilteredAdcDataI_o	=	outDataI;
 	assign	FilteredAdcDataQ_o	=	outDataQ;
 
-	assign	FilteredDataVal_o	=	decimDataValI;
+	assign	FilteredDataVal_o	=	decimDataValIR;
 
 
 // {{14{AdcData_i[AdcDataWidth-1]}},AdcData_i}
@@ -168,7 +169,7 @@ cicFilterInstI
 	.Clk_i			(Clk_i),
 	.Rst_i			(Rst_i),
 	.DecimFactor_i	(DecimFactor_i),
-	.Data_i			({{15{AdcData_i[AdcDataWidth-1]}},AdcData_i}),
+	.Data_i			({{16{AdcData_i[AdcDataWidth-1]}},AdcData_i}),
 	.DataNd_i		(OscWind_i),
 	.Data_o			(decimDataI),
 	.DataValid_o	(decimDataValI)

S5443_M/S5443.srcs/sources_1/new/FftDataFiltering/DecimFilterWrapperTb.v

@@ -16,7 +16,8 @@ real	signal;
 
 reg		[31:0]	tbCnt;
 reg		[31:0]	pNumCnt;
-wire	oscWind	=	(tbCnt>=4500&tbCnt<=5499)?	1'b1:1'b0;
+// wire	oscWind	=	(tbCnt>=4500&tbCnt<=5499)?	1'b1:1'b0;
+wire	oscWind	=	(tbCnt>=4500&tbCnt<=4999)?	1'b1:1'b0;
 
 wire	signed	[13:0]	ncoSin1;
 wire	signed	[13:0]	ncoCos1;
@@ -37,22 +38,25 @@ wire	signed	[13:0]	adcDataMixedCut	=	adcDataMixed[27-:14];
 wire	signed	[13:0]	sinAdd	=	(ncoSin1>>>1)+(ncoSin2>>>1);
 
 wire	signed	[17:0]	wind;
+
+// wire	signed	[13:0]	singlePulse	=	(tbCnt>=4505&tbCnt<=4510)?	14'h1fff:14'h0;
+wire	signed	[13:0]	singlePulse	=	(tbCnt==4505)?	14'h1fff:14'h0;
 //==========================================================================================
 //clocks gen
 always	#10 Clk50	=	~Clk50;
 
 //==========================================================================================
 
-parameter	N	=	5;
+parameter	N	=	4;
 parameter	M	=	1;
 
 initial begin
 	Clk50		=	1'b1;
 	Rst			=	1'b1;
-	decimFactor	=	3'd2;
+	decimFactor	=	3'd4;
 #100;
 	Rst		=	1'b0;
-end		
+end	
 
 always	@(posedge	Clk50)	begin
 	if	(!Rst)	begin
@@ -133,7 +137,7 @@ DecimFilterWrapper
 	.AdcDataWidth	(14),
 	.N	(N),
 	.M	(M),
-	.FilteredDataWidth	(29),
+	.FilteredDataWidth	(30),
 	.FirOutDataWidth	(48),
 	.FirOutCutBit		(42)
 )
@@ -147,7 +151,8 @@ DecimFilter
 	.IfFtwL_i		(24'h51eb85),
 	.IfFtwH_i		(24'h23),
 	
-	.AdcData_i		(sinAdd),
+	.AdcData_i		(singlePulse),
+	// .AdcData_i		(sinAdd),
 	// .AdcData_i		(adcDataMixedCut),
 	
 	.FilteredAdcDataI_o	(resultI),
@@ -219,30 +224,31 @@ always	@(posedge	Clk50)	begin
 	end	else	begin
 		if	(oscWind)	begin
 			// $display("AdcData is %d", sinAdd);
-			$fwrite(inSignal,"%d\n",   sinAdd);
+			// $fwrite(inSignal,"%d\n",   sinAdd);
+			$fwrite(inSignal,"%d\n",   singlePulse);
 		end	
 	end	
 end
 
-// always	@(posedge	Clk50)	begin
-	// if	(Rst)	begin
-		// filteredData = $fopen("C:/Users/Stepan/Desktop/4portCompact/S5443Current/S5443_M/S5443.srcs/sources_1/new/filteredData.txt","w");
-	// end	else	begin
-		// if	(resultVal)	begin
-			// $fwrite(filteredData,"%d\n",   resultI);
-		// end	
-	// end	
-// end
- 
 always	@(posedge	Clk50)	begin
 	if	(Rst)	begin
 		filteredData = $fopen("C:/Users/Stepan/Desktop/4portCompact/S5443Current/S5443_M/S5443.srcs/sources_1/new/filteredData.txt","w");
 	end	else	begin
-		if	(windResultVal)	begin
-			$fwrite(filteredData,"%d\n",   windResultCut);
+		if	(resultVal)	begin
+			$fwrite(filteredData,"%d\n",   resultI);
 		end	
 	end	
-end 
+end
+ 
+// always	@(posedge	Clk50)	begin
+	// if	(Rst)	begin
+		// filteredData = $fopen("C:/Users/Stepan/Desktop/4portCompact/S5443Current/S5443_M/S5443.srcs/sources_1/new/filteredData.txt","w");
+	// end	else	begin
+		// if	(windResultVal)	begin
+			// $fwrite(filteredData,"%d\n",   windResultCut);
+		// end	
+	// end	
+// end 
 
 endmodule
 

S5443_M/S5443.srcs/sources_1/new/FilteredData.txt

@@ -1,500 +1,125 @@
-    -1
-    -1
-    -2
-    -2
-    -4
-    -2
-    -2
-    -3
-     5
-     1
-    12
-    13
-    14
-    30
-    17
-    33
-    27
-    16
-    31
-    -7
-     7
-   -18
-   -45
-   -27
-   -87
-   -59
-   -84
-  -105
-   -52
-  -109
-   -36
-   -36
-   -34
-    67
-    12
-   123
-   124
-   117
-   226
-   118
-   213
-   159
-    89
-   164
-   -33
-    33
-   -77
-  -191
-  -107
-  -337
-  -221
-  -301
-  -367
-  -177
-  -357
-  -115
-  -112
-  -101
-   200
-    36
-   346
-   343
-   317
-   598
-   306
-   544
-   399
-   219
-   396
-   -79
-    78
-  -176
-  -434
-  -238
-  -745
-  -483
-  -649
-  -782
-  -371
-  -743
-  -237
-  -227
-  -202
-   399
-    72
-   677
-   665
-   608
-  1138
-   578
-  1018
-   741
-   403
-   724
-  -143
-   141
-  -314
-  -768
-  -419
- -1302
-  -838
- -1119
- -1339
-  -631
- -1255
-  -398
-  -379
-  -336
-   659
-   119
-  1107
-  1080
-   983
-  1831
-   926
-  1622
-  1174
-   637
-  1137
-  -223
-   220
-  -487
- -1186
-  -644
- -1993
- -1277
- -1699
- -2024
-  -951
- -1884
-  -595
-  -565
-  -498
-   976
-   176
-  1627
-  1583
-  1436
-  2664
-  1343
-  2344
-  1692
-   915
-  1629
-  -318
-   313
-  -690
- -1675
-  -907
- -2799
- -1788
- -2373
- -2820
- -1321
- -2611
-  -822
-  -779
-  -685
-  1339
-   241
-  2221
-  2155
-  1950
-  3610
-  1816
-  3163
-  2277
-  1228
-  2182
-  -424
-   419
-  -919
- -2228
- -1203
- -3707
- -2364
- -3130
- -3713
- -1735
- -3424
- -1076
- -1017
-  -893
-  1743
-   313
-  2880
-  2789
-  2515
-  4648
-  2334
-  4057
-  2917
-  1570
-  2785
-  -541
-   533
- -1168
- -2824
- -1523
- -4685
- -2983
- -3943
- -4670
- -2179
- -4294
- -1347
- -1272
- -1114
-  2173
-   389
-  3580
-  3462
-  3123
-  5763
-  2890
-  5016
-  3601
-  1937
-  3430
-  -665
-   654
- -1432
- -3459
- -1863
- -5724
- -3640
- -4805
- -5684
- -2643
- -5202
- -1629
- -1537
- -1345
-  2619
-   469
-  4306
-  4159
-  3747
-  6907
-  3459
-  5998
-  4301
-  2310
-  4087
-  -791
-   778
- -1701
- -4104
- -2208
- -6776
- -4304
- -5677
- -6708
- -3123
- -6140
- -1921
- -1810
- -1582
-  3080
-   551
-  5052
-  4875
-  4388
-  8081
-  4043
-  7004
-  5018
-  2693
-  4759
-  -920
-   902
- -1969
- -4748
- -2551
- -7825
- -4966
- -6543
- -7725
- -3594
- -7059
- -2207
- -2077
- -1814
-  3528
-   630
-  5778
-  5571
-  5010
-  9218
-  4608
-  7976
-  5710
-  3062
-  5406
- -1045
-  1026
- -2238
- -5391
- -2895
- -8871
- -5625
- -7406
- -8737
- -4061
- -7971
- -2490
- -2342
- -2044
-  3972
-   709
-  6495
-  6257
-  5606
- 10306
-  5148
-  8904
-  6370
-  3413
-  6022
- -1163
-  1141
- -2487
- -5987
- -3213
- -9839
- -6234
- -8203
- -9669
- -4492
- -8810
- -2750
- -2585
- -2254
-  4378
-   781
-  7149
-  6883
-  6182
- 11357
-  5670
-  9801
-  7006
-  3751
-  6615
- -1276
-  1252
- -2727
- -6560
- -3518
--10766
- -6817
- -8964
--10560
- -4884
- -9573
- -2986
- -2806
- -2445
-  4746
-   846
-  7739
-  7447
-  6684
- 12272
-  6123
- 10577
-  7557
-  4044
-  7127
- -1374
-  1347
- -2932
- -7050
- -3778
--11556
- -7313
- -9611
--11316
- -5250
--10285
- -3207
- -3011
- -2622
-  5087
-   906
-  8286
-  7968
-  7148
- 13118
-  6541
- 11293
-  8064
-  4313
-  7596
- -1464
-  1428
- -3106
- -7465
- -3998
--12223
- -7731
--10154
--11949
- -5541
--10848
- -3380
- -3172
- -2761
-  5354
-   954
-  8711
-  8373
-  7507
- 13768
-  6862
- 11841
-  8450
-  4517
-  7952
- -1531
-  1500
- -3261
- -7832
- -4193
--12811
- -8099
--10632
--12504
- -5795
--11341
- -3532
- -3313
- -2882
-  5586
-   994
-  9080
-  8722
-  7777
- 14257
-  7102
- 12248
-  8736
-  4668
-  8212
- -1581
-  1548
- -3362
- -8072
- -4319
--13191
- -8335
--10936
--12855
- -5955
--11648
- -3626
- -3399
- -2956
-  5725
-  1019
-  9297
-  8926
-  7996
- 14649
-  7294
- 12573
-  8964
-  4787
-  8418
- -1620
-  1585
- -3442
- -8259
- -4417
--13483
- -8515
--11162
--13107
- -6041
--11809
- -3674
- -3443
- -2992
-  5793
-  1030
-  9398
-  9019
-  8074
- 14781
-  7353
- 12665
-  9022
-  4814
-  8460
- -1626
-  1590
- -3451
- -8276
- -4423
--13493
+     0
+     4
+    21
+     4
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0
+     0

S5443_M/S5443.srcs/sources_1/new/MeasDataFifo/OscDataFormer.v

@@ -2,7 +2,7 @@
 (* keep_hierarchy = "yes" *)	
 module OscDataFormer
 #(	
-	parameter	AdcDataWidth		=	14,	
+	parameter	AdcDataWidth		=	16,	
 	parameter	ExtAdcDataWidth		=	AdcDataWidth+2,	
 	parameter	ChNum				=	1,
 	parameter	DataValCycles		=	16,
@@ -112,7 +112,8 @@ module OscDataFormer
 		if	(!Rst_i)	begin
 			if	(OscWind_i)	begin
 				if	(AdcDataVal_i)	begin
-					oscDataBusReg	<=	{adcDataExt,oscDataBusReg[OutDataWidth-1:AdcDataWidth+2]};	//first points
+					// oscDataBusReg	<=	{adcDataExt,oscDataBusReg[OutDataWidth-1:AdcDataWidth+2]};	//first points
+					oscDataBusReg	<=	{AdcData_i,oscDataBusReg[OutDataWidth-1:AdcDataWidth]};	//first points
 				end
 			end	else	begin
 				oscDataBusReg		<=	0;

S5443_M/S5443.srcs/sources_1/new/S5443TopSpectrumTb.v

@@ -40,8 +40,8 @@ module S5443TopSpectrumTb;
 	
 	localparam	[1:0]	CURRADCCHANNEL	=	2'b0;
 	//COMMANDS	FOR REG_MAP
-	parameter	[31:0]	MeasCmdBypass	=	{8'h11,8'h0,8'h63,7'h1,1'h1};
-	// parameter	[31:0]	MeasCmdFft 		=	{8'h11,8'h0,8'h63,7'h1,1'b1};
+	// parameter	[31:0]	MeasCmdBypass	=	{8'h11,8'h0,8'h63,7'h1,1'h1};
+	parameter	[31:0]	MeasCmdFft 		=	{8'h11,8'h0,8'h63,7'h4,1'b1};
 	parameter	[31:0]	AdcCtrl =	{8'h12,24'h2};
 	parameter	[31:0]	SensCtrlCmd =	{1'b0,21'h0,CURRADCCHANNEL,4'h0,4'b1};
 	parameter	[31:0]	DitherCmd 	= {8'h0E,8'd9,4'h0,4'h1,4'd11,4'h3};
@@ -369,7 +369,7 @@ end
 always	@(posedge	Clk41)	begin
 	if	(txCurrState	==	CMD)	begin
 		if	(cmdCnt	==	0)	begin
-			DspSpiData		<=	MeasCmdBypass;
+			DspSpiData		<=	MeasCmdFft;
 		end	else	if	(cmdCnt	==	1)	begin
 			DspSpiData		<=	MeasNum0RegCmd;
 		end	else	if	(cmdCnt	==	2)	begin