Добавлен контроль записи в fifo результатов измерений. Записывается количество равное значению из команды MeasNum. Актуализирован проект для FPGA_S.

S5443_M/S5443.srcs/sources_1/new/ExtDspInterface/DspInterface.v

@@ -62,6 +62,7 @@ module	DspInterface
 	output	Ss1_o,
 	input	Miso_i,
 	output	Miso_o,
+
 	
 	output	[CmdRegWidth-1:0]	CmdDataReg_o,
 	output	CmdDataVal_o,

S5443_M/S5443.srcs/sources_1/new/InternalDsp/MeasCtrlModule.v

@@ -326,7 +326,7 @@ module MeasCtrlModule
 				measWind	=	1'b0;
 			end
 		end	else	begin
-			measWind	<=	1'b0;
+			measWind	=	1'b0;
 		end
 	end
 

S5443_M/S5443.srcs/sources_1/new/MeasDataFifo/FifoController.v

@@ -33,6 +33,7 @@ module FifoController
 	input	PpiBusy_i,	
 	input	DspReadyForRx_i,
 	input	MeasDataVal_i,
+	input	[32-1:0]	MeasNum_i,
 	input	FullFlag_i,
 	input	EmptyFlag_i,
 	
@@ -45,7 +46,7 @@ module FifoController
 //  REG/WIRE
 //================================================================================
 	reg	rdEn;
-	
+	reg	[13:0]	wrCnt;
 //================================================================================
 //  ASSIGNMENTS
 //================================================================================
@@ -58,9 +59,23 @@ module FifoController
 
 always	@(posedge	Clk_i)	begin
 	if	(!Rst_i)	begin
-		if	(MeasDataVal_i)	begin
-			if	(!FullFlag_i)	begin
-				WrEn_o	<=	1'b1;
+		if	(WrEn_o)	begin
+			wrCnt	<=	wrCnt+14'd1;
+		end	
+	end	else	begin
+		wrCnt	<=	14'd0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(!FullFlag_i)	begin
+			if	(MeasDataVal_i)	begin
+				if	(wrCnt!=MeasNum_i)	begin
+					WrEn_o	<=	1'b1;
+				end	else	begin
+					WrEn_o	<=	1'b0;
+				end
 			end	else	begin
 				WrEn_o	<=	1'b0;
 			end

S5443_M/S5443.srcs/sources_1/new/MeasDataFifo/MeasDataFifoWrapper.v

@@ -39,15 +39,29 @@ module MeasDataFifoWrapper
 	
 	integer	i;
 	reg	[0:0]	rstFromDspPipe	[49:0];
+	
+	reg		[13:0]	rdCnt;
+	wire	rstOr;
+	
 //================================================================================
 //  ASSIGNMENTS
 //================================================================================
-	assign	MeasDataVal_o	=	rdEn;
-	assign	startMeasDspPos	=	(StartMeasDsp_i&(!startMeasDspReg));
+	assign	rstOr	=	Rst_i|startMeasDspPos;
+	assign	MeasDataVal_o		=	rdEn;
+	assign	startMeasDspPos		=	(StartMeasDsp_i&(!startMeasDspReg));
 //================================================================================
 //  CODING
 //================================================================================		
 
+always	@(posedge	Clk_i)	begin
+	if	(!rstOr)	begin
+		if	(rdEn)	begin
+			rdCnt	<=	rdCnt+14'd1;
+		end	
+	end	else	begin
+		rdCnt	<=	14'd0;
+	end
+end
 
 always	@(posedge	Clk_i)	begin
 	if	(!Rst_i)	begin
@@ -76,6 +90,7 @@ FifoController	FifoControllerInst
 	.Rst_i				(Rst_i|startMeasDspPos),	
 	.DspReadyForRx_i	(DspReadyForRx_i),	
 	.PpiBusy_i			(PpiBusy_i),	
+	.MeasNum_i			(MeasNum_i),	
 	.MeasDataVal_i		(MeasDataVal_i),
 	.FullFlag_i			(fullFlag),
 	.EmptyFlag_i		(emptyFlag),

S5443_M/S5443.srcs/sources_1/new/S5443Top.v

@@ -520,7 +520,6 @@ module	S5443Top
 	assign	Adc2InitCs_o	=	adc1InitCs;
 	assign	AdcInitRst_o	=	adcCtrl[0];
 
-	// assign	Led_o	=	ledReg	|(|ampEnNewStates);
 	assign	Led_o	=	ledReg	|(|ampEnNewStates);
 	
 	assign	StartMeasEvent_o	=	startMeasEvent;
@@ -557,7 +556,9 @@ module	S5443Top
 	assign	Trig6to1Dir_o	[5]	=	!measCtrl[21];
 	
 	assign	Trig6to1_io	[0]	=	(measCtrl[16])	?	1'bz:extPortsMuxedOut[0];	//1 - in, 0 - out
+	// assign	Trig6to1_io	[0]	=	(measCtrl[16])	?	1'bz:LpOutFs_o;	//1 - in, 0 - out
 	assign	Trig6to1_io	[1]	=	(measCtrl[17])	?	1'bz:extPortsMuxedOut[1];	//1 - in, 0 - out
+	// assign	Trig6to1_io	[1]	=	(measCtrl[17])	?	1'bz:LpOutFs_o;	//1 - in, 0 - out
 	assign	Trig6to1_io	[2]	=	(measCtrl[18])	?	1'bz:extPortsMuxedOut[2];	//1 - in, 0 - out
 	assign	Trig6to1_io	[3]	=	(measCtrl[19])	?	1'bz:extPortsMuxedOut[3];	//1 - in, 0 - out
 	assign	Trig6to1_io	[4]	=	(measCtrl[20])	?	1'bz:extPortsMuxedOut[4];	//1 - in, 0 - out

S5443_S/S5443.srcs/sources_1/new/ExtDspInterface/DspInterface.v

@@ -62,6 +62,7 @@ module	DspInterface
 	output	Ss1_o,
 	input	Miso_i,
 	output	Miso_o,
+
 	
 	output	[CmdRegWidth-1:0]	CmdDataReg_o,
 	output	CmdDataVal_o,

S5443_S/S5443.srcs/sources_1/new/InternalDsp/MeasCtrlModule.v

@@ -326,7 +326,7 @@ module MeasCtrlModule
 				measWind	=	1'b0;
 			end
 		end	else	begin
-			measWind	<=	1'b0;
+			measWind	=	1'b0;
 		end
 	end
 

S5443_S/S5443.srcs/sources_1/new/MeasDataFifo/FifoController.v

@@ -33,6 +33,7 @@ module FifoController
 	input	PpiBusy_i,	
 	input	DspReadyForRx_i,
 	input	MeasDataVal_i,
+	input	[32-1:0]	MeasNum_i,
 	input	FullFlag_i,
 	input	EmptyFlag_i,
 	
@@ -45,7 +46,7 @@ module FifoController
 //  REG/WIRE
 //================================================================================
 	reg	rdEn;
-	
+	reg	[13:0]	wrCnt;
 //================================================================================
 //  ASSIGNMENTS
 //================================================================================
@@ -58,9 +59,23 @@ module FifoController
 
 always	@(posedge	Clk_i)	begin
 	if	(!Rst_i)	begin
-		if	(MeasDataVal_i)	begin
-			if	(!FullFlag_i)	begin
-				WrEn_o	<=	1'b1;
+		if	(WrEn_o)	begin
+			wrCnt	<=	wrCnt+14'd1;
+		end	
+	end	else	begin
+		wrCnt	<=	14'd0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(!FullFlag_i)	begin
+			if	(MeasDataVal_i)	begin
+				if	(wrCnt!=MeasNum_i)	begin
+					WrEn_o	<=	1'b1;
+				end	else	begin
+					WrEn_o	<=	1'b0;
+				end
 			end	else	begin
 				WrEn_o	<=	1'b0;
 			end

S5443_S/S5443.srcs/sources_1/new/MeasDataFifo/MeasDataFifoWrapper.v

@@ -39,15 +39,29 @@ module MeasDataFifoWrapper
 	
 	integer	i;
 	reg	[0:0]	rstFromDspPipe	[49:0];
+	
+	reg		[13:0]	rdCnt;
+	wire	rstOr;
+	
 //================================================================================
 //  ASSIGNMENTS
 //================================================================================
-	assign	MeasDataVal_o	=	rdEn;
-	assign	startMeasDspPos	=	(StartMeasDsp_i&(!startMeasDspReg));
+	assign	rstOr	=	Rst_i|startMeasDspPos;
+	assign	MeasDataVal_o		=	rdEn;
+	assign	startMeasDspPos		=	(StartMeasDsp_i&(!startMeasDspReg));
 //================================================================================
 //  CODING
 //================================================================================		
 
+always	@(posedge	Clk_i)	begin
+	if	(!rstOr)	begin
+		if	(rdEn)	begin
+			rdCnt	<=	rdCnt+14'd1;
+		end	
+	end	else	begin
+		rdCnt	<=	14'd0;
+	end
+end
 
 always	@(posedge	Clk_i)	begin
 	if	(!Rst_i)	begin
@@ -76,6 +90,7 @@ FifoController	FifoControllerInst
 	.Rst_i				(Rst_i|startMeasDspPos),	
 	.DspReadyForRx_i	(DspReadyForRx_i),	
 	.PpiBusy_i			(PpiBusy_i),	
+	.MeasNum_i			(MeasNum_i),	
 	.MeasDataVal_i		(MeasDataVal_i),
 	.FullFlag_i			(fullFlag),
 	.EmptyFlag_i		(emptyFlag),