Реализованы измерения ГВЗ. Окно считается на 150МГц. Данные измерений упаковываются согласно документу лежащему тут \\192.168.210.1\Public\S5443\Docs\S5435v4port_reg

S5443_M/S5443.srcs/sources_1/new/Clk200Gen.v

@@ -24,7 +24,7 @@ PLLE2_ADV #(
       	.CLKOUT1_DIVIDE		(120),
       	.CLKOUT1_DUTY_CYCLE	(0.5),
       	.CLKOUT1_PHASE		(0.0),
-      	.CLKOUT2_DIVIDE		(6),
+      	.CLKOUT2_DIVIDE		(8),
       	.CLKOUT2_DUTY_CYCLE	(0.5),
       	.CLKOUT2_PHASE		(0.0),
       	.CLKOUT3_DIVIDE		(120),

S5443_M/S5443.srcs/sources_1/new/InternalDsp/InternalDsp.v

@@ -98,8 +98,11 @@ module InternalDsp
 	
 	wire	[WindWidth-1:0]	wind;			
 
-	wire	[NcoWidth-1:0]	ncoCos;
-	wire	[NcoWidth-1:0]	ncoSin;
+	wire	[NcoWidth-1:0]	ncoCosFirstTone;
+	wire	[NcoWidth-1:0]	ncoSinFirstTone;
+	
+	wire	[NcoWidth-1:0]	ncoCosSecondTone;
+	wire	[NcoWidth-1:0]	ncoSinSecondTone;
 	
 	wire	[CorrAdcDataWidth-1:0]	adcDataBus	[ChNum-1:0];
 	wire	[CorrAdcDataWidth-1:0]	adcDataBusExt	[ChNum-1:0];
@@ -162,17 +165,17 @@ module InternalDsp
 	assign	Adc1ImR1Data_o	=	resultImBus	[ChNum-3];
 	assign	Adc1ReR1Data_o	=	resultReBus	[ChNum-3];
 	//adc2                 
-	assign	Adc2ImR2Data_o	=	resultImBus	[ChNum-2];
-	assign	Adc2ReR2Data_o	=	resultReBus	[ChNum-2];
-	assign	Adc2ImT2Data_o	=	resultImBus	[ChNum-1];
-	assign	Adc2ReT2Data_o	=	resultReBus	[ChNum-1];
+	assign	Adc2ImR2Data_o	=	resultImBus	[ChNum-1];
+	assign	Adc2ReR2Data_o	=	resultReBus	[ChNum-1];
+	assign	Adc2ImT2Data_o	=	resultImBus	[ChNum-2];
+	assign	Adc2ReT2Data_o	=	resultReBus	[ChNum-2];
 	
 	
 	assign	MeasDataRdy_o	=	&resultValBus;
 	assign	EndMeas_o		=	stopMeas;
 	
-	assign	NcoCos_o	=	ncoCos;
-	assign	NcoSin_o	=	ncoSin;
+	assign	NcoCos_o	=	ncoCosFirstTone;
+	assign	NcoSin_o	=	ncoSinSecondTone;
 	assign	MeasWind_o	=	measWind;
 	
 	assign	CalModeDone_o	=	&calDone;
@@ -286,17 +289,40 @@ CordicNco
 	.IterNum	(15),
 	.EnSinN		(1)
 )
-ncoInst
+ncoFirstTone
+(
+	.Clk_i		(Clk_i),
+	.Rst_i		(Rst_i|NcoRst_i),
+	.Val_i		(1'b1),
+	// .PhaseInc_i	({ifFtwHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],ifFtwLReg}),
+	.PhaseInc_i	(32'h40000000),
+	.WindVal_i	(1'b1),
+	.WinType_i	(),
+	.Wind_o		(),
+	.Sin_o		(ncoSinFirstTone),
+	.Cos_o		(ncoCosFirstTone),	
+	.Val_o		()
+);
+
+CordicNco		
+#(	
+	.ODatWidth	(NcoWidth),
+	.PhIncWidth	(WindNcoPhIncWidth),
+	.IterNum	(15),
+	.EnSinN		(1)
+)
+ncoSecondTone
 (
 	.Clk_i		(Clk_i),
 	.Rst_i		(Rst_i|NcoRst_i),
 	.Val_i		(1'b1),
-	.PhaseInc_i	({ifFtwHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],ifFtwLReg}),
+	// .PhaseInc_i	({ifFtwHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],ifFtwLReg}),
+	.PhaseInc_i	(32'h31eb851e),
 	.WindVal_i	(1'b1),
 	.WinType_i	(),
 	.Wind_o		(),
-	.Sin_o		(ncoSin),
-	.Cos_o		(ncoCos),	
+	.Sin_o		(ncoSinSecondTone),
+	.Cos_o		(ncoCosSecondTone),	
 	.Val_o		()
 );
 
@@ -323,7 +349,7 @@ end
 //------------------------------------------------
 //Generating needed amount of calculating channels
 generate
-	for	(g=0;	g<ChNum;	g=g+1)	begin	:DspChannel
+	for	(g=0;	g<ChNum-2;	g=g+1)	begin	:DspChannel
 	
 		AdcCalibration 
 		#(	
@@ -352,7 +378,7 @@ generate
 			.WindNormCoefWidth	(WindNormCoefWidth),
 			.IntermediateWidth	(IntermediateWidth)
 		)
-		DspPipelineInst
+		DspFirstTone
 		(
 			.Clk_i				(Clk_i),
 			.Rst_i				(Rst_i),
@@ -363,14 +389,46 @@ generate
 			.AverageNoizeLvl_i	(averageNoizeLvl),
 			.AdcData_i			(gatedAdcDataBus[g]),
 			.Wind_i				(wind),
-			.NcoSin_i			(ncoSin),
-			.NcoCos_i			(ncoCos),	
+			.NcoSin_i			(ncoSinFirstTone),
+			.NcoCos_i			(ncoCosFirstTone),	
 			.NormCoef_i			(windNormCoef),
 
 			.CorrResultIm_o		(resultImBus[g]),
 			.CorrResultRe_o		(resultReBus[g]),
 			.CorrResultVal_o	(resultValBus[g])
 		);
+		
+		DspPipeline	
+		#(	
+			.AdcDataWidth		(AdcDataWidth),
+			.AccWidth			(AccWidth),
+			.WindWidth			(WindWidth),
+			.NcoWidth			(NcoWidth),
+			.ResultWidth		(ResultWidth),
+			.WindCorrCoefWidth	(WindCorrCoefWidth),
+			.WindNormCoefWidth	(WindNormCoefWidth),
+			.IntermediateWidth	(IntermediateWidth)
+		)
+		DspSecondTone
+		(
+			.Clk_i				(Clk_i),
+			.Rst_i				(Rst_i),
+			.Val_i				(measWind),
+			.StartFpConv_i		(StartFpConv),
+			
+			.FilterCorrCoef_i	({filterCorrCoefHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],filterCorrCoefLReg}),
+			.AverageNoizeLvl_i	(averageNoizeLvl),
+			.AdcData_i			(gatedAdcDataBus[g]),
+			.Wind_i				(wind),
+			.NcoSin_i			(ncoSinSecondTone),
+			.NcoCos_i			(ncoCosSecondTone),	
+			.NormCoef_i			(windNormCoef),
+
+			.CorrResultIm_o		(resultImBus[g+2]),
+			.CorrResultRe_o		(resultReBus[g+2]),
+			.CorrResultVal_o	(resultValBus[g+2])
+		);
+		
 	end
 endgenerate
 

S5443_M/S5443.srcs/sources_1/new/InternalDsp/Win_calc.v

@@ -35,7 +35,7 @@ module Win_calc	(
 //  REG/WIRE
 //================================================================================
 	
-	reg			[3:0]	calc_cycle;
+	reg			[2:0]	calc_cycle;
 	reg	signed	[17:0]	a1;		
 	reg signed	[17:0]	b; 	
 	reg signed	[17:0]	c1;
@@ -136,36 +136,30 @@ always	@(*)	begin
 	end
 end
 
-always	@(negedge	wind_clk)	begin
+always	@(posedge	wind_clk)	begin
 	if	(!reset_i)	begin
-		// if	(MeasWind_i)	begin
 			case	(calc_cycle)
-				4'd1: 	
+				3'd0: 	
 						begin
 							a1	<=	A5;
 							c1	<=	A4;
 							c2	<=	A3;
+							// b	<=	win_value_i[31]	?	18'h3FFFF	-	win_value_i[31:14]	:	win_value_i	[31:14];
 							b	<=	bCurr;
 						end
 						
-				4'd2:	
+				3'd1:	
 						begin
 							a1	<=	p2[34:17];
 							c1	<=	A2;
 							c2	<=	A1;
 						end
-				4'd3:	
+				3'd2:	
 						begin
 							a1	<=	p2[34:17];
 							c1	<=	b;
 						end
 			endcase
-		// end	else	begin
-			// a1	<=	18'b0;
-			// c1	<=	18'b0;
-			// c2	<=	18'b0;
-			// b	<=	18'b0;
-		// end
 	end	else	begin
 		a1	<=	18'b0;
 		c1	<=	18'b0;
@@ -173,33 +167,6 @@ always	@(negedge	wind_clk)	begin
 		b	<=	18'b0;
 	end
 end
-
-// always	@(*)	begin
-	// if	(!reset_i)	begin
-		// if	(MeasWind_i)	begin
-			// case	(calc_cycle)
-				// 3'd1: 	
-						// begin
-							// a1	=	A5;
-							// c1	=	A4;
-							// c2	=	A3;
-							// b	=	bCurr;
-						// end
-			// endcase
-		// end	else	begin
-			// a1	=	18'b0;
-			// c1	=	18'b0;
-			// c2	=	18'b0;
-			// b	=	18'b0;
-		// end
-	// end	else	begin
-		// a1	=	18'b0;
-		// c1	=	18'b0;
-		// c2	=	18'b0;
-		// b	=	18'b0;
-	// end
-// end
-
 		
 always	@(posedge	wind_clk)	begin
 	if	(!reset_i)	begin
@@ -242,17 +209,13 @@ end
 
 always	@(posedge	wind_clk)	begin
 	if	(!reset_i)	begin
-		if	(MeasWind_i)	begin
-			if	(calc_cycle	!=	4'd3)	begin
-				calc_cycle	<=	calc_cycle	+	4'd1;
+			if	(calc_cycle	!=	3'd2)	begin
+				calc_cycle	<=	calc_cycle	+	3'd1;
 			end	else	begin
-				calc_cycle	<=	4'd0;
+				calc_cycle	<=	3'd0;
 			end
-		end	else	begin
-			calc_cycle	<=	4'd0;
-		end
 	end	else	begin
-		calc_cycle	<=	4'd0;
+		calc_cycle	<=	3'd0;
 	end
 end
 
@@ -284,7 +247,7 @@ DSP48E1 #(
       .INMODEREG(0),                    // Number of pipeline stages for INMODE (0 or 1)
       .MREG(0),                         // Number of multiplier pipeline stages (0 or 1)
       .OPMODEREG(0),                    // Number of pipeline stages for OPMODE (0 or 1)
-      .PREG(1)                          // Number of pipeline stages for P (0 or 1)
+      .PREG(0)                          // Number of pipeline stages for P (0 or 1)
    )
 FirstStage (
       // Cascade: 30-bit (each) output: Cascade Ports
@@ -310,8 +273,8 @@ FirstStage (
       // Control: 4-bit (each) input: Control Inputs/Status Bits
       .ALUMODE(4'b0000),               // 4-bit input: ALU control input
       .CARRYINSEL(3'b000),         // 3-bit input: Carry select input
-      // .CLK(1'b0),                       // 1-bit input: Clock input
-      .CLK(wind_clk),                       // 1-bit input: Clock input
+      .CLK(1'b0),                       // 1-bit input: Clock input
+      // .CLK(wind_clk),                       // 1-bit input: Clock input
       .INMODE(5'b00000),                 // 5-bit input: INMODE control input
       .OPMODE(7'b0110101),                 // 7-bit input: Operation mode input
       // Data: 30-bit (each) input: Data Ports
@@ -332,7 +295,7 @@ FirstStage (
       .CECTRL(1'b1),                 // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
       .CED(1'b1),                       // 1-bit input: Clock enable input for DREG
       .CEINMODE(1'b1),             // 1-bit input: Clock enable input for INMODEREG
-      .CEM(1'b0),                       // 1-bit input: Clock enable input for MREG
+      .CEM(1'b1),                       // 1-bit input: Clock enable input for MREG
       .CEP(1'b1),                       // 1-bit input: Clock enable input for PREG
       .RSTA(1'b0),                     // 1-bit input: Reset input for AREG
       .RSTALLCARRYIN(1'b0),   // 1-bit input: Reset input for CARRYINREG
@@ -342,8 +305,8 @@ FirstStage (
       .RSTCTRL(1'b0),               // 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
       .RSTD(1'b0),                     // 1-bit input: Reset input for DREG and ADREG
       .RSTINMODE(1'b0),           // 1-bit input: Reset input for INMODEREG
-      .RSTM(reset_i),                     // 1-bit input: Reset input for MREG
-      .RSTP(reset_i)                      // 1-bit input: Reset input for PREG
+      .RSTM(1'b0),                     // 1-bit input: Reset input for MREG
+      .RSTP(1'b0)                      // 1-bit input: Reset input for PREG
 );
    
 DSP48E1 #(
@@ -422,8 +385,8 @@ SecondStage (
       .CECTRL(1'b1),                 // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
       .CED(1'b1),                       // 1-bit input: Clock enable input for DREG
       .CEINMODE(1'b1),             // 1-bit input: Clock enable input for INMODEREG
-      .CEM(1'b0),                       // 1-bit input: Clock enable input for MREG
-      .CEP(1'b0),                       // 1-bit input: Clock enable input for PREG
+      .CEM(1'b1),                       // 1-bit input: Clock enable input for MREG
+      .CEP(1'b1),                       // 1-bit input: Clock enable input for PREG
       .RSTA(1'b0),                     // 1-bit input: Reset input for AREG
       .RSTALLCARRYIN(1'b0),   // 1-bit input: Reset input for CARRYINREG
       .RSTALUMODE(1'b0),         // 1-bit input: Reset input for ALUMODEREG
@@ -432,8 +395,8 @@ SecondStage (
       .RSTCTRL(1'b0),               // 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
       .RSTD(1'b0),                     // 1-bit input: Reset input for DREG and ADREG
       .RSTINMODE(1'b0),           // 1-bit input: Reset input for INMODEREG
-      .RSTM(reset_i),                     // 1-bit input: Reset input for MREG
-      .RSTP(reset_i)                      // 1-bit input: Reset input for PREG
+      .RSTM(1'b0),                     // 1-bit input: Reset input for MREG
+      .RSTP(1'b0)                      // 1-bit input: Reset input for PREG
 );
 
 endmodule

S5443_M/S5443.srcs/sources_1/new/S5443TopPulseProfileTb.v

@@ -180,8 +180,11 @@ module S5443TopPulseProfileTb;
 	reg	[31:0]	DspSpiData;
 	reg		startCalcCmdReg;
 						
-	wire	[17:0]	cos_value;	
-	wire	[17:0]	sin_value;				
+	wire	signed	[17:0]	cosValueFirstTone;	
+	wire	signed	[17:0]	sinValueFirstTone;		
+	
+	wire	signed	[17:0]	cosValueSecondTone;	
+	wire	signed	[17:0]	sinValueSecondTone;				
 
 	wire	ExtDspTrigPos0	=	(tb_cnt	>=	180	&&	tb_cnt	<=	181)?	1'b1:1'b0;
 	wire	ExtDspTrigNeg0	=	(tb_cnt	>=	180	&&	tb_cnt	<=	181)?	1'b0:1'b1;
@@ -201,6 +204,8 @@ module S5443TopPulseProfileTb;
 	assign	trig0R	=	trig0;
     assign	trig1R	=	trig1;
 	
+	reg		signed	[35:0]	twoToneSignal;
+	wire	signed	[13:0]	twoToneSignalCut	=	twoToneSignal[35-:14];
 //==========================================================================================
 //clocks gen
 	always	#10 Clk50	=	~Clk50;
@@ -255,27 +260,56 @@ end
 wire	Adc1DataDa0P;
 wire	Adc1DataDa1P;
 
-// wire	[31:0]	test	=	32'h2351eb85;
-wire	[31:0]	test	=	32'h40000000;
+wire	[31:0]	test2	=	32'h31eb851e;
+wire	[31:0]	test1	=	32'h40000000;
 CordicNco		
 #(	.ODatWidth	(18),
 	.PhIncWidth	(32),
 	.IterNum	(10),
 	.EnSinN		(0))
-ncoInst
+FirstToneGen
 (
 	.Clk_i				(Clk50),
 	.Rst_i				(rst),
 	.Val_i				(1'b1),
-	.PhaseInc_i			(test),
+	.PhaseInc_i			(test1),
 	.WindVal_i			(1'b1),
 	.WinType_i			(),
 	.Wind_o				(),
-	.Sin_o				(sin_value),
-	.Cos_o				(cos_value),
+	.Sin_o				(sinValueFirstTone),
+	.Cos_o				(),
 	.Val_o				()
 );
 
+CordicNco		
+#(	.ODatWidth	(18),
+	.PhIncWidth	(32),
+	.IterNum	(10),
+	.EnSinN		(0))
+SecondToneGen
+(
+	.Clk_i				(Clk50),
+	.Rst_i				(rst),
+	.Val_i				(1'b1),
+	.PhaseInc_i			(test2),
+	.WindVal_i			(1'b1),
+	.WinType_i			(),
+	.Wind_o				(),
+	.Sin_o				(sinValueSecondTone),
+	.Cos_o				(),
+	.Val_o				()
+);
+
+
+
+always	@(posedge	Clk50)	begin
+	if	(!rst)	begin
+		twoToneSignal	<=	sinValueFirstTone*sinValueSecondTone;
+	end	else	begin
+		twoToneSignal	<=	0;
+	end
+end
+
 
 S5443Top MasterFpga 
 (
@@ -349,7 +383,7 @@ S5443Top MasterFpga
 	.DspReadyForRx_i		(1'b0),
 	.DspReadyForRxToFpgaS_o	(),
 	.AmpEn_o				(),	//	0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
-	.AdcData_i				(sin_value[17-:14])
+	.AdcData_i				(twoToneSignalCut)
 	// .AdcData_i			(Data_i)
 );
 

S5443_S/S5443.srcs/sources_1/new/Clk200Gen.v

@@ -24,7 +24,7 @@ PLLE2_ADV #(
       	.CLKOUT1_DIVIDE		(120),
       	.CLKOUT1_DUTY_CYCLE	(0.5),
       	.CLKOUT1_PHASE		(0.0),
-      	.CLKOUT2_DIVIDE		(6),
+      	.CLKOUT2_DIVIDE		(8),
       	.CLKOUT2_DUTY_CYCLE	(0.5),
       	.CLKOUT2_PHASE		(0.0),
       	.CLKOUT3_DIVIDE		(120),

S5443_S/S5443.srcs/sources_1/new/InternalDsp/InternalDsp.v

@@ -98,8 +98,11 @@ module InternalDsp
 	
 	wire	[WindWidth-1:0]	wind;			
 
-	wire	[NcoWidth-1:0]	ncoCos;
-	wire	[NcoWidth-1:0]	ncoSin;
+	wire	[NcoWidth-1:0]	ncoCosFirstTone;
+	wire	[NcoWidth-1:0]	ncoSinFirstTone;
+	
+	wire	[NcoWidth-1:0]	ncoCosSecondTone;
+	wire	[NcoWidth-1:0]	ncoSinSecondTone;
 	
 	wire	[CorrAdcDataWidth-1:0]	adcDataBus	[ChNum-1:0];
 	wire	[CorrAdcDataWidth-1:0]	adcDataBusExt	[ChNum-1:0];
@@ -162,17 +165,17 @@ module InternalDsp
 	assign	Adc1ImR1Data_o	=	resultImBus	[ChNum-3];
 	assign	Adc1ReR1Data_o	=	resultReBus	[ChNum-3];
 	//adc2                 
-	assign	Adc2ImR2Data_o	=	resultImBus	[ChNum-2];
-	assign	Adc2ReR2Data_o	=	resultReBus	[ChNum-2];
-	assign	Adc2ImT2Data_o	=	resultImBus	[ChNum-1];
-	assign	Adc2ReT2Data_o	=	resultReBus	[ChNum-1];
+	assign	Adc2ImR2Data_o	=	resultImBus	[ChNum-1];
+	assign	Adc2ReR2Data_o	=	resultReBus	[ChNum-1];
+	assign	Adc2ImT2Data_o	=	resultImBus	[ChNum-2];
+	assign	Adc2ReT2Data_o	=	resultReBus	[ChNum-2];
 	
 	
 	assign	MeasDataRdy_o	=	&resultValBus;
 	assign	EndMeas_o		=	stopMeas;
 	
-	assign	NcoCos_o	=	ncoCos;
-	assign	NcoSin_o	=	ncoSin;
+	assign	NcoCos_o	=	ncoCosFirstTone;
+	assign	NcoSin_o	=	ncoSinSecondTone;
 	assign	MeasWind_o	=	measWind;
 	
 	assign	CalModeDone_o	=	&calDone;
@@ -286,17 +289,40 @@ CordicNco
 	.IterNum	(15),
 	.EnSinN		(1)
 )
-ncoInst
+ncoFirstTone
+(
+	.Clk_i		(Clk_i),
+	.Rst_i		(Rst_i|NcoRst_i),
+	.Val_i		(1'b1),
+	// .PhaseInc_i	({ifFtwHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],ifFtwLReg}),
+	.PhaseInc_i	(32'h40000000),
+	.WindVal_i	(1'b1),
+	.WinType_i	(),
+	.Wind_o		(),
+	.Sin_o		(ncoSinFirstTone),
+	.Cos_o		(ncoCosFirstTone),	
+	.Val_o		()
+);
+
+CordicNco		
+#(	
+	.ODatWidth	(NcoWidth),
+	.PhIncWidth	(WindNcoPhIncWidth),
+	.IterNum	(15),
+	.EnSinN		(1)
+)
+ncoSecondTone
 (
 	.Clk_i		(Clk_i),
 	.Rst_i		(Rst_i|NcoRst_i),
 	.Val_i		(1'b1),
-	.PhaseInc_i	({ifFtwHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],ifFtwLReg}),
+	// .PhaseInc_i	({ifFtwHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],ifFtwLReg}),
+	.PhaseInc_i	(32'h31eb851e),
 	.WindVal_i	(1'b1),
 	.WinType_i	(),
 	.Wind_o		(),
-	.Sin_o		(ncoSin),
-	.Cos_o		(ncoCos),	
+	.Sin_o		(ncoSinSecondTone),
+	.Cos_o		(ncoCosSecondTone),	
 	.Val_o		()
 );
 
@@ -323,7 +349,7 @@ end
 //------------------------------------------------
 //Generating needed amount of calculating channels
 generate
-	for	(g=0;	g<ChNum;	g=g+1)	begin	:DspChannel
+	for	(g=0;	g<ChNum-2;	g=g+1)	begin	:DspChannel
 	
 		AdcCalibration 
 		#(	
@@ -352,7 +378,7 @@ generate
 			.WindNormCoefWidth	(WindNormCoefWidth),
 			.IntermediateWidth	(IntermediateWidth)
 		)
-		DspPipelineInst
+		DspFirstTone
 		(
 			.Clk_i				(Clk_i),
 			.Rst_i				(Rst_i),
@@ -363,14 +389,46 @@ generate
 			.AverageNoizeLvl_i	(averageNoizeLvl),
 			.AdcData_i			(gatedAdcDataBus[g]),
 			.Wind_i				(wind),
-			.NcoSin_i			(ncoSin),
-			.NcoCos_i			(ncoCos),	
+			.NcoSin_i			(ncoSinFirstTone),
+			.NcoCos_i			(ncoCosFirstTone),	
 			.NormCoef_i			(windNormCoef),
 
 			.CorrResultIm_o		(resultImBus[g]),
 			.CorrResultRe_o		(resultReBus[g]),
 			.CorrResultVal_o	(resultValBus[g])
 		);
+		
+		DspPipeline	
+		#(	
+			.AdcDataWidth		(AdcDataWidth),
+			.AccWidth			(AccWidth),
+			.WindWidth			(WindWidth),
+			.NcoWidth			(NcoWidth),
+			.ResultWidth		(ResultWidth),
+			.WindCorrCoefWidth	(WindCorrCoefWidth),
+			.WindNormCoefWidth	(WindNormCoefWidth),
+			.IntermediateWidth	(IntermediateWidth)
+		)
+		DspSecondTone
+		(
+			.Clk_i				(Clk_i),
+			.Rst_i				(Rst_i),
+			.Val_i				(measWind),
+			.StartFpConv_i		(StartFpConv),
+			
+			.FilterCorrCoef_i	({filterCorrCoefHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],filterCorrCoefLReg}),
+			.AverageNoizeLvl_i	(averageNoizeLvl),
+			.AdcData_i			(gatedAdcDataBus[g]),
+			.Wind_i				(wind),
+			.NcoSin_i			(ncoSinSecondTone),
+			.NcoCos_i			(ncoCosSecondTone),	
+			.NormCoef_i			(windNormCoef),
+
+			.CorrResultIm_o		(resultImBus[g+2]),
+			.CorrResultRe_o		(resultReBus[g+2]),
+			.CorrResultVal_o	(resultValBus[g+2])
+		);
+		
 	end
 endgenerate
 

S5443_S/S5443.srcs/sources_1/new/InternalDsp/Win_calc.v

@@ -35,7 +35,7 @@ module Win_calc	(
 //  REG/WIRE
 //================================================================================
 	
-	reg			[3:0]	calc_cycle;
+	reg			[2:0]	calc_cycle;
 	reg	signed	[17:0]	a1;		
 	reg signed	[17:0]	b; 	
 	reg signed	[17:0]	c1;
@@ -136,36 +136,30 @@ always	@(*)	begin
 	end
 end
 
-always	@(negedge	wind_clk)	begin
+always	@(posedge	wind_clk)	begin
 	if	(!reset_i)	begin
-		// if	(MeasWind_i)	begin
 			case	(calc_cycle)
-				4'd1: 	
+				3'd0: 	
 						begin
 							a1	<=	A5;
 							c1	<=	A4;
 							c2	<=	A3;
+							// b	<=	win_value_i[31]	?	18'h3FFFF	-	win_value_i[31:14]	:	win_value_i	[31:14];
 							b	<=	bCurr;
 						end
 						
-				4'd2:	
+				3'd1:	
 						begin
 							a1	<=	p2[34:17];
 							c1	<=	A2;
 							c2	<=	A1;
 						end
-				4'd3:	
+				3'd2:	
 						begin
 							a1	<=	p2[34:17];
 							c1	<=	b;
 						end
 			endcase
-		// end	else	begin
-			// a1	<=	18'b0;
-			// c1	<=	18'b0;
-			// c2	<=	18'b0;
-			// b	<=	18'b0;
-		// end
 	end	else	begin
 		a1	<=	18'b0;
 		c1	<=	18'b0;
@@ -173,33 +167,6 @@ always	@(negedge	wind_clk)	begin
 		b	<=	18'b0;
 	end
 end
-
-// always	@(*)	begin
-	// if	(!reset_i)	begin
-		// if	(MeasWind_i)	begin
-			// case	(calc_cycle)
-				// 3'd1: 	
-						// begin
-							// a1	=	A5;
-							// c1	=	A4;
-							// c2	=	A3;
-							// b	=	bCurr;
-						// end
-			// endcase
-		// end	else	begin
-			// a1	=	18'b0;
-			// c1	=	18'b0;
-			// c2	=	18'b0;
-			// b	=	18'b0;
-		// end
-	// end	else	begin
-		// a1	=	18'b0;
-		// c1	=	18'b0;
-		// c2	=	18'b0;
-		// b	=	18'b0;
-	// end
-// end
-
 		
 always	@(posedge	wind_clk)	begin
 	if	(!reset_i)	begin
@@ -242,17 +209,13 @@ end
 
 always	@(posedge	wind_clk)	begin
 	if	(!reset_i)	begin
-		if	(MeasWind_i)	begin
-			if	(calc_cycle	!=	4'd3)	begin
-				calc_cycle	<=	calc_cycle	+	4'd1;
+			if	(calc_cycle	!=	3'd2)	begin
+				calc_cycle	<=	calc_cycle	+	3'd1;
 			end	else	begin
-				calc_cycle	<=	4'd0;
+				calc_cycle	<=	3'd0;
 			end
-		end	else	begin
-			calc_cycle	<=	4'd0;
-		end
 	end	else	begin
-		calc_cycle	<=	4'd0;
+		calc_cycle	<=	3'd0;
 	end
 end
 
@@ -284,7 +247,7 @@ DSP48E1 #(
       .INMODEREG(0),                    // Number of pipeline stages for INMODE (0 or 1)
       .MREG(0),                         // Number of multiplier pipeline stages (0 or 1)
       .OPMODEREG(0),                    // Number of pipeline stages for OPMODE (0 or 1)
-      .PREG(1)                          // Number of pipeline stages for P (0 or 1)
+      .PREG(0)                          // Number of pipeline stages for P (0 or 1)
    )
 FirstStage (
       // Cascade: 30-bit (each) output: Cascade Ports
@@ -310,8 +273,8 @@ FirstStage (
       // Control: 4-bit (each) input: Control Inputs/Status Bits
       .ALUMODE(4'b0000),               // 4-bit input: ALU control input
       .CARRYINSEL(3'b000),         // 3-bit input: Carry select input
-      // .CLK(1'b0),                       // 1-bit input: Clock input
-      .CLK(wind_clk),                       // 1-bit input: Clock input
+      .CLK(1'b0),                       // 1-bit input: Clock input
+      // .CLK(wind_clk),                       // 1-bit input: Clock input
       .INMODE(5'b00000),                 // 5-bit input: INMODE control input
       .OPMODE(7'b0110101),                 // 7-bit input: Operation mode input
       // Data: 30-bit (each) input: Data Ports
@@ -332,7 +295,7 @@ FirstStage (
       .CECTRL(1'b1),                 // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
       .CED(1'b1),                       // 1-bit input: Clock enable input for DREG
       .CEINMODE(1'b1),             // 1-bit input: Clock enable input for INMODEREG
-      .CEM(1'b0),                       // 1-bit input: Clock enable input for MREG
+      .CEM(1'b1),                       // 1-bit input: Clock enable input for MREG
       .CEP(1'b1),                       // 1-bit input: Clock enable input for PREG
       .RSTA(1'b0),                     // 1-bit input: Reset input for AREG
       .RSTALLCARRYIN(1'b0),   // 1-bit input: Reset input for CARRYINREG
@@ -342,8 +305,8 @@ FirstStage (
       .RSTCTRL(1'b0),               // 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
       .RSTD(1'b0),                     // 1-bit input: Reset input for DREG and ADREG
       .RSTINMODE(1'b0),           // 1-bit input: Reset input for INMODEREG
-      .RSTM(reset_i),                     // 1-bit input: Reset input for MREG
-      .RSTP(reset_i)                      // 1-bit input: Reset input for PREG
+      .RSTM(1'b0),                     // 1-bit input: Reset input for MREG
+      .RSTP(1'b0)                      // 1-bit input: Reset input for PREG
 );
    
 DSP48E1 #(
@@ -422,8 +385,8 @@ SecondStage (
       .CECTRL(1'b1),                 // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
       .CED(1'b1),                       // 1-bit input: Clock enable input for DREG
       .CEINMODE(1'b1),             // 1-bit input: Clock enable input for INMODEREG
-      .CEM(1'b0),                       // 1-bit input: Clock enable input for MREG
-      .CEP(1'b0),                       // 1-bit input: Clock enable input for PREG
+      .CEM(1'b1),                       // 1-bit input: Clock enable input for MREG
+      .CEP(1'b1),                       // 1-bit input: Clock enable input for PREG
       .RSTA(1'b0),                     // 1-bit input: Reset input for AREG
       .RSTALLCARRYIN(1'b0),   // 1-bit input: Reset input for CARRYINREG
       .RSTALUMODE(1'b0),         // 1-bit input: Reset input for ALUMODEREG
@@ -432,8 +395,8 @@ SecondStage (
       .RSTCTRL(1'b0),               // 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
       .RSTD(1'b0),                     // 1-bit input: Reset input for DREG and ADREG
       .RSTINMODE(1'b0),           // 1-bit input: Reset input for INMODEREG
-      .RSTM(reset_i),                     // 1-bit input: Reset input for MREG
-      .RSTP(reset_i)                      // 1-bit input: Reset input for PREG
+      .RSTM(1'b0),                     // 1-bit input: Reset input for MREG
+      .RSTP(1'b0)                      // 1-bit input: Reset input for PREG
 );
 
 endmodule