Перекомпилина MeasDataFifo .

Добавлены тестовые изменения:
	1. Сброс для NCO при нарастующем фронте сигнала запуска измерений от DSP.
	2. Сбров MeasDataFifo и логики упаковки данных для MeasDataFifo, при нарастующем фронте сигнала запуска измерений от DSP.

S5443_M/S5443.srcs/sources_1/new/ExtDspInterface/DspInterface.v

@@ -116,18 +116,22 @@ module	DspInterface
 	wire	signed	[15:0]	filteredDecimDataI;
 	wire	signed	[15:0]	filteredDecimDataQ;
 	wire	filteredDecimDataVal;
+	
+	reg		startMeasDspReg;
 //================================================================================
 //	ASSIGNMENTS
 //================================================================================
 
-	assign	measDataBus	[(ResultWidth*(ChNum*2-7))-1-:ResultWidth]	=	Adc1T1ImResult_i;
-	assign	measDataBus	[(ResultWidth*(ChNum*2-6))-1-:ResultWidth]	=	Adc1T1ReResult_i;
-	assign	measDataBus	[(ResultWidth*(ChNum*2-5))-1-:ResultWidth]	=	Adc1R1ImResult_i;
-	assign	measDataBus	[(ResultWidth*(ChNum*2-4))-1-:ResultWidth]	=	Adc1R1ReResult_i;
-	assign	measDataBus	[(ResultWidth*(ChNum*2-3))-1-:ResultWidth]	=	Adc2T2ImResult_i;
-	assign	measDataBus	[(ResultWidth*(ChNum*2-2))-1-:ResultWidth]	=	Adc2T2ReResult_i;
-	assign	measDataBus	[(ResultWidth*(ChNum*2-1))-1-:ResultWidth]	=	Adc2R2ImResult_i;
-	assign	measDataBus	[(ResultWidth*(ChNum*2-0))-1-:ResultWidth]	=	Adc2R2ReResult_i;
+	assign	startMeasDspPos		=	(!startMeasDspReg&StartMeasDsp_i);
+	
+	assign	measDataBus	[(ResultWidth*(ChNum*2-7))-1-:ResultWidth]	=	(startMeasDspPos)?32'd0:Adc1T1ImResult_i;
+	assign	measDataBus	[(ResultWidth*(ChNum*2-6))-1-:ResultWidth]	=	(startMeasDspPos)?32'd0:Adc1T1ReResult_i;
+	assign	measDataBus	[(ResultWidth*(ChNum*2-5))-1-:ResultWidth]	=	(startMeasDspPos)?32'd0:Adc1R1ImResult_i;
+	assign	measDataBus	[(ResultWidth*(ChNum*2-4))-1-:ResultWidth]	=	(startMeasDspPos)?32'd0:Adc1R1ReResult_i;
+	assign	measDataBus	[(ResultWidth*(ChNum*2-3))-1-:ResultWidth]	=	(startMeasDspPos)?32'd0:Adc2T2ImResult_i;
+	assign	measDataBus	[(ResultWidth*(ChNum*2-2))-1-:ResultWidth]	=	(startMeasDspPos)?32'd0:Adc2T2ReResult_i;
+	assign	measDataBus	[(ResultWidth*(ChNum*2-1))-1-:ResultWidth]	=	(startMeasDspPos)?32'd0:Adc2R2ImResult_i;
+	assign	measDataBus	[(ResultWidth*(ChNum*2-0))-1-:ResultWidth]	=	(startMeasDspPos)?32'd0:Adc2R2ReResult_i;
 	
 	// assign	measDataBus	[(ResultWidth*(ChNum*2-7))-1-:ResultWidth]	=	32'h4000_0000;	//2 in float
 	// assign	measDataBus	[(ResultWidth*(ChNum*2-6))-1-:ResultWidth]	=	32'h4040_0000;	//3 in float
@@ -160,9 +164,11 @@ wire	oscWindNeg	=	(!OscWind_i&oscWindR);
 
 always	@(posedge	Clk_i)	begin
 	if	(!Rst_i)	begin
-		oscWindR	<=	OscWind_i;
+		oscWindR		<=	OscWind_i;
+		startMeasDspReg	<=	StartMeasDsp_i;
 	end	else	begin
-		oscWindR	<=	0;
+		oscWindR		<=	0;
+		startMeasDspReg	<=	0;
 	end
 end
 
@@ -303,7 +309,7 @@ MeasDataFifoWrapper
 MeasDataFifoInst
 (
 	.Clk_i			(Clk_i), 
-	.Rst_i			(Rst_i),	
+	.Rst_i			(Rst_i|startMeasDspPos),	
 	.PpiBusy_i		(ppiBusy),	
 	.MeasNum_i		(MeasNum_i),	
 	.StartMeasDsp_i	(StartMeasDsp_i),	
@@ -325,7 +331,7 @@ DspPpiOut
 )
 MeasDataPpiOut
 (
-	.Rst_i				(Rst_i),	
+	.Rst_i				(Rst_i|startMeasDspPos),	
 	.Clk_i				(Clk_i),		
 	
 	.MeasDataBus_i		(measDataBusTx),

S5443_M/S5443.srcs/sources_1/new/InternalDsp/InternalDsp.v

@@ -335,8 +335,8 @@ ncoFirstTone
 	.Rst_i		(Rst_i|startMeasDspPos),
 	.Val_i		(1'b1),
 	// .PhaseInc_i	({ifFtwHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],ifFtwLReg}),
-	// .PhaseInc_i	(32'h40000000),
-	.PhaseInc_i	(32'h33333333),
+	.PhaseInc_i	(32'h40000000),
+	// .PhaseInc_i	(32'h33333333),
 	.WindVal_i	(1'b1),
 	.WinType_i	(),
 	.Wind_o		(),
@@ -386,19 +386,19 @@ always 	@(posedge Clk_i) begin
 	end
 end
 	
-blk_mem_gen_0 sinCosMemFirstTone
-(
-	.clka	(Clk_i),    // input wire clka
-	.addra	(memAddrFirstTone),  // input wire [8 : 0] addra
-	.douta	(firstToneSinCosValues)  // output wire [35 : 0] douta
-);
-
-blk_mem_gen_0 sinCosMemSecondTone
-(
-	.clka	(Clk_i),    // input wire clka
-	.addra	(memAddrSecondTone),  // input wire [8 : 0] addra
-	.douta	(secondToneSinCosValues)  // output wire [35 : 0] douta
-);
+// blk_mem_gen_0 sinCosMemFirstTone
+// (
+	// .clka	(Clk_i),    // input wire clka
+	// .addra	(memAddrFirstTone),  // input wire [8 : 0] addra
+	// .douta	(firstToneSinCosValues)  // output wire [35 : 0] douta
+// );
+
+// blk_mem_gen_0 sinCosMemSecondTone
+// (
+	// .clka	(Clk_i),    // input wire clka
+	// .addra	(memAddrSecondTone),  // input wire [8 : 0] addra
+	// .douta	(secondToneSinCosValues)  // output wire [35 : 0] douta
+// );
 
 ComplPrng
 #(

S5443_M/S5443.srcs/sources_1/new/InternalDsp/NcoRstGenV2.v

@@ -0,0 +1,121 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 		Churbanov S.
+// 
+// Create Date:		15:22:20 12/08/2019 
+// Design Name: 
+// Module Name:		Win_parameters
+// Project Name:	Compact_main
+// Target Devices: 
+// Tool versions: 
+// Description: 	
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module NcoRstGenV2
+(
+	input	Clk_i,
+	input	Rst_i,
+	input	[31:0]	NcoPhInc_i,
+	input	StartMeasEvent_i,
+	
+	output	NcoRst_o,
+	output	StartMeasEvent_o
+);
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	reg	[13:0]	startMeasEventReg;
+	reg	[31:0]	ncoPhIncReg;
+	reg	[31:0]	ncoPhIncRegR;
+	
+	wire	ncoPhIncUpdateFlag	=	(ncoPhIncRegR!=ncoPhIncReg);
+	wire	delFlag	=	(startMeasEventReg[13]);
+	
+	reg	[1:0]	currState;
+	
+	reg	rst;
+	reg	startMeasEventR;
+	reg	measEvent;
+//================================================================================
+//  PARAMETERS
+//================================================================================
+	parameter	[1:0]	IDLE	=	2'd0;
+	parameter	[1:0]	RST		=	2'd1;
+	parameter	[1:0]	DEL		=	2'd2;
+//================================================================================
+//  ASSIGNMENTS
+// ================================================================================	
+	assign	NcoRst_o	=	rst;
+	assign	StartMeasEvent_o	=	startMeasEventReg[13];
+	assign	startMeasDspPos		=	(!startMeasEventR&StartMeasEvent_i);
+	
+//================================================================================
+//  CODING
+//================================================================================	
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			ncoPhIncReg		<=	NcoPhInc_i;
+			ncoPhIncRegR	<=	ncoPhIncReg;
+			startMeasEventR	<=	StartMeasEvent_i;
+		end	else	begin
+			ncoPhIncReg		<=	0;
+			ncoPhIncReg		<=	0;
+			startMeasEventR	<=	0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			startMeasEventReg	<=	{startMeasEventReg[12:0],StartMeasEvent_i};
+		end	else	begin
+			startMeasEventReg	<=	0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			case(currState)
+			IDLE	:	begin
+							if (startMeasDspPos)	begin
+								currState	<= RST;
+								rst	<=	1'b1;
+							end	else begin
+								currState	<= IDLE;
+								rst	<=	1'b0;
+							end
+						end
+						
+			RST		:	begin
+							if	(rst	&	StartMeasEvent_i)	begin
+								currState	<= DEL;
+								rst	<=	1'b0;
+							end	else begin
+								currState	<= RST;
+								rst	<=	1'b1;
+							end
+						end
+		
+			DEL		:	begin
+							if	(delFlag)	begin
+								currState  <= IDLE;
+								rst	<=	1'b0;
+							end	else begin
+								currState  <= DEL;
+								rst	<=	1'b0;
+							end
+						end
+			endcase
+		end	else	begin
+			currState	<=	2'd0;
+		end
+	end
+
+endmodule

S5443_M/S5443.srcs/sources_1/new/MeasDataFifo/MeasDataFifoWrapper.v

@@ -54,7 +54,7 @@ module MeasDataFifoWrapper
 //================================================================================		
 
 always	@(posedge	Clk_i)	begin
-	if	(!rstOr)	begin
+	if	(!Rst_i)	begin
 		if	(rdEn)	begin
 			rdCnt	<=	rdCnt+14'd1;
 		end	
@@ -74,7 +74,7 @@ end
 MeasDataFifo	MeasDataFifoInst
 (
 	.clk	(Clk_i),
-	.srst	(Rst_i|startMeasDspPos),
+	.srst	(Rst_i),
 	.din	(MeasDataBus_i),
 	.wr_en	(wrEn),
 	.rd_en	(rdEn),
@@ -87,7 +87,7 @@ MeasDataFifo	MeasDataFifoInst
 FifoController	FifoControllerInst
 (
 	.Clk_i				(Clk_i), 
-	.Rst_i				(Rst_i|startMeasDspPos),	
+	.Rst_i				(Rst_i),	
 	.DspReadyForRx_i	(DspReadyForRx_i),	
 	.PpiBusy_i			(PpiBusy_i),	
 	.MeasNum_i			(MeasNum_i),	

S5443_M/S5443.srcs/sources_1/new/S5243Top.v

@@ -737,7 +737,18 @@ always	@(posedge	gclk)	begin
 	end
 end
 
-NcoRstGen	NcoRstGenInst
+// NcoRstGen	NcoRstGenInst
+// (
+	// .Clk_i				(gclk),
+	// .Rst_i				(initRst),
+	// .NcoPhInc_i			({ifFtwH[0+:PhIncWidth-CmdDataRegWith],ifFtwL}),
+	// .StartMeasEvent_i	(startMeasEvent),
+	
+	// .NcoRst_o			(ncoRst),
+	// .StartMeasEvent_o	(intTrig1)	
+// );
+
+NcoRstGenV2	NcoRstGenInst
 (
 	.Clk_i				(gclk),
 	.Rst_i				(initRst),

S5443_M/S5443.srcs/sources_1/new/S5443TopSimpleMeasTb.v

@@ -340,9 +340,10 @@ ncoInst
 );
 
 
-S5443Top MasterFpga 
+S5243Top MasterFpga 
 (
-	.Clk_i				(Clk50),
+	.ClkP_i				(Clk50),
+	.ClkN_i				(~Clk50),
 	.Led_o				(),
 //------------------------------------------	
     .Adc1FclkP_i		(),		
@@ -371,11 +372,11 @@ S5443Top MasterFpga
     .Adc2DataDb1P_i		(1'b1),
     .Adc2DataDb1N_i		(1'b0),
 //------------------------------------------
-	.AdcInitMosi_o		(),
-	.AdcInitClk_o		(),			
+	// .AdcInitMosi_o		(),
+	// .AdcInitClk_o		(),			
 	.Adc1InitCs_o		(),
 	.Adc2InitCs_o		(),
-	.AdcInitRst_o		(),
+	// .AdcInitRst_o		(),
 //------------------------------------------	
 	
 	.Mosi_i				(mosi_i),
@@ -388,30 +389,32 @@ S5443Top MasterFpga
 	
 	//fpga-dsp signals
 	.StartMeas_i		(startCalcCmdReg),
-	.StartMeas_o		(startMeasS),
+	// .StartMeasEvent_o	(startMeasS),
 	.EndMeas_o			(endMeas),
 	.TimersClk_o		(),
 	
 	.Trig6to1_io		(),	
 	.Trig6to1Dir_o		(),	
 	
-	.DspTrigOut_i		(dspTrigOut),				//Trig from DSP
+	.DspTrigOut_i		(Clk41),				//Trig from DSP
 	.DspTrigIn_o		(),				//Trig To DSP
 	
-	.OverloadS_i		(1'b0),
+	// .OverloadS_i		(1'b0),
 	.Overload_o			(),
 	
 	.PortSel_o			(),
-	.PortSelDir_o		(),
+	// .PortSelDir_o		(),
 	
 	//mod out line
 	
 	.Mod_o				(),	
 	
 	//gain lines
-	.SensEnM_io			(sensEn),
-	.AmpEn_o			(),	//	0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
-	.AdcData_i			(sin_value[17-:14])
+	.DspReadyForRx_i		(1'b0),
+	// .DspReadyForRxToFpgaS_o	(),
+	.AmpEn_o				(),	//	0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
+	.AdcData_i				(sin_value[17-:14])
+	// .AdcData_i			(Data_i)
 );
 
 parameter	IDLE	=	2'h0;