Добавлен сброс NCO перед каждым измерением.

S5443_M/S5443.ip_user_files/ip/MeasDataFifo/MeasDataFifo_stub.v

@@ -1,27 +0,0 @@
-// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
-// Date        : Tue Aug 29 17:27:14 2023
-// Host        : DESKTOP-RMARCDV running 64-bit major release  (build 9200)
-// Command     : write_verilog -force -mode synth_stub
-//               c:/Users/Stepan/Desktop/4portCompact/S5443Current/S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_stub.v
-// Design      : MeasDataFifo
-// Purpose     : Stub declaration of top-level module interface
-// Device      : xc7s25csga324-2
-// --------------------------------------------------------------------------------
-
-// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
-// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
-// Please paste the declaration into a Verilog source file or add the file as an additional source.
-(* x_core_info = "fifo_generator_v13_2_5,Vivado 2020.2" *)
-module MeasDataFifo(clk, srst, din, wr_en, rd_en, dout, full, empty)
-/* synthesis syn_black_box black_box_pad_pin="clk,srst,din[255:0],wr_en,rd_en,dout[255:0],full,empty" */;
-  input clk;
-  input srst;
-  input [255:0]din;
-  input wr_en;
-  input rd_en;
-  output [255:0]dout;
-  output full;
-  output empty;
-endmodule

S5443_M/S5443.ip_user_files/ip/MeasDataFifo/MeasDataFifo_stub.vhdl

@@ -1,37 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity MeasDataFifo is
-  Port ( 
-    clk : in STD_LOGIC;
-    srst : in STD_LOGIC;
-    din : in STD_LOGIC_VECTOR ( 255 downto 0 );
-    wr_en : in STD_LOGIC;
-    rd_en : in STD_LOGIC;
-    dout : out STD_LOGIC_VECTOR ( 255 downto 0 );
-    full : out STD_LOGIC;
-    empty : out STD_LOGIC
-  );
-
-end MeasDataFifo;
-
-architecture stub of MeasDataFifo is
-attribute syn_black_box : boolean;
-attribute black_box_pad_pin : string;
-attribute syn_black_box of stub : architecture is true;
-attribute black_box_pad_pin of stub : architecture is "clk,srst,din[255:0],wr_en,rd_en,dout[255:0],full,empty";
-attribute x_core_info : string;
-attribute x_core_info of stub : architecture is "fifo_generator_v13_2_5,Vivado 2020.2";
-begin
-end;

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/README.txt

@@ -1,83 +0,0 @@
-################################################################################
-# Vivado (TM) v2020.2 (64-bit)
-#
-# README.txt: Please read the sections below to understand the steps required
-#             to simulate the design for a simulator, the directory structure
-#             and the generated exported files.
-#
-################################################################################
-
-1. Simulate Design
-
-To simulate design, cd to the simulator directory and execute the script.
-
-For example:-
-
-% cd questa
-% ./top.sh
-
-The export simulation flow requires the Xilinx pre-compiled simulation library
-components for the target simulator. These components are referred using the
-'-lib_map_path' switch. If this switch is specified, then the export simulation
-will automatically set this library path in the generated script and update,
-copy the simulator setup file(s) in the exported directory.
-
-If '-lib_map_path' is not specified, then the pre-compiled simulation library
-information will not be included in the exported scripts and that may cause
-simulation errors when running this script. Alternatively, you can provide the
-library information using this switch while executing the generated script.
-
-For example:-
-
-% ./top.sh -lib_map_path /design/questa/clibs
-
-Please refer to the generated script header 'Prerequisite' section for more details.
-
-2. Directory Structure
-
-By default, if the -directory switch is not specified, export_simulation will
-create the following directory structure:-
-
-<current_working_directory>/export_sim/<simulator>
-
-For example, if the current working directory is /tmp/test, export_simulation
-will create the following directory path:-
-
-/tmp/test/export_sim/questa
-
-If -directory switch is specified, export_simulation will create a simulator
-sub-directory under the specified directory path.
-
-For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
-command will create the following directory:-
-
-/tmp/test/my_test_area/func_sim/questa
-
-By default, if -simulator is not specified, export_simulation will create a
-simulator sub-directory for each simulator and export the files for each simulator
-in this sub-directory respectively.
-
-IMPORTANT: Please note that the simulation library path must be specified manually
-in the generated script for the respective simulator. Please refer to the generated
-script header 'Prerequisite' section for more details.
-
-3. Exported script and files
-
-Export simulation will create the driver shell script, setup files and copy the
-design sources in the output directory path.
-
-By default, when the -script_name switch is not specified, export_simulation will
-create the following script name:-
-
-<simulation_top>.sh  (Unix)
-When exporting the files for an IP using the -of_objects switch, export_simulation
-will create the following script name:-
-
-<ip-name>.sh  (Unix)
-Export simulation will create the setup files for the target simulator specified
-with the -simulator switch.
-
-For example, if the target simulator is "ies", export_simulation will create the
-'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
-file.
-

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/activehdl/MeasDataFifo.sh

@@ -1,153 +0,0 @@
-#!/bin/bash -f
-#*********************************************************************************************************
-# Vivado (TM) v2020.2 (64-bit)
-#
-# Filename    : MeasDataFifo.sh
-# Simulator   : Aldec Active-HDL Simulator
-# Description : Simulation script for compiling, elaborating and verifying the project source files.
-#               The script will automatically create the design libraries sub-directories in the run
-#               directory, add the library logical mappings in the simulator setup file, create default
-#               'do/prj' file, execute compilation, elaboration and simulation steps.
-#
-# Generated by Vivado on Tue Aug 29 17:27:19 +0700 2023
-# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
-#
-# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
-#
-# usage: MeasDataFifo.sh [-help]
-# usage: MeasDataFifo.sh [-lib_map_path]
-# usage: MeasDataFifo.sh [-noclean_files]
-# usage: MeasDataFifo.sh [-reset_run]
-#
-# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
-# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
-# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
-# that points to these libraries and rerun export_simulation. For more information about this switch please
-# type 'export_simulation -help' in the Tcl shell.
-#
-# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
-# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
-# executing this script. Please type 'MeasDataFifo.sh -help' for more information.
-#
-# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
-#
-#*********************************************************************************************************
-
-
-# Script info
-echo -e "MeasDataFifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
-
-# Main steps
-run()
-{
-  check_args $# $1
-  setup $1 $2
-  compile
-  simulate
-}
-
-# RUN_STEP: <compile>
-compile()
-{
-  # Compile design files
-  source compile.do 2>&1 | tee -a compile.log
-
-}
-
-# RUN_STEP: <simulate>
-simulate()
-{
-  runvsimsa -l simulate.log -do "do {simulate.do}"
-}
-
-# STEP: setup
-setup()
-{
-  case $1 in
-    "-lib_map_path" )
-      if [[ ($2 == "") ]]; then
-        echo -e "ERROR: Simulation library directory path not specified (type \"./MeasDataFifo.sh -help\" for more information)\n"
-        exit 1
-      fi
-     map_setup_file $2
-    ;;
-    "-reset_run" )
-      reset_run
-      echo -e "INFO: Simulation run files deleted.\n"
-      exit 0
-    ;;
-    "-noclean_files" )
-      # do not remove previous data
-    ;;
-    * )
-     map_setup_file $2
-  esac
-
-  # Add any setup/initialization commands here:-
-
-  # <user specific commands>
-
-}
-
-# Map library.cfg file
-map_setup_file()
-{
-  file="library.cfg"
-  if [[ ($1 != "") ]]; then
-    lib_map_path="$1"
-  else
-    lib_map_path="C:/Users/Stepan/Desktop/4portCompact/S5443Current/S5443_M/S5443.cache/compile_simlib/activehdl"
-  fi
-  if [[ ($lib_map_path != "") ]]; then
-    src_file="$lib_map_path/$file"
-    if [[ -e $src_file ]]; then
-      vmap -link $lib_map_path
-    fi
-  fi
-}
-
-# Delete generated data from the previous run
-reset_run()
-{
-  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
-  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
-    file="${files_to_remove[i]}"
-    if [[ -e $file ]]; then
-      rm -rf $file
-    fi
-  done
-}
-
-# Check command line arguments
-check_args()
-{
-  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
-    echo -e "ERROR: Unknown option specified '$2' (type \"./MeasDataFifo.sh -help\" for more information)\n"
-    exit 1
-  fi
-
-  if [[ ($2 == "-help" || $2 == "-h") ]]; then
-    usage
-  fi
-}
-
-# Script usage
-usage()
-{
-  msg="Usage: MeasDataFifo.sh [-help]\n\
-Usage: MeasDataFifo.sh [-lib_map_path]\n\
-Usage: MeasDataFifo.sh [-reset_run]\n\
-Usage: MeasDataFifo.sh [-noclean_files]\n\n\
-[-help] -- Print help information for this script\n\n\
-[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
-using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
-[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
-from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
--noclean_files switch.\n\n\
-[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
-  echo -e $msg
-  exit 1
-}
-
-# Launch script
-run $1 $2

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/activehdl/README.txt

@@ -1,49 +0,0 @@
-################################################################################
-# Vivado (TM) v2020.2 (64-bit)
-#
-# README.txt: Please read the sections below to understand the steps required to
-#             run the exported script and information about the source files.
-#
-# Generated by export_simulation on Tue Aug 29 17:27:19 +0700 2023
-#
-################################################################################
-
-1. How to run the generated simulation script:-
-
-From the shell prompt in the current directory, issue the following command:-
-
-./MeasDataFifo.sh
-
-This command will launch the 'compile', 'elaborate' and 'simulate' functions
-implemented in the script file for the 3-step flow. These functions are called
-from the main 'run' function in the script file.
-
-The 'run' function first executes the 'setup' function, the purpose of which is to
-create simulator specific setup files, create design library mappings and library
-directories and copy 'glbl.v' from the Vivado software install location into the
-current directory.
-
-The 'setup' function is also used for removing the simulator generated data in
-order to reset the current directory to the original state when export_simulation
-was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './MeasDataFifo.sh' script.
-
-./MeasDataFifo.sh -reset_run
-
-To keep the generated data from the previous run but regenerate the setup files and
-library directories, use the '-noclean_files' switch.
-
-./MeasDataFifo.sh -noclean_files
-
-For more information on the script, please type './MeasDataFifo.sh -help'.
-
-2. Additional design information files:-
-
-export_simulation generates following additional file that can be used for fetching
-the design files information or for integrating with external custom scripts.
-
-Name   : file_info.txt
-Purpose: This file contains detail design file information based on the compile order
-         when export_simulation was executed from Vivado. The file contains information
-         about the file type, name, whether it is part of the IP, associated library
-         and the file path information.

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/activehdl/compile.do

@@ -1,22 +0,0 @@
-vlib work
-vlib activehdl
-
-vlib activehdl/xpm
-vlib activehdl/xil_defaultlib
-
-vmap xpm activehdl/xpm
-vmap xil_defaultlib activehdl/xil_defaultlib
-
-vlog -work xpm  -sv2k12 \
-"C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
-"C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
-
-vcom -work xpm -93 \
-"C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
-
-vlog -work xil_defaultlib  -v2k5 \
-"../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v" \
-
-vlog -work xil_defaultlib \
-"glbl.v"
-

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/activehdl/file_info.txt

@@ -1,5 +0,0 @@
-xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
-xpm_memory.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
-MeasDataFifo_sim_netlist.v,verilog,xil_defaultlib,../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v,
-glbl.v,Verilog,xil_defaultlib,glbl.v

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/activehdl/glbl.v

@@ -1,84 +0,0 @@
-// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
-`ifndef GLBL
-`define GLBL
-`timescale  1 ps / 1 ps
-
-module glbl ();
-
-    parameter ROC_WIDTH = 100000;
-    parameter TOC_WIDTH = 0;
-    parameter GRES_WIDTH = 10000;
-    parameter GRES_START = 10000;
-
-//--------   STARTUP Globals --------------
-    wire GSR;
-    wire GTS;
-    wire GWE;
-    wire PRLD;
-    wire GRESTORE;
-    tri1 p_up_tmp;
-    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
-    wire PROGB_GLBL;
-    wire CCLKO_GLBL;
-    wire FCSBO_GLBL;
-    wire [3:0] DO_GLBL;
-    wire [3:0] DI_GLBL;
-   
-    reg GSR_int;
-    reg GTS_int;
-    reg PRLD_int;
-    reg GRESTORE_int;
-
-//--------   JTAG Globals --------------
-    wire JTAG_TDO_GLBL;
-    wire JTAG_TCK_GLBL;
-    wire JTAG_TDI_GLBL;
-    wire JTAG_TMS_GLBL;
-    wire JTAG_TRST_GLBL;
-
-    reg JTAG_CAPTURE_GLBL;
-    reg JTAG_RESET_GLBL;
-    reg JTAG_SHIFT_GLBL;
-    reg JTAG_UPDATE_GLBL;
-    reg JTAG_RUNTEST_GLBL;
-
-    reg JTAG_SEL1_GLBL = 0;
-    reg JTAG_SEL2_GLBL = 0 ;
-    reg JTAG_SEL3_GLBL = 0;
-    reg JTAG_SEL4_GLBL = 0;
-
-    reg JTAG_USER_TDO1_GLBL = 1'bz;
-    reg JTAG_USER_TDO2_GLBL = 1'bz;
-    reg JTAG_USER_TDO3_GLBL = 1'bz;
-    reg JTAG_USER_TDO4_GLBL = 1'bz;
-
-    assign (strong1, weak0) GSR = GSR_int;
-    assign (strong1, weak0) GTS = GTS_int;
-    assign (weak1, weak0) PRLD = PRLD_int;
-    assign (strong1, weak0) GRESTORE = GRESTORE_int;
-
-    initial begin
-	GSR_int = 1'b1;
-	PRLD_int = 1'b1;
-	#(ROC_WIDTH)
-	GSR_int = 1'b0;
-	PRLD_int = 1'b0;
-    end
-
-    initial begin
-	GTS_int = 1'b1;
-	#(TOC_WIDTH)
-	GTS_int = 1'b0;
-    end
-
-    initial begin 
-	GRESTORE_int = 1'b0;
-	#(GRES_START);
-	GRESTORE_int = 1'b1;
-	#(GRES_WIDTH);
-	GRESTORE_int = 1'b0;
-    end
-
-endmodule
-`endif

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/activehdl/simulate.do

@@ -1,17 +0,0 @@
-onbreak {quit -force}
-onerror {quit -force}
-
-asim +access +r +m+MeasDataFifo -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.MeasDataFifo xil_defaultlib.glbl
-
-do {wave.do}
-
-view wave
-view structure
-
-do {MeasDataFifo.udo}
-
-run -all
-
-endsim
-
-quit -force

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/activehdl/wave.do

@@ -1,2 +0,0 @@
-add wave *
-add wave /glbl/GSR

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/ies/MeasDataFifo.sh

@@ -1,175 +0,0 @@
-#!/bin/bash -f
-#*********************************************************************************************************
-# Vivado (TM) v2020.2 (64-bit)
-#
-# Filename    : MeasDataFifo.sh
-# Simulator   : Cadence Incisive Enterprise Simulator
-# Description : Simulation script for compiling, elaborating and verifying the project source files.
-#               The script will automatically create the design libraries sub-directories in the run
-#               directory, add the library logical mappings in the simulator setup file, create default
-#               'do/prj' file, execute compilation, elaboration and simulation steps.
-#
-# Generated by Vivado on Tue Aug 29 17:27:19 +0700 2023
-# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
-#
-# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
-#
-# usage: MeasDataFifo.sh [-help]
-# usage: MeasDataFifo.sh [-lib_map_path]
-# usage: MeasDataFifo.sh [-noclean_files]
-# usage: MeasDataFifo.sh [-reset_run]
-#
-# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
-# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
-# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
-# that points to these libraries and rerun export_simulation. For more information about this switch please
-# type 'export_simulation -help' in the Tcl shell.
-#
-# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
-# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
-# executing this script. Please type 'MeasDataFifo.sh -help' for more information.
-#
-# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
-#
-#*********************************************************************************************************
-
-# Directory path for design sources and include directories (if any) wrt this path
-ref_dir="."
-
-# Override directory with 'export_sim_ref_dir' env path value if set in the shell
-if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
-  ref_dir="$export_sim_ref_dir"
-fi
-
-# Set the compiled library directory
-ref_lib_dir="."
-
-# Command line options
-irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
-
-# Design libraries
-design_libs=(xpm xil_defaultlib)
-
-# Simulation root library directory
-sim_lib_dir="ies_lib"
-
-# Script info
-echo -e "MeasDataFifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
-
-# Main steps
-run()
-{
-  check_args $# $1
-  setup $1 $2
-  execute
-}
-
-# RUN_STEP: <execute>
-execute()
-{
-  irun $irun_opts \
-       -reflib "$ref_lib_dir/unisim:unisim" \
-       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
-       -reflib "$ref_lib_dir/secureip:secureip" \
-       -reflib "$ref_lib_dir/unimacro:unimacro" \
-       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
-       -top xil_defaultlib.MeasDataFifo \
-       -f run.f \
-       -top glbl \
-       glbl.v
-}
-
-# STEP: setup
-setup()
-{
-  case $1 in
-    "-lib_map_path" )
-      if [[ ($2 == "") ]]; then
-        echo -e "ERROR: Simulation library directory path not specified (type \"./MeasDataFifo.sh -help\" for more information)\n"
-        exit 1
-      else
-        ref_lib_dir=$2
-      fi
-    ;;
-    "-reset_run" )
-      reset_run
-      echo -e "INFO: Simulation run files deleted.\n"
-      exit 0
-    ;;
-    "-noclean_files" )
-      # do not remove previous data
-    ;;
-    * )
-  esac
-
-  create_lib_dir
-
-  # Add any setup/initialization commands here:-
-
-  # <user specific commands>
-
-}
-
-# Create design library directory paths
-create_lib_dir()
-{
-  if [[ -e $sim_lib_dir ]]; then
-    rm -rf $sim_lib_dir
-  fi
-
-  for (( i=0; i<${#design_libs[*]}; i++ )); do
-    lib="${design_libs[i]}"
-    lib_dir="$sim_lib_dir/$lib"
-    if [[ ! -e $lib_dir ]]; then
-      mkdir -p $lib_dir
-    fi
-  done
-}
-
-# Delete generated data from the previous run
-reset_run()
-{
-  files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
-  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
-    file="${files_to_remove[i]}"
-    if [[ -e $file ]]; then
-      rm -rf $file
-    fi
-  done
-
-  create_lib_dir
-}
-
-# Check command line arguments
-check_args()
-{
-  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
-    echo -e "ERROR: Unknown option specified '$2' (type \"./MeasDataFifo.sh -help\" for more information)\n"
-    exit 1
-  fi
-
-  if [[ ($2 == "-help" || $2 == "-h") ]]; then
-    usage
-  fi
-}
-
-# Script usage
-usage()
-{
-  msg="Usage: MeasDataFifo.sh [-help]\n\
-Usage: MeasDataFifo.sh [-lib_map_path]\n\
-Usage: MeasDataFifo.sh [-reset_run]\n\
-Usage: MeasDataFifo.sh [-noclean_files]\n\n\
-[-help] -- Print help information for this script\n\n\
-[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
-using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
-[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
-from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
--noclean_files switch.\n\n\
-[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
-  echo -e $msg
-  exit 1
-}
-
-# Launch script
-run $1 $2

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/ies/README.txt

@@ -1,48 +0,0 @@
-################################################################################
-# Vivado (TM) v2020.2 (64-bit)
-#
-# README.txt: Please read the sections below to understand the steps required to
-#             run the exported script and information about the source files.
-#
-# Generated by export_simulation on Tue Aug 29 17:27:19 +0700 2023
-#
-################################################################################
-
-1. How to run the generated simulation script:-
-
-From the shell prompt in the current directory, issue the following command:-
-
-./MeasDataFifo.sh
-
-This command will launch the 'execute' function for the single-step flow. This
-function is called from the main 'run' function in the script file.
-
-The 'run' function first executes the 'setup' function, the purpose of which is to
-create simulator specific setup files, create design library mappings and library
-directories and copy 'glbl.v' from the Vivado software install location into the
-current directory.
-
-The 'setup' function is also used for removing the simulator generated data in
-order to reset the current directory to the original state when export_simulation
-was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './MeasDataFifo.sh' script.
-
-./MeasDataFifo.sh -reset_run
-
-To keep the generated data from the previous run but regenerate the setup files and
-library directories, use the '-noclean_files' switch.
-
-./MeasDataFifo.sh -noclean_files
-
-For more information on the script, please type './MeasDataFifo.sh -help'.
-
-2. Additional design information files:-
-
-export_simulation generates following additional file that can be used for fetching
-the design files information or for integrating with external custom scripts.
-
-Name   : file_info.txt
-Purpose: This file contains detail design file information based on the compile order
-         when export_simulation was executed from Vivado. The file contains information
-         about the file type, name, whether it is part of the IP, associated library
-         and the file path information.

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/ies/file_info.txt

@@ -1,5 +0,0 @@
-xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
-xpm_memory.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
-MeasDataFifo_sim_netlist.v,verilog,xil_defaultlib,../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v,
-glbl.v,Verilog,xil_defaultlib,glbl.v

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/ies/glbl.v

@@ -1,84 +0,0 @@
-// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
-`ifndef GLBL
-`define GLBL
-`timescale  1 ps / 1 ps
-
-module glbl ();
-
-    parameter ROC_WIDTH = 100000;
-    parameter TOC_WIDTH = 0;
-    parameter GRES_WIDTH = 10000;
-    parameter GRES_START = 10000;
-
-//--------   STARTUP Globals --------------
-    wire GSR;
-    wire GTS;
-    wire GWE;
-    wire PRLD;
-    wire GRESTORE;
-    tri1 p_up_tmp;
-    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
-    wire PROGB_GLBL;
-    wire CCLKO_GLBL;
-    wire FCSBO_GLBL;
-    wire [3:0] DO_GLBL;
-    wire [3:0] DI_GLBL;
-   
-    reg GSR_int;
-    reg GTS_int;
-    reg PRLD_int;
-    reg GRESTORE_int;
-
-//--------   JTAG Globals --------------
-    wire JTAG_TDO_GLBL;
-    wire JTAG_TCK_GLBL;
-    wire JTAG_TDI_GLBL;
-    wire JTAG_TMS_GLBL;
-    wire JTAG_TRST_GLBL;
-
-    reg JTAG_CAPTURE_GLBL;
-    reg JTAG_RESET_GLBL;
-    reg JTAG_SHIFT_GLBL;
-    reg JTAG_UPDATE_GLBL;
-    reg JTAG_RUNTEST_GLBL;
-
-    reg JTAG_SEL1_GLBL = 0;
-    reg JTAG_SEL2_GLBL = 0 ;
-    reg JTAG_SEL3_GLBL = 0;
-    reg JTAG_SEL4_GLBL = 0;
-
-    reg JTAG_USER_TDO1_GLBL = 1'bz;
-    reg JTAG_USER_TDO2_GLBL = 1'bz;
-    reg JTAG_USER_TDO3_GLBL = 1'bz;
-    reg JTAG_USER_TDO4_GLBL = 1'bz;
-
-    assign (strong1, weak0) GSR = GSR_int;
-    assign (strong1, weak0) GTS = GTS_int;
-    assign (weak1, weak0) PRLD = PRLD_int;
-    assign (strong1, weak0) GRESTORE = GRESTORE_int;
-
-    initial begin
-	GSR_int = 1'b1;
-	PRLD_int = 1'b1;
-	#(ROC_WIDTH)
-	GSR_int = 1'b0;
-	PRLD_int = 1'b0;
-    end
-
-    initial begin
-	GTS_int = 1'b1;
-	#(TOC_WIDTH)
-	GTS_int = 1'b0;
-    end
-
-    initial begin 
-	GRESTORE_int = 1'b0;
-	#(GRES_START);
-	GRESTORE_int = 1'b1;
-	#(GRES_WIDTH);
-	GRESTORE_int = 1'b0;
-    end
-
-endmodule
-`endif

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/ies/run.f

@@ -1,14 +0,0 @@
--makelib ies_lib/xpm -sv \
-  "C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
-  "C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
--endlib
--makelib ies_lib/xpm \
-  "C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
--endlib
--makelib ies_lib/xil_defaultlib \
-  "../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v" \
--endlib
--makelib ies_lib/xil_defaultlib \
-  glbl.v
--endlib
-

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/modelsim/MeasDataFifo.sh

@@ -1,167 +0,0 @@
-#!/bin/bash -f
-#*********************************************************************************************************
-# Vivado (TM) v2020.2 (64-bit)
-#
-# Filename    : MeasDataFifo.sh
-# Simulator   : Mentor Graphics ModelSim Simulator
-# Description : Simulation script for compiling, elaborating and verifying the project source files.
-#               The script will automatically create the design libraries sub-directories in the run
-#               directory, add the library logical mappings in the simulator setup file, create default
-#               'do/prj' file, execute compilation, elaboration and simulation steps.
-#
-# Generated by Vivado on Tue Aug 29 17:27:19 +0700 2023
-# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
-#
-# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
-#
-# usage: MeasDataFifo.sh [-help]
-# usage: MeasDataFifo.sh [-lib_map_path]
-# usage: MeasDataFifo.sh [-noclean_files]
-# usage: MeasDataFifo.sh [-reset_run]
-#
-# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
-# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
-# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
-# that points to these libraries and rerun export_simulation. For more information about this switch please
-# type 'export_simulation -help' in the Tcl shell.
-#
-# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
-# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
-# executing this script. Please type 'MeasDataFifo.sh -help' for more information.
-#
-# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
-#
-#*********************************************************************************************************
-
-
-# Script info
-echo -e "MeasDataFifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
-
-# Main steps
-run()
-{
-  check_args $# $1
-  setup $1 $2
-  compile
-  simulate
-}
-
-# RUN_STEP: <compile>
-compile()
-{
-  # Compile design files
-  source compile.do 2>&1 | tee -a compile.log
-
-}
-
-# RUN_STEP: <simulate>
-simulate()
-{
-  vsim  -c -do "do {simulate.do}" -l simulate.log
-}
-
-# STEP: setup
-setup()
-{
-  case $1 in
-    "-lib_map_path" )
-      if [[ ($2 == "") ]]; then
-        echo -e "ERROR: Simulation library directory path not specified (type \"./MeasDataFifo.sh -help\" for more information)\n"
-        exit 1
-      fi
-     copy_setup_file $2
-    ;;
-    "-reset_run" )
-      reset_run
-      echo -e "INFO: Simulation run files deleted.\n"
-      exit 0
-    ;;
-    "-noclean_files" )
-      # do not remove previous data
-    ;;
-    * )
-     copy_setup_file $2
-  esac
-
-  create_lib_dir
-
-  # Add any setup/initialization commands here:-
-
-  # <user specific commands>
-
-}
-
-# Copy modelsim.ini file
-copy_setup_file()
-{
-  file="modelsim.ini"
-  if [[ ($1 != "") ]]; then
-    lib_map_path="$1"
-  else
-    lib_map_path="C:/Users/Stepan/Desktop/4portCompact/S5443Current/S5443_M/S5443.cache/compile_simlib/modelsim"
-  fi
-  if [[ ($lib_map_path != "") ]]; then
-    src_file="$lib_map_path/$file"
-    cp $src_file .
-  fi
-}
-
-# Create design library directory
-create_lib_dir()
-{
-  lib_dir="modelsim_lib"
-  if [[ -e $lib_dir ]]; then
-    rm -rf $lib_dir
-  fi
-
-  mkdir $lib_dir
-
-}
-
-# Delete generated data from the previous run
-reset_run()
-{
-  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
-  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
-    file="${files_to_remove[i]}"
-    if [[ -e $file ]]; then
-      rm -rf $file
-    fi
-  done
-
-  create_lib_dir
-}
-
-# Check command line arguments
-check_args()
-{
-  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
-    echo -e "ERROR: Unknown option specified '$2' (type \"./MeasDataFifo.sh -help\" for more information)\n"
-    exit 1
-  fi
-
-  if [[ ($2 == "-help" || $2 == "-h") ]]; then
-    usage
-  fi
-}
-
-# Script usage
-usage()
-{
-  msg="Usage: MeasDataFifo.sh [-help]\n\
-Usage: MeasDataFifo.sh [-lib_map_path]\n\
-Usage: MeasDataFifo.sh [-reset_run]\n\
-Usage: MeasDataFifo.sh [-noclean_files]\n\n\
-[-help] -- Print help information for this script\n\n\
-[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
-using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
-[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
-from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
--noclean_files switch.\n\n\
-[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
-  echo -e $msg
-  exit 1
-}
-
-# Launch script
-run $1 $2

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/modelsim/README.txt

@@ -1,49 +0,0 @@
-################################################################################
-# Vivado (TM) v2020.2 (64-bit)
-#
-# README.txt: Please read the sections below to understand the steps required to
-#             run the exported script and information about the source files.
-#
-# Generated by export_simulation on Tue Aug 29 17:27:19 +0700 2023
-#
-################################################################################
-
-1. How to run the generated simulation script:-
-
-From the shell prompt in the current directory, issue the following command:-
-
-./MeasDataFifo.sh
-
-This command will launch the 'compile', 'elaborate' and 'simulate' functions
-implemented in the script file for the 3-step flow. These functions are called
-from the main 'run' function in the script file.
-
-The 'run' function first executes the 'setup' function, the purpose of which is to
-create simulator specific setup files, create design library mappings and library
-directories and copy 'glbl.v' from the Vivado software install location into the
-current directory.
-
-The 'setup' function is also used for removing the simulator generated data in
-order to reset the current directory to the original state when export_simulation
-was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './MeasDataFifo.sh' script.
-
-./MeasDataFifo.sh -reset_run
-
-To keep the generated data from the previous run but regenerate the setup files and
-library directories, use the '-noclean_files' switch.
-
-./MeasDataFifo.sh -noclean_files
-
-For more information on the script, please type './MeasDataFifo.sh -help'.
-
-2. Additional design information files:-
-
-export_simulation generates following additional file that can be used for fetching
-the design files information or for integrating with external custom scripts.
-
-Name   : file_info.txt
-Purpose: This file contains detail design file information based on the compile order
-         when export_simulation was executed from Vivado. The file contains information
-         about the file type, name, whether it is part of the IP, associated library
-         and the file path information.

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/modelsim/compile.do

@@ -1,14 +0,0 @@
-vlib modelsim_lib/work
-vlib modelsim_lib/msim
-
-vlib modelsim_lib/msim/xil_defaultlib
-
-vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
-
-vlog -work xil_defaultlib  -incr \
-"../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v" \
-
-
-vlog -work xil_defaultlib \
-"glbl.v"
-

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/modelsim/file_info.txt

@@ -1,2 +0,0 @@
-MeasDataFifo_sim_netlist.v,verilog,xil_defaultlib,../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v,
-glbl.v,Verilog,xil_defaultlib,glbl.v

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/modelsim/glbl.v

@@ -1,84 +0,0 @@
-// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
-`ifndef GLBL
-`define GLBL
-`timescale  1 ps / 1 ps
-
-module glbl ();
-
-    parameter ROC_WIDTH = 100000;
-    parameter TOC_WIDTH = 0;
-    parameter GRES_WIDTH = 10000;
-    parameter GRES_START = 10000;
-
-//--------   STARTUP Globals --------------
-    wire GSR;
-    wire GTS;
-    wire GWE;
-    wire PRLD;
-    wire GRESTORE;
-    tri1 p_up_tmp;
-    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
-    wire PROGB_GLBL;
-    wire CCLKO_GLBL;
-    wire FCSBO_GLBL;
-    wire [3:0] DO_GLBL;
-    wire [3:0] DI_GLBL;
-   
-    reg GSR_int;
-    reg GTS_int;
-    reg PRLD_int;
-    reg GRESTORE_int;
-
-//--------   JTAG Globals --------------
-    wire JTAG_TDO_GLBL;
-    wire JTAG_TCK_GLBL;
-    wire JTAG_TDI_GLBL;
-    wire JTAG_TMS_GLBL;
-    wire JTAG_TRST_GLBL;
-
-    reg JTAG_CAPTURE_GLBL;
-    reg JTAG_RESET_GLBL;
-    reg JTAG_SHIFT_GLBL;
-    reg JTAG_UPDATE_GLBL;
-    reg JTAG_RUNTEST_GLBL;
-
-    reg JTAG_SEL1_GLBL = 0;
-    reg JTAG_SEL2_GLBL = 0 ;
-    reg JTAG_SEL3_GLBL = 0;
-    reg JTAG_SEL4_GLBL = 0;
-
-    reg JTAG_USER_TDO1_GLBL = 1'bz;
-    reg JTAG_USER_TDO2_GLBL = 1'bz;
-    reg JTAG_USER_TDO3_GLBL = 1'bz;
-    reg JTAG_USER_TDO4_GLBL = 1'bz;
-
-    assign (strong1, weak0) GSR = GSR_int;
-    assign (strong1, weak0) GTS = GTS_int;
-    assign (weak1, weak0) PRLD = PRLD_int;
-    assign (strong1, weak0) GRESTORE = GRESTORE_int;
-
-    initial begin
-	GSR_int = 1'b1;
-	PRLD_int = 1'b1;
-	#(ROC_WIDTH)
-	GSR_int = 1'b0;
-	PRLD_int = 1'b0;
-    end
-
-    initial begin
-	GTS_int = 1'b1;
-	#(TOC_WIDTH)
-	GTS_int = 1'b0;
-    end
-
-    initial begin 
-	GRESTORE_int = 1'b0;
-	#(GRES_START);
-	GRESTORE_int = 1'b1;
-	#(GRES_WIDTH);
-	GRESTORE_int = 1'b0;
-    end
-
-endmodule
-`endif

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/modelsim/simulate.do

@@ -1,16 +0,0 @@
-onbreak {quit -f}
-onerror {quit -f}
-
-vsim -voptargs="+acc" -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.MeasDataFifo xil_defaultlib.glbl
-
-do {wave.do}
-
-view wave
-view structure
-view signals
-
-do {MeasDataFifo.udo}
-
-run -all
-
-quit -force

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/modelsim/wave.do

@@ -1,2 +0,0 @@
-add wave *
-add wave /glbl/GSR

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/questa/MeasDataFifo.sh

@@ -1,174 +0,0 @@
-#!/bin/bash -f
-#*********************************************************************************************************
-# Vivado (TM) v2020.2 (64-bit)
-#
-# Filename    : MeasDataFifo.sh
-# Simulator   : Mentor Graphics Questa Advanced Simulator
-# Description : Simulation script for compiling, elaborating and verifying the project source files.
-#               The script will automatically create the design libraries sub-directories in the run
-#               directory, add the library logical mappings in the simulator setup file, create default
-#               'do/prj' file, execute compilation, elaboration and simulation steps.
-#
-# Generated by Vivado on Tue Aug 29 17:27:19 +0700 2023
-# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
-#
-# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
-#
-# usage: MeasDataFifo.sh [-help]
-# usage: MeasDataFifo.sh [-lib_map_path]
-# usage: MeasDataFifo.sh [-noclean_files]
-# usage: MeasDataFifo.sh [-reset_run]
-#
-# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
-# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
-# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
-# that points to these libraries and rerun export_simulation. For more information about this switch please
-# type 'export_simulation -help' in the Tcl shell.
-#
-# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
-# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
-# executing this script. Please type 'MeasDataFifo.sh -help' for more information.
-#
-# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
-#
-#*********************************************************************************************************
-
-
-# Script info
-echo -e "MeasDataFifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
-
-# Main steps
-run()
-{
-  check_args $# $1
-  setup $1 $2
-  compile
-  elaborate
-  simulate
-}
-
-# RUN_STEP: <compile>
-compile()
-{
-  # Compile design files
-  source compile.do 2>&1 | tee -a compile.log
-
-}
-
-# RUN_STEP: <elaborate>
-elaborate()
-{
-  source elaborate.do 2>&1 | tee -a elaborate.log
-}
-
-# RUN_STEP: <simulate>
-simulate()
-{
-  vsim  -c -do "do {simulate.do}" -l simulate.log
-}
-
-# STEP: setup
-setup()
-{
-  case $1 in
-    "-lib_map_path" )
-      if [[ ($2 == "") ]]; then
-        echo -e "ERROR: Simulation library directory path not specified (type \"./MeasDataFifo.sh -help\" for more information)\n"
-        exit 1
-      fi
-     copy_setup_file $2
-    ;;
-    "-reset_run" )
-      reset_run
-      echo -e "INFO: Simulation run files deleted.\n"
-      exit 0
-    ;;
-    "-noclean_files" )
-      # do not remove previous data
-    ;;
-    * )
-     copy_setup_file $2
-  esac
-
-  create_lib_dir
-
-  # Add any setup/initialization commands here:-
-
-  # <user specific commands>
-
-}
-
-# Copy modelsim.ini file
-copy_setup_file()
-{
-  file="modelsim.ini"
-  if [[ ($1 != "") ]]; then
-    lib_map_path="$1"
-  else
-    lib_map_path="C:/Users/Stepan/Desktop/4portCompact/S5443Current/S5443_M/S5443.cache/compile_simlib/questa"
-  fi
-  if [[ ($lib_map_path != "") ]]; then
-    src_file="$lib_map_path/$file"
-    cp $src_file .
-  fi
-}
-
-# Create design library directory
-create_lib_dir()
-{
-  lib_dir="questa_lib"
-  if [[ -e $lib_dir ]]; then
-    rm -rf $lib_dir
-  fi
-
-  mkdir $lib_dir
-
-}
-
-# Delete generated data from the previous run
-reset_run()
-{
-  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
-  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
-    file="${files_to_remove[i]}"
-    if [[ -e $file ]]; then
-      rm -rf $file
-    fi
-  done
-
-  create_lib_dir
-}
-
-# Check command line arguments
-check_args()
-{
-  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
-    echo -e "ERROR: Unknown option specified '$2' (type \"./MeasDataFifo.sh -help\" for more information)\n"
-    exit 1
-  fi
-
-  if [[ ($2 == "-help" || $2 == "-h") ]]; then
-    usage
-  fi
-}
-
-# Script usage
-usage()
-{
-  msg="Usage: MeasDataFifo.sh [-help]\n\
-Usage: MeasDataFifo.sh [-lib_map_path]\n\
-Usage: MeasDataFifo.sh [-reset_run]\n\
-Usage: MeasDataFifo.sh [-noclean_files]\n\n\
-[-help] -- Print help information for this script\n\n\
-[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
-using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
-[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
-from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
--noclean_files switch.\n\n\
-[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
-  echo -e $msg
-  exit 1
-}
-
-# Launch script
-run $1 $2

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/questa/README.txt

@@ -1,49 +0,0 @@
-################################################################################
-# Vivado (TM) v2020.2 (64-bit)
-#
-# README.txt: Please read the sections below to understand the steps required to
-#             run the exported script and information about the source files.
-#
-# Generated by export_simulation on Tue Aug 29 17:27:19 +0700 2023
-#
-################################################################################
-
-1. How to run the generated simulation script:-
-
-From the shell prompt in the current directory, issue the following command:-
-
-./MeasDataFifo.sh
-
-This command will launch the 'compile', 'elaborate' and 'simulate' functions
-implemented in the script file for the 3-step flow. These functions are called
-from the main 'run' function in the script file.
-
-The 'run' function first executes the 'setup' function, the purpose of which is to
-create simulator specific setup files, create design library mappings and library
-directories and copy 'glbl.v' from the Vivado software install location into the
-current directory.
-
-The 'setup' function is also used for removing the simulator generated data in
-order to reset the current directory to the original state when export_simulation
-was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './MeasDataFifo.sh' script.
-
-./MeasDataFifo.sh -reset_run
-
-To keep the generated data from the previous run but regenerate the setup files and
-library directories, use the '-noclean_files' switch.
-
-./MeasDataFifo.sh -noclean_files
-
-For more information on the script, please type './MeasDataFifo.sh -help'.
-
-2. Additional design information files:-
-
-export_simulation generates following additional file that can be used for fetching
-the design files information or for integrating with external custom scripts.
-
-Name   : file_info.txt
-Purpose: This file contains detail design file information based on the compile order
-         when export_simulation was executed from Vivado. The file contains information
-         about the file type, name, whether it is part of the IP, associated library
-         and the file path information.

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/questa/compile.do

@@ -1,22 +0,0 @@
-vlib questa_lib/work
-vlib questa_lib/msim
-
-vlib questa_lib/msim/xpm
-vlib questa_lib/msim/xil_defaultlib
-
-vmap xpm questa_lib/msim/xpm
-vmap xil_defaultlib questa_lib/msim/xil_defaultlib
-
-vlog -work xpm  -sv \
-"C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
-"C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
-
-vcom -work xpm  -93 \
-"C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
-
-vlog -work xil_defaultlib  \
-"../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v" \
-
-vlog -work xil_defaultlib \
-"glbl.v"
-

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/questa/elaborate.do

@@ -1 +0,0 @@
-vopt +acc=npr -l elaborate.log -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.MeasDataFifo xil_defaultlib.glbl -o MeasDataFifo_opt

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/questa/file_info.txt

@@ -1,5 +0,0 @@
-xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
-xpm_memory.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
-MeasDataFifo_sim_netlist.v,verilog,xil_defaultlib,../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v,
-glbl.v,Verilog,xil_defaultlib,glbl.v

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/questa/glbl.v

@@ -1,84 +0,0 @@
-// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
-`ifndef GLBL
-`define GLBL
-`timescale  1 ps / 1 ps
-
-module glbl ();
-
-    parameter ROC_WIDTH = 100000;
-    parameter TOC_WIDTH = 0;
-    parameter GRES_WIDTH = 10000;
-    parameter GRES_START = 10000;
-
-//--------   STARTUP Globals --------------
-    wire GSR;
-    wire GTS;
-    wire GWE;
-    wire PRLD;
-    wire GRESTORE;
-    tri1 p_up_tmp;
-    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
-    wire PROGB_GLBL;
-    wire CCLKO_GLBL;
-    wire FCSBO_GLBL;
-    wire [3:0] DO_GLBL;
-    wire [3:0] DI_GLBL;
-   
-    reg GSR_int;
-    reg GTS_int;
-    reg PRLD_int;
-    reg GRESTORE_int;
-
-//--------   JTAG Globals --------------
-    wire JTAG_TDO_GLBL;
-    wire JTAG_TCK_GLBL;
-    wire JTAG_TDI_GLBL;
-    wire JTAG_TMS_GLBL;
-    wire JTAG_TRST_GLBL;
-
-    reg JTAG_CAPTURE_GLBL;
-    reg JTAG_RESET_GLBL;
-    reg JTAG_SHIFT_GLBL;
-    reg JTAG_UPDATE_GLBL;
-    reg JTAG_RUNTEST_GLBL;
-
-    reg JTAG_SEL1_GLBL = 0;
-    reg JTAG_SEL2_GLBL = 0 ;
-    reg JTAG_SEL3_GLBL = 0;
-    reg JTAG_SEL4_GLBL = 0;
-
-    reg JTAG_USER_TDO1_GLBL = 1'bz;
-    reg JTAG_USER_TDO2_GLBL = 1'bz;
-    reg JTAG_USER_TDO3_GLBL = 1'bz;
-    reg JTAG_USER_TDO4_GLBL = 1'bz;
-
-    assign (strong1, weak0) GSR = GSR_int;
-    assign (strong1, weak0) GTS = GTS_int;
-    assign (weak1, weak0) PRLD = PRLD_int;
-    assign (strong1, weak0) GRESTORE = GRESTORE_int;
-
-    initial begin
-	GSR_int = 1'b1;
-	PRLD_int = 1'b1;
-	#(ROC_WIDTH)
-	GSR_int = 1'b0;
-	PRLD_int = 1'b0;
-    end
-
-    initial begin
-	GTS_int = 1'b1;
-	#(TOC_WIDTH)
-	GTS_int = 1'b0;
-    end
-
-    initial begin 
-	GRESTORE_int = 1'b0;
-	#(GRES_START);
-	GRESTORE_int = 1'b1;
-	#(GRES_WIDTH);
-	GRESTORE_int = 1'b0;
-    end
-
-endmodule
-`endif

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/questa/simulate.do

@@ -1,16 +0,0 @@
-onbreak {quit -f}
-onerror {quit -f}
-
-vsim -lib xil_defaultlib MeasDataFifo_opt
-
-do {wave.do}
-
-view wave
-view structure
-view signals
-
-do {MeasDataFifo.udo}
-
-run -all
-
-quit -force

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/questa/wave.do

@@ -1,2 +0,0 @@
-add wave *
-add wave /glbl/GSR

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/riviera/MeasDataFifo.sh

@@ -1,153 +0,0 @@
-#!/bin/bash -f
-#*********************************************************************************************************
-# Vivado (TM) v2020.2 (64-bit)
-#
-# Filename    : MeasDataFifo.sh
-# Simulator   : Aldec Riviera-PRO Simulator
-# Description : Simulation script for compiling, elaborating and verifying the project source files.
-#               The script will automatically create the design libraries sub-directories in the run
-#               directory, add the library logical mappings in the simulator setup file, create default
-#               'do/prj' file, execute compilation, elaboration and simulation steps.
-#
-# Generated by Vivado on Tue Aug 29 17:27:19 +0700 2023
-# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
-#
-# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
-#
-# usage: MeasDataFifo.sh [-help]
-# usage: MeasDataFifo.sh [-lib_map_path]
-# usage: MeasDataFifo.sh [-noclean_files]
-# usage: MeasDataFifo.sh [-reset_run]
-#
-# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
-# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
-# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
-# that points to these libraries and rerun export_simulation. For more information about this switch please
-# type 'export_simulation -help' in the Tcl shell.
-#
-# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
-# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
-# executing this script. Please type 'MeasDataFifo.sh -help' for more information.
-#
-# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
-#
-#*********************************************************************************************************
-
-
-# Script info
-echo -e "MeasDataFifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
-
-# Main steps
-run()
-{
-  check_args $# $1
-  setup $1 $2
-  compile
-  simulate
-}
-
-# RUN_STEP: <compile>
-compile()
-{
-  # Compile design files
-  source compile.do 2>&1 | tee -a compile.log
-
-}
-
-# RUN_STEP: <simulate>
-simulate()
-{
-  runvsimsa -l simulate.log -do "do {simulate.do}"
-}
-
-# STEP: setup
-setup()
-{
-  case $1 in
-    "-lib_map_path" )
-      if [[ ($2 == "") ]]; then
-        echo -e "ERROR: Simulation library directory path not specified (type \"./MeasDataFifo.sh -help\" for more information)\n"
-        exit 1
-      fi
-     map_setup_file $2
-    ;;
-    "-reset_run" )
-      reset_run
-      echo -e "INFO: Simulation run files deleted.\n"
-      exit 0
-    ;;
-    "-noclean_files" )
-      # do not remove previous data
-    ;;
-    * )
-     map_setup_file $2
-  esac
-
-  # Add any setup/initialization commands here:-
-
-  # <user specific commands>
-
-}
-
-# Map library.cfg file
-map_setup_file()
-{
-  file="library.cfg"
-  if [[ ($1 != "") ]]; then
-    lib_map_path="$1"
-  else
-    lib_map_path="C:/Users/Stepan/Desktop/4portCompact/S5443Current/S5443_M/S5443.cache/compile_simlib/riviera"
-  fi
-  if [[ ($lib_map_path != "") ]]; then
-    src_file="$lib_map_path/$file"
-    if [[ -e $src_file ]]; then
-      vmap -link $lib_map_path
-    fi
-  fi
-}
-
-# Delete generated data from the previous run
-reset_run()
-{
-  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
-  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
-    file="${files_to_remove[i]}"
-    if [[ -e $file ]]; then
-      rm -rf $file
-    fi
-  done
-}
-
-# Check command line arguments
-check_args()
-{
-  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
-    echo -e "ERROR: Unknown option specified '$2' (type \"./MeasDataFifo.sh -help\" for more information)\n"
-    exit 1
-  fi
-
-  if [[ ($2 == "-help" || $2 == "-h") ]]; then
-    usage
-  fi
-}
-
-# Script usage
-usage()
-{
-  msg="Usage: MeasDataFifo.sh [-help]\n\
-Usage: MeasDataFifo.sh [-lib_map_path]\n\
-Usage: MeasDataFifo.sh [-reset_run]\n\
-Usage: MeasDataFifo.sh [-noclean_files]\n\n\
-[-help] -- Print help information for this script\n\n\
-[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
-using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
-[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
-from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
--noclean_files switch.\n\n\
-[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
-  echo -e $msg
-  exit 1
-}
-
-# Launch script
-run $1 $2

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/riviera/README.txt

@@ -1,49 +0,0 @@
-################################################################################
-# Vivado (TM) v2020.2 (64-bit)
-#
-# README.txt: Please read the sections below to understand the steps required to
-#             run the exported script and information about the source files.
-#
-# Generated by export_simulation on Tue Aug 29 17:27:19 +0700 2023
-#
-################################################################################
-
-1. How to run the generated simulation script:-
-
-From the shell prompt in the current directory, issue the following command:-
-
-./MeasDataFifo.sh
-
-This command will launch the 'compile', 'elaborate' and 'simulate' functions
-implemented in the script file for the 3-step flow. These functions are called
-from the main 'run' function in the script file.
-
-The 'run' function first executes the 'setup' function, the purpose of which is to
-create simulator specific setup files, create design library mappings and library
-directories and copy 'glbl.v' from the Vivado software install location into the
-current directory.
-
-The 'setup' function is also used for removing the simulator generated data in
-order to reset the current directory to the original state when export_simulation
-was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './MeasDataFifo.sh' script.
-
-./MeasDataFifo.sh -reset_run
-
-To keep the generated data from the previous run but regenerate the setup files and
-library directories, use the '-noclean_files' switch.
-
-./MeasDataFifo.sh -noclean_files
-
-For more information on the script, please type './MeasDataFifo.sh -help'.
-
-2. Additional design information files:-
-
-export_simulation generates following additional file that can be used for fetching
-the design files information or for integrating with external custom scripts.
-
-Name   : file_info.txt
-Purpose: This file contains detail design file information based on the compile order
-         when export_simulation was executed from Vivado. The file contains information
-         about the file type, name, whether it is part of the IP, associated library
-         and the file path information.

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/riviera/compile.do

@@ -1,22 +0,0 @@
-vlib work
-vlib riviera
-
-vlib riviera/xpm
-vlib riviera/xil_defaultlib
-
-vmap xpm riviera/xpm
-vmap xil_defaultlib riviera/xil_defaultlib
-
-vlog -work xpm  -sv2k12 \
-"C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
-"C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
-
-vcom -work xpm -93 \
-"C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
-
-vlog -work xil_defaultlib  -v2k5 \
-"../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v" \
-
-vlog -work xil_defaultlib \
-"glbl.v"
-

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/riviera/file_info.txt

@@ -1,5 +0,0 @@
-xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
-xpm_memory.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
-MeasDataFifo_sim_netlist.v,verilog,xil_defaultlib,../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v,
-glbl.v,Verilog,xil_defaultlib,glbl.v

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/riviera/glbl.v

@@ -1,84 +0,0 @@
-// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
-`ifndef GLBL
-`define GLBL
-`timescale  1 ps / 1 ps
-
-module glbl ();
-
-    parameter ROC_WIDTH = 100000;
-    parameter TOC_WIDTH = 0;
-    parameter GRES_WIDTH = 10000;
-    parameter GRES_START = 10000;
-
-//--------   STARTUP Globals --------------
-    wire GSR;
-    wire GTS;
-    wire GWE;
-    wire PRLD;
-    wire GRESTORE;
-    tri1 p_up_tmp;
-    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
-    wire PROGB_GLBL;
-    wire CCLKO_GLBL;
-    wire FCSBO_GLBL;
-    wire [3:0] DO_GLBL;
-    wire [3:0] DI_GLBL;
-   
-    reg GSR_int;
-    reg GTS_int;
-    reg PRLD_int;
-    reg GRESTORE_int;
-
-//--------   JTAG Globals --------------
-    wire JTAG_TDO_GLBL;
-    wire JTAG_TCK_GLBL;
-    wire JTAG_TDI_GLBL;
-    wire JTAG_TMS_GLBL;
-    wire JTAG_TRST_GLBL;
-
-    reg JTAG_CAPTURE_GLBL;
-    reg JTAG_RESET_GLBL;
-    reg JTAG_SHIFT_GLBL;
-    reg JTAG_UPDATE_GLBL;
-    reg JTAG_RUNTEST_GLBL;
-
-    reg JTAG_SEL1_GLBL = 0;
-    reg JTAG_SEL2_GLBL = 0 ;
-    reg JTAG_SEL3_GLBL = 0;
-    reg JTAG_SEL4_GLBL = 0;
-
-    reg JTAG_USER_TDO1_GLBL = 1'bz;
-    reg JTAG_USER_TDO2_GLBL = 1'bz;
-    reg JTAG_USER_TDO3_GLBL = 1'bz;
-    reg JTAG_USER_TDO4_GLBL = 1'bz;
-
-    assign (strong1, weak0) GSR = GSR_int;
-    assign (strong1, weak0) GTS = GTS_int;
-    assign (weak1, weak0) PRLD = PRLD_int;
-    assign (strong1, weak0) GRESTORE = GRESTORE_int;
-
-    initial begin
-	GSR_int = 1'b1;
-	PRLD_int = 1'b1;
-	#(ROC_WIDTH)
-	GSR_int = 1'b0;
-	PRLD_int = 1'b0;
-    end
-
-    initial begin
-	GTS_int = 1'b1;
-	#(TOC_WIDTH)
-	GTS_int = 1'b0;
-    end
-
-    initial begin 
-	GRESTORE_int = 1'b0;
-	#(GRES_START);
-	GRESTORE_int = 1'b1;
-	#(GRES_WIDTH);
-	GRESTORE_int = 1'b0;
-    end
-
-endmodule
-`endif

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/riviera/simulate.do

@@ -1,17 +0,0 @@
-onbreak {quit -force}
-onerror {quit -force}
-
-asim +access +r +m+MeasDataFifo -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.MeasDataFifo xil_defaultlib.glbl
-
-do {wave.do}
-
-view wave
-view structure
-
-do {MeasDataFifo.udo}
-
-run -all
-
-endsim
-
-quit -force

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/riviera/wave.do

@@ -1,2 +0,0 @@
-add wave *
-add wave /glbl/GSR

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/vcs/MeasDataFifo.sh

@@ -1,229 +0,0 @@
-#!/bin/bash -f
-#*********************************************************************************************************
-# Vivado (TM) v2020.2 (64-bit)
-#
-# Filename    : MeasDataFifo.sh
-# Simulator   : Synopsys Verilog Compiler Simulator
-# Description : Simulation script for compiling, elaborating and verifying the project source files.
-#               The script will automatically create the design libraries sub-directories in the run
-#               directory, add the library logical mappings in the simulator setup file, create default
-#               'do/prj' file, execute compilation, elaboration and simulation steps.
-#
-# Generated by Vivado on Tue Aug 29 17:27:19 +0700 2023
-# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
-#
-# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
-#
-# usage: MeasDataFifo.sh [-help]
-# usage: MeasDataFifo.sh [-lib_map_path]
-# usage: MeasDataFifo.sh [-noclean_files]
-# usage: MeasDataFifo.sh [-reset_run]
-#
-# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
-# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
-# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
-# that points to these libraries and rerun export_simulation. For more information about this switch please
-# type 'export_simulation -help' in the Tcl shell.
-#
-# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
-# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
-# executing this script. Please type 'MeasDataFifo.sh -help' for more information.
-#
-# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
-#
-#*********************************************************************************************************
-
-# Directory path for design sources and include directories (if any) wrt this path
-ref_dir="."
-
-# Override directory with 'export_sim_ref_dir' env path value if set in the shell
-if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
-  ref_dir="$export_sim_ref_dir"
-fi
-
-# Command line options
-vlogan_opts="-full64"
-vhdlan_opts="-full64"
-vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
-vcs_sim_opts="-ucli -licqueue -l simulate.log"
-
-# Design libraries
-design_libs=(xpm xil_defaultlib)
-
-# Simulation root library directory
-sim_lib_dir="vcs_lib"
-
-# Script info
-echo -e "MeasDataFifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
-
-# Main steps
-run()
-{
-  check_args $# $1
-  setup $1 $2
-  compile
-  elaborate
-  simulate
-}
-
-# RUN_STEP: <compile>
-compile()
-{
-  # Compile design files
-  vlogan -work xpm $vlogan_opts -sverilog \
-    "C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
-    "C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
-  2>&1 | tee -a vlogan.log
-
-  vhdlan -work xpm $vhdlan_opts \
-    "C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
-  2>&1 | tee -a vhdlan.log
-
-  vlogan -work xil_defaultlib $vlogan_opts +v2k \
-    "$ref_dir/../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v" \
-  2>&1 | tee -a vlogan.log
-
-
-  vlogan -work xil_defaultlib $vlogan_opts +v2k \
-    glbl.v \
-  2>&1 | tee -a vlogan.log
-
-}
-
-# RUN_STEP: <elaborate>
-elaborate()
-{
-  vcs $vcs_elab_opts xil_defaultlib.MeasDataFifo xil_defaultlib.glbl -o MeasDataFifo_simv
-}
-
-# RUN_STEP: <simulate>
-simulate()
-{
-  ./MeasDataFifo_simv $vcs_sim_opts -do simulate.do
-}
-
-# STEP: setup
-setup()
-{
-  case $1 in
-    "-lib_map_path" )
-      if [[ ($2 == "") ]]; then
-        echo -e "ERROR: Simulation library directory path not specified (type \"./MeasDataFifo.sh -help\" for more information)\n"
-        exit 1
-      fi
-      create_lib_mappings $2
-    ;;
-    "-reset_run" )
-      reset_run
-      echo -e "INFO: Simulation run files deleted.\n"
-      exit 0
-    ;;
-    "-noclean_files" )
-      # do not remove previous data
-    ;;
-    * )
-      create_lib_mappings $2
-  esac
-
-  create_lib_dir
-
-  # Add any setup/initialization commands here:-
-
-  # <user specific commands>
-
-}
-
-# Define design library mappings
-create_lib_mappings()
-{
-  file="synopsys_sim.setup"
-  if [[ -e $file ]]; then
-    if [[ ($1 == "") ]]; then
-      return
-    else
-      rm -rf $file
-    fi
-  fi
-
-  touch $file
-
-  lib_map_path=""
-  if [[ ($1 != "") ]]; then
-    lib_map_path="$1"
-  fi
-
-  for (( i=0; i<${#design_libs[*]}; i++ )); do
-    lib="${design_libs[i]}"
-    mapping="$lib:$sim_lib_dir/$lib"
-    echo $mapping >> $file
-  done
-
-  if [[ ($lib_map_path != "") ]]; then
-    incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
-    echo $incl_ref >> $file
-  fi
-}
-
-# Create design library directory paths
-create_lib_dir()
-{
-  if [[ -e $sim_lib_dir ]]; then
-    rm -rf $sim_lib_dir
-  fi
-
-  for (( i=0; i<${#design_libs[*]}; i++ )); do
-    lib="${design_libs[i]}"
-    lib_dir="$sim_lib_dir/$lib"
-    if [[ ! -e $lib_dir ]]; then
-      mkdir -p $lib_dir
-    fi
-  done
-}
-
-# Delete generated data from the previous run
-reset_run()
-{
-  files_to_remove=(ucli.key MeasDataFifo_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc MeasDataFifo_simv.daidir)
-  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
-    file="${files_to_remove[i]}"
-    if [[ -e $file ]]; then
-      rm -rf $file
-    fi
-  done
-
-  create_lib_dir
-}
-
-# Check command line arguments
-check_args()
-{
-  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
-    echo -e "ERROR: Unknown option specified '$2' (type \"./MeasDataFifo.sh -help\" for more information)\n"
-    exit 1
-  fi
-
-  if [[ ($2 == "-help" || $2 == "-h") ]]; then
-    usage
-  fi
-}
-
-# Script usage
-usage()
-{
-  msg="Usage: MeasDataFifo.sh [-help]\n\
-Usage: MeasDataFifo.sh [-lib_map_path]\n\
-Usage: MeasDataFifo.sh [-reset_run]\n\
-Usage: MeasDataFifo.sh [-noclean_files]\n\n\
-[-help] -- Print help information for this script\n\n\
-[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
-using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
-[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
-from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
--noclean_files switch.\n\n\
-[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
-  echo -e $msg
-  exit 1
-}
-
-# Launch script
-run $1 $2

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/vcs/README.txt

@@ -1,49 +0,0 @@
-################################################################################
-# Vivado (TM) v2020.2 (64-bit)
-#
-# README.txt: Please read the sections below to understand the steps required to
-#             run the exported script and information about the source files.
-#
-# Generated by export_simulation on Tue Aug 29 17:27:19 +0700 2023
-#
-################################################################################
-
-1. How to run the generated simulation script:-
-
-From the shell prompt in the current directory, issue the following command:-
-
-./MeasDataFifo.sh
-
-This command will launch the 'compile', 'elaborate' and 'simulate' functions
-implemented in the script file for the 3-step flow. These functions are called
-from the main 'run' function in the script file.
-
-The 'run' function first executes the 'setup' function, the purpose of which is to
-create simulator specific setup files, create design library mappings and library
-directories and copy 'glbl.v' from the Vivado software install location into the
-current directory.
-
-The 'setup' function is also used for removing the simulator generated data in
-order to reset the current directory to the original state when export_simulation
-was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './MeasDataFifo.sh' script.
-
-./MeasDataFifo.sh -reset_run
-
-To keep the generated data from the previous run but regenerate the setup files and
-library directories, use the '-noclean_files' switch.
-
-./MeasDataFifo.sh -noclean_files
-
-For more information on the script, please type './MeasDataFifo.sh -help'.
-
-2. Additional design information files:-
-
-export_simulation generates following additional file that can be used for fetching
-the design files information or for integrating with external custom scripts.
-
-Name   : file_info.txt
-Purpose: This file contains detail design file information based on the compile order
-         when export_simulation was executed from Vivado. The file contains information
-         about the file type, name, whether it is part of the IP, associated library
-         and the file path information.

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/vcs/file_info.txt

@@ -1,5 +0,0 @@
-xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
-xpm_memory.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
-MeasDataFifo_sim_netlist.v,verilog,xil_defaultlib,../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v,
-glbl.v,Verilog,xil_defaultlib,glbl.v

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/vcs/glbl.v

@@ -1,84 +0,0 @@
-// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
-`ifndef GLBL
-`define GLBL
-`timescale  1 ps / 1 ps
-
-module glbl ();
-
-    parameter ROC_WIDTH = 100000;
-    parameter TOC_WIDTH = 0;
-    parameter GRES_WIDTH = 10000;
-    parameter GRES_START = 10000;
-
-//--------   STARTUP Globals --------------
-    wire GSR;
-    wire GTS;
-    wire GWE;
-    wire PRLD;
-    wire GRESTORE;
-    tri1 p_up_tmp;
-    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
-    wire PROGB_GLBL;
-    wire CCLKO_GLBL;
-    wire FCSBO_GLBL;
-    wire [3:0] DO_GLBL;
-    wire [3:0] DI_GLBL;
-   
-    reg GSR_int;
-    reg GTS_int;
-    reg PRLD_int;
-    reg GRESTORE_int;
-
-//--------   JTAG Globals --------------
-    wire JTAG_TDO_GLBL;
-    wire JTAG_TCK_GLBL;
-    wire JTAG_TDI_GLBL;
-    wire JTAG_TMS_GLBL;
-    wire JTAG_TRST_GLBL;
-
-    reg JTAG_CAPTURE_GLBL;
-    reg JTAG_RESET_GLBL;
-    reg JTAG_SHIFT_GLBL;
-    reg JTAG_UPDATE_GLBL;
-    reg JTAG_RUNTEST_GLBL;
-
-    reg JTAG_SEL1_GLBL = 0;
-    reg JTAG_SEL2_GLBL = 0 ;
-    reg JTAG_SEL3_GLBL = 0;
-    reg JTAG_SEL4_GLBL = 0;
-
-    reg JTAG_USER_TDO1_GLBL = 1'bz;
-    reg JTAG_USER_TDO2_GLBL = 1'bz;
-    reg JTAG_USER_TDO3_GLBL = 1'bz;
-    reg JTAG_USER_TDO4_GLBL = 1'bz;
-
-    assign (strong1, weak0) GSR = GSR_int;
-    assign (strong1, weak0) GTS = GTS_int;
-    assign (weak1, weak0) PRLD = PRLD_int;
-    assign (strong1, weak0) GRESTORE = GRESTORE_int;
-
-    initial begin
-	GSR_int = 1'b1;
-	PRLD_int = 1'b1;
-	#(ROC_WIDTH)
-	GSR_int = 1'b0;
-	PRLD_int = 1'b0;
-    end
-
-    initial begin
-	GTS_int = 1'b1;
-	#(TOC_WIDTH)
-	GTS_int = 1'b0;
-    end
-
-    initial begin 
-	GRESTORE_int = 1'b0;
-	#(GRES_START);
-	GRESTORE_int = 1'b1;
-	#(GRES_WIDTH);
-	GRESTORE_int = 1'b0;
-    end
-
-endmodule
-`endif

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/vcs/simulate.do

@@ -1,2 +0,0 @@
-run
-quit

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xcelium/MeasDataFifo.sh

@@ -1,175 +0,0 @@
-#!/bin/bash -f
-#*********************************************************************************************************
-# Vivado (TM) v2020.2 (64-bit)
-#
-# Filename    : MeasDataFifo.sh
-# Simulator   : Cadence Xcelium Parallel Simulator
-# Description : Simulation script for compiling, elaborating and verifying the project source files.
-#               The script will automatically create the design libraries sub-directories in the run
-#               directory, add the library logical mappings in the simulator setup file, create default
-#               'do/prj' file, execute compilation, elaboration and simulation steps.
-#
-# Generated by Vivado on Tue Aug 29 17:27:19 +0700 2023
-# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
-#
-# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
-#
-# usage: MeasDataFifo.sh [-help]
-# usage: MeasDataFifo.sh [-lib_map_path]
-# usage: MeasDataFifo.sh [-noclean_files]
-# usage: MeasDataFifo.sh [-reset_run]
-#
-# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
-# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
-# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
-# that points to these libraries and rerun export_simulation. For more information about this switch please
-# type 'export_simulation -help' in the Tcl shell.
-#
-# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
-# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
-# executing this script. Please type 'MeasDataFifo.sh -help' for more information.
-#
-# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
-#
-#*********************************************************************************************************
-
-# Directory path for design sources and include directories (if any) wrt this path
-ref_dir="."
-
-# Override directory with 'export_sim_ref_dir' env path value if set in the shell
-if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
-  ref_dir="$export_sim_ref_dir"
-fi
-
-# Set the compiled library directory
-ref_lib_dir="."
-
-# Command line options
-xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
-
-# Design libraries
-design_libs=(xpm xil_defaultlib)
-
-# Simulation root library directory
-sim_lib_dir="xcelium_lib"
-
-# Script info
-echo -e "MeasDataFifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
-
-# Main steps
-run()
-{
-  check_args $# $1
-  setup $1 $2
-  execute
-}
-
-# RUN_STEP: <execute>
-execute()
-{
-  xrun $xrun_opts \
-       -reflib "$ref_lib_dir/unisim:unisim" \
-       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
-       -reflib "$ref_lib_dir/secureip:secureip" \
-       -reflib "$ref_lib_dir/unimacro:unimacro" \
-       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
-       -top xil_defaultlib.MeasDataFifo \
-       -f run.f \
-       -top glbl \
-       glbl.v
-}
-
-# STEP: setup
-setup()
-{
-  case $1 in
-    "-lib_map_path" )
-      if [[ ($2 == "") ]]; then
-        echo -e "ERROR: Simulation library directory path not specified (type \"./MeasDataFifo.sh -help\" for more information)\n"
-        exit 1
-      else
-        ref_lib_dir=$2
-      fi
-    ;;
-    "-reset_run" )
-      reset_run
-      echo -e "INFO: Simulation run files deleted.\n"
-      exit 0
-    ;;
-    "-noclean_files" )
-      # do not remove previous data
-    ;;
-    * )
-  esac
-
-  create_lib_dir
-
-  # Add any setup/initialization commands here:-
-
-  # <user specific commands>
-
-}
-
-# Create design library directory paths
-create_lib_dir()
-{
-  if [[ -e $sim_lib_dir ]]; then
-    rm -rf $sim_lib_dir
-  fi
-
-  for (( i=0; i<${#design_libs[*]}; i++ )); do
-    lib="${design_libs[i]}"
-    lib_dir="$sim_lib_dir/$lib"
-    if [[ ! -e $lib_dir ]]; then
-      mkdir -p $lib_dir
-    fi
-  done
-}
-
-# Delete generated data from the previous run
-reset_run()
-{
-  files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium)
-  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
-    file="${files_to_remove[i]}"
-    if [[ -e $file ]]; then
-      rm -rf $file
-    fi
-  done
-
-  create_lib_dir
-}
-
-# Check command line arguments
-check_args()
-{
-  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
-    echo -e "ERROR: Unknown option specified '$2' (type \"./MeasDataFifo.sh -help\" for more information)\n"
-    exit 1
-  fi
-
-  if [[ ($2 == "-help" || $2 == "-h") ]]; then
-    usage
-  fi
-}
-
-# Script usage
-usage()
-{
-  msg="Usage: MeasDataFifo.sh [-help]\n\
-Usage: MeasDataFifo.sh [-lib_map_path]\n\
-Usage: MeasDataFifo.sh [-reset_run]\n\
-Usage: MeasDataFifo.sh [-noclean_files]\n\n\
-[-help] -- Print help information for this script\n\n\
-[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
-using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
-[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
-from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
--noclean_files switch.\n\n\
-[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
-  echo -e $msg
-  exit 1
-}
-
-# Launch script
-run $1 $2

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xcelium/README.txt

@@ -1,48 +0,0 @@
-################################################################################
-# Vivado (TM) v2020.2 (64-bit)
-#
-# README.txt: Please read the sections below to understand the steps required to
-#             run the exported script and information about the source files.
-#
-# Generated by export_simulation on Tue Aug 29 17:27:19 +0700 2023
-#
-################################################################################
-
-1. How to run the generated simulation script:-
-
-From the shell prompt in the current directory, issue the following command:-
-
-./MeasDataFifo.sh
-
-This command will launch the 'execute' function for the single-step flow. This
-function is called from the main 'run' function in the script file.
-
-The 'run' function first executes the 'setup' function, the purpose of which is to
-create simulator specific setup files, create design library mappings and library
-directories and copy 'glbl.v' from the Vivado software install location into the
-current directory.
-
-The 'setup' function is also used for removing the simulator generated data in
-order to reset the current directory to the original state when export_simulation
-was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './MeasDataFifo.sh' script.
-
-./MeasDataFifo.sh -reset_run
-
-To keep the generated data from the previous run but regenerate the setup files and
-library directories, use the '-noclean_files' switch.
-
-./MeasDataFifo.sh -noclean_files
-
-For more information on the script, please type './MeasDataFifo.sh -help'.
-
-2. Additional design information files:-
-
-export_simulation generates following additional file that can be used for fetching
-the design files information or for integrating with external custom scripts.
-
-Name   : file_info.txt
-Purpose: This file contains detail design file information based on the compile order
-         when export_simulation was executed from Vivado. The file contains information
-         about the file type, name, whether it is part of the IP, associated library
-         and the file path information.

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xcelium/file_info.txt

@@ -1,5 +0,0 @@
-xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
-xpm_memory.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
-MeasDataFifo_sim_netlist.v,verilog,xil_defaultlib,../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v,
-glbl.v,Verilog,xil_defaultlib,glbl.v

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xcelium/glbl.v

@@ -1,84 +0,0 @@
-// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
-`ifndef GLBL
-`define GLBL
-`timescale  1 ps / 1 ps
-
-module glbl ();
-
-    parameter ROC_WIDTH = 100000;
-    parameter TOC_WIDTH = 0;
-    parameter GRES_WIDTH = 10000;
-    parameter GRES_START = 10000;
-
-//--------   STARTUP Globals --------------
-    wire GSR;
-    wire GTS;
-    wire GWE;
-    wire PRLD;
-    wire GRESTORE;
-    tri1 p_up_tmp;
-    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
-    wire PROGB_GLBL;
-    wire CCLKO_GLBL;
-    wire FCSBO_GLBL;
-    wire [3:0] DO_GLBL;
-    wire [3:0] DI_GLBL;
-   
-    reg GSR_int;
-    reg GTS_int;
-    reg PRLD_int;
-    reg GRESTORE_int;
-
-//--------   JTAG Globals --------------
-    wire JTAG_TDO_GLBL;
-    wire JTAG_TCK_GLBL;
-    wire JTAG_TDI_GLBL;
-    wire JTAG_TMS_GLBL;
-    wire JTAG_TRST_GLBL;
-
-    reg JTAG_CAPTURE_GLBL;
-    reg JTAG_RESET_GLBL;
-    reg JTAG_SHIFT_GLBL;
-    reg JTAG_UPDATE_GLBL;
-    reg JTAG_RUNTEST_GLBL;
-
-    reg JTAG_SEL1_GLBL = 0;
-    reg JTAG_SEL2_GLBL = 0 ;
-    reg JTAG_SEL3_GLBL = 0;
-    reg JTAG_SEL4_GLBL = 0;
-
-    reg JTAG_USER_TDO1_GLBL = 1'bz;
-    reg JTAG_USER_TDO2_GLBL = 1'bz;
-    reg JTAG_USER_TDO3_GLBL = 1'bz;
-    reg JTAG_USER_TDO4_GLBL = 1'bz;
-
-    assign (strong1, weak0) GSR = GSR_int;
-    assign (strong1, weak0) GTS = GTS_int;
-    assign (weak1, weak0) PRLD = PRLD_int;
-    assign (strong1, weak0) GRESTORE = GRESTORE_int;
-
-    initial begin
-	GSR_int = 1'b1;
-	PRLD_int = 1'b1;
-	#(ROC_WIDTH)
-	GSR_int = 1'b0;
-	PRLD_int = 1'b0;
-    end
-
-    initial begin
-	GTS_int = 1'b1;
-	#(TOC_WIDTH)
-	GTS_int = 1'b0;
-    end
-
-    initial begin 
-	GRESTORE_int = 1'b0;
-	#(GRES_START);
-	GRESTORE_int = 1'b1;
-	#(GRES_WIDTH);
-	GRESTORE_int = 1'b0;
-    end
-
-endmodule
-`endif

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xcelium/run.f

@@ -1,14 +0,0 @@
--makelib xcelium_lib/xpm -sv \
-  "C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
-  "C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
--endlib
--makelib xcelium_lib/xpm \
-  "C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
--endlib
--makelib xcelium_lib/xil_defaultlib \
-  "../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v" \
--endlib
--makelib xcelium_lib/xil_defaultlib \
-  glbl.v
--endlib
-

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xsim/MeasDataFifo.sh

@@ -1,212 +0,0 @@
-#!/bin/bash -f
-#*********************************************************************************************************
-# Vivado (TM) v2020.2 (64-bit)
-#
-# Filename    : MeasDataFifo.sh
-# Simulator   : Xilinx Vivado Simulator
-# Description : Simulation script for compiling, elaborating and verifying the project source files.
-#               The script will automatically create the design libraries sub-directories in the run
-#               directory, add the library logical mappings in the simulator setup file, create default
-#               'do/prj' file, execute compilation, elaboration and simulation steps.
-#
-# Generated by Vivado on Tue Aug 29 17:27:19 +0700 2023
-# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
-#
-# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
-#
-# usage: MeasDataFifo.sh [-help]
-# usage: MeasDataFifo.sh [-lib_map_path]
-# usage: MeasDataFifo.sh [-noclean_files]
-# usage: MeasDataFifo.sh [-reset_run]
-#
-#*********************************************************************************************************
-
-# Command line options
-xv_boost_lib_path=C:/Xilinx/Vivado/2020.2/tps/boost_1_64_0
-xvlog_opts="--relax"
-
-
-# Script info
-echo -e "MeasDataFifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
-
-# Main steps
-run()
-{
-  check_args $# $1
-  setup $1 $2
-  compile
-  elaborate
-  simulate
-}
-
-# RUN_STEP: <compile>
-compile()
-{
-  # Compile design files
-  xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
-
-}
-
-# RUN_STEP: <elaborate>
-elaborate()
-{
-  xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot MeasDataFifo xil_defaultlib.MeasDataFifo xil_defaultlib.glbl -log elaborate.log
-}
-
-# RUN_STEP: <simulate>
-simulate()
-{
-  xsim MeasDataFifo -key {Behavioral:sim_1:Functional:MeasDataFifo} -tclbatch cmd.tcl -log simulate.log
-}
-
-# STEP: setup
-setup()
-{
-  case $1 in
-    "-lib_map_path" )
-      if [[ ($2 == "") ]]; then
-        echo -e "ERROR: Simulation library directory path not specified (type \"./MeasDataFifo.sh -help\" for more information)\n"
-        exit 1
-      fi
-     copy_setup_file $2
-    ;;
-    "-reset_run" )
-      reset_run
-      echo -e "INFO: Simulation run files deleted.\n"
-      exit 0
-    ;;
-    "-noclean_files" )
-      # do not remove previous data
-    ;;
-    * )
-     copy_setup_file $2
-  esac
-
-  # Add any setup/initialization commands here:-
-
-  # <user specific commands>
-
-}
-
-# Copy xsim.ini file
-copy_setup_file()
-{
-  file="xsim.ini"
-  lib_map_path="C:/Xilinx/Vivado/2020.2/data/xsim"
-  if [[ ($1 != "") ]]; then
-    lib_map_path="$1"
-  fi
-  if [[ ($lib_map_path != "") ]]; then
-    src_file="$lib_map_path/$file"
-    if [[ -e $src_file ]]; then
-      cp $src_file .
-    fi
-
-    # Map local design libraries to xsim.ini
-    map_local_libs
-
-  fi
-}
-
-# Map local design libraries
-map_local_libs()
-{
-  updated_mappings=()
-  local_mappings=()
-
-  # Local design libraries
-  local_libs=()
-
-  if [[ 0 == ${#local_libs[@]} ]]; then
-    return
-  fi
-
-  file="xsim.ini"
-  file_backup="xsim.ini.bak"
-
-  if [[ -e $file ]]; then
-    rm -f $file_backup
-    # Create a backup copy of the xsim.ini file
-    cp $file $file_backup
-    # Read libraries from backup file and search in local library collection
-    while read -r line
-    do
-      IN=$line
-      # Split mapping entry with '=' delimiter to fetch library name and mapping
-      read lib_name mapping <<<$(IFS="="; echo $IN)
-      # If local library found, then construct the local mapping and add to local mapping collection
-      if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
-        line="$lib_name=xsim.dir/$lib_name"
-        local_mappings+=("$lib_name")
-      fi
-      # Add to updated library mapping collection
-      updated_mappings+=("$line")
-    done < "$file_backup"
-    # Append local libraries not found originally from xsim.ini
-    for (( i=0; i<${#local_libs[*]}; i++ )); do
-      lib_name="${local_libs[i]}"
-      if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
-        line="$lib_name=xsim.dir/$lib_name"
-        updated_mappings+=("$line")
-      fi
-    done
-    # Write updated mappings in xsim.ini
-    rm -f $file
-    for (( i=0; i<${#updated_mappings[*]}; i++ )); do
-      lib_name="${updated_mappings[i]}"
-      echo $lib_name >> $file
-    done
-  else
-    for (( i=0; i<${#local_libs[*]}; i++ )); do
-      lib_name="${local_libs[i]}"
-      mapping="$lib_name=xsim.dir/$lib_name"
-      echo $mapping >> $file
-    done
-  fi
-}
-
-# Delete generated data from the previous run
-reset_run()
-{
-  files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb MeasDataFifo.wdb xsim.dir)
-  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
-    file="${files_to_remove[i]}"
-    if [[ -e $file ]]; then
-      rm -rf $file
-    fi
-  done
-}
-
-# Check command line arguments
-check_args()
-{
-  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
-    echo -e "ERROR: Unknown option specified '$2' (type \"./MeasDataFifo.sh -help\" for more information)\n"
-    exit 1
-  fi
-
-  if [[ ($2 == "-help" || $2 == "-h") ]]; then
-    usage
-  fi
-}
-
-# Script usage
-usage()
-{
-  msg="Usage: MeasDataFifo.sh [-help]\n\
-Usage: MeasDataFifo.sh [-lib_map_path]\n\
-Usage: MeasDataFifo.sh [-reset_run]\n\
-Usage: MeasDataFifo.sh [-noclean_files]\n\n\
-[-help] -- Print help information for this script\n\n\
-[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
-using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
-[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
-from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
--noclean_files switch.\n\n\
-[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
-  echo -e $msg
-  exit 1
-}
-
-# Launch script
-run $1 $2

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xsim/README.txt

@@ -1,49 +0,0 @@
-################################################################################
-# Vivado (TM) v2020.2 (64-bit)
-#
-# README.txt: Please read the sections below to understand the steps required to
-#             run the exported script and information about the source files.
-#
-# Generated by export_simulation on Tue Aug 29 17:27:19 +0700 2023
-#
-################################################################################
-
-1. How to run the generated simulation script:-
-
-From the shell prompt in the current directory, issue the following command:-
-
-./MeasDataFifo.sh
-
-This command will launch the 'compile', 'elaborate' and 'simulate' functions
-implemented in the script file for the 3-step flow. These functions are called
-from the main 'run' function in the script file.
-
-The 'run' function first executes the 'setup' function, the purpose of which is to
-create simulator specific setup files, create design library mappings and library
-directories and copy 'glbl.v' from the Vivado software install location into the
-current directory.
-
-The 'setup' function is also used for removing the simulator generated data in
-order to reset the current directory to the original state when export_simulation
-was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './MeasDataFifo.sh' script.
-
-./MeasDataFifo.sh -reset_run
-
-To keep the generated data from the previous run but regenerate the setup files and
-library directories, use the '-noclean_files' switch.
-
-./MeasDataFifo.sh -noclean_files
-
-For more information on the script, please type './MeasDataFifo.sh -help'.
-
-2. Additional design information files:-
-
-export_simulation generates following additional file that can be used for fetching
-the design files information or for integrating with external custom scripts.
-
-Name   : file_info.txt
-Purpose: This file contains detail design file information based on the compile order
-         when export_simulation was executed from Vivado. The file contains information
-         about the file type, name, whether it is part of the IP, associated library
-         and the file path information.

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xsim/cmd.tcl

@@ -1,12 +0,0 @@
-set curr_wave [current_wave_config]
-if { [string length $curr_wave] == 0 } {
-  if { [llength [get_objects]] > 0} {
-    add_wave /
-    set_property needs_save false [current_wave_config]
-  } else {
-     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-  }
-}
-
-run -all
-quit

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xsim/elab.opt

@@ -1 +0,0 @@
---relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot MeasDataFifo xil_defaultlib.MeasDataFifo xil_defaultlib.glbl -log elaborate.log

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xsim/file_info.txt

@@ -1,2 +0,0 @@
-MeasDataFifo_sim_netlist.v,verilog,xil_defaultlib,../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v,
-glbl.v,Verilog,xil_defaultlib,glbl.v

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xsim/glbl.v

@@ -1,84 +0,0 @@
-// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
-`ifndef GLBL
-`define GLBL
-`timescale  1 ps / 1 ps
-
-module glbl ();
-
-    parameter ROC_WIDTH = 100000;
-    parameter TOC_WIDTH = 0;
-    parameter GRES_WIDTH = 10000;
-    parameter GRES_START = 10000;
-
-//--------   STARTUP Globals --------------
-    wire GSR;
-    wire GTS;
-    wire GWE;
-    wire PRLD;
-    wire GRESTORE;
-    tri1 p_up_tmp;
-    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
-    wire PROGB_GLBL;
-    wire CCLKO_GLBL;
-    wire FCSBO_GLBL;
-    wire [3:0] DO_GLBL;
-    wire [3:0] DI_GLBL;
-   
-    reg GSR_int;
-    reg GTS_int;
-    reg PRLD_int;
-    reg GRESTORE_int;
-
-//--------   JTAG Globals --------------
-    wire JTAG_TDO_GLBL;
-    wire JTAG_TCK_GLBL;
-    wire JTAG_TDI_GLBL;
-    wire JTAG_TMS_GLBL;
-    wire JTAG_TRST_GLBL;
-
-    reg JTAG_CAPTURE_GLBL;
-    reg JTAG_RESET_GLBL;
-    reg JTAG_SHIFT_GLBL;
-    reg JTAG_UPDATE_GLBL;
-    reg JTAG_RUNTEST_GLBL;
-
-    reg JTAG_SEL1_GLBL = 0;
-    reg JTAG_SEL2_GLBL = 0 ;
-    reg JTAG_SEL3_GLBL = 0;
-    reg JTAG_SEL4_GLBL = 0;
-
-    reg JTAG_USER_TDO1_GLBL = 1'bz;
-    reg JTAG_USER_TDO2_GLBL = 1'bz;
-    reg JTAG_USER_TDO3_GLBL = 1'bz;
-    reg JTAG_USER_TDO4_GLBL = 1'bz;
-
-    assign (strong1, weak0) GSR = GSR_int;
-    assign (strong1, weak0) GTS = GTS_int;
-    assign (weak1, weak0) PRLD = PRLD_int;
-    assign (strong1, weak0) GRESTORE = GRESTORE_int;
-
-    initial begin
-	GSR_int = 1'b1;
-	PRLD_int = 1'b1;
-	#(ROC_WIDTH)
-	GSR_int = 1'b0;
-	PRLD_int = 1'b0;
-    end
-
-    initial begin
-	GTS_int = 1'b1;
-	#(TOC_WIDTH)
-	GTS_int = 1'b0;
-    end
-
-    initial begin 
-	GRESTORE_int = 1'b0;
-	#(GRES_START);
-	GRESTORE_int = 1'b1;
-	#(GRES_WIDTH);
-	GRESTORE_int = 1'b0;
-    end
-
-endmodule
-`endif

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xsim/vlog.prj

@@ -1,6 +0,0 @@
-verilog xil_defaultlib  \
-"../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v" \
-
-verilog xil_defaultlib "glbl.v"
-
-nosort

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xsim/xsim.ini

@@ -1,497 +0,0 @@
-std=$RDI_DATADIR/xsim/vhdl/std
-ieee=$RDI_DATADIR/xsim/vhdl/ieee
-ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed
-vl=$RDI_DATADIR/xsim/vhdl/vl
-synopsys=$RDI_DATADIR/xsim/vhdl/synopsys
-uvm=$RDI_DATADIR/xsim/system_verilog/uvm
-secureip=$RDI_DATADIR/xsim/verilog/secureip
-unisim=$RDI_DATADIR/xsim/vhdl/unisim
-unimacro=$RDI_DATADIR/xsim/vhdl/unimacro
-unifast=$RDI_DATADIR/xsim/vhdl/unifast
-unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver
-unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver
-unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver
-simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver
-axi_clock_converter_v2_1_21=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_21
-axis_dbg_stub_v1_0_0=$RDI_DATADIR/xsim/ip/axis_dbg_stub_v1_0_0
-xlconcat_v2_1_4=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_4
-lte_fft_v2_0_20=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_20
-axi_remapper_rx_v1_0_0=$RDI_DATADIR/xsim/ip/axi_remapper_rx_v1_0_0
-noc_ncrb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_ncrb_v1_0_0
-lut_buffer_v1_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v1_0_0
-system_cache_v5_0_3=$RDI_DATADIR/xsim/ip/system_cache_v5_0_3
-rld3_pl_v1_0_4=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_4
-ernic_v3_0_0=$RDI_DATADIR/xsim/ip/ernic_v3_0_0
-xfft_v9_1_5=$RDI_DATADIR/xsim/ip/xfft_v9_1_5
-pr_axi_shutdown_manager_v1_0_2=$RDI_DATADIR/xsim/ip/pr_axi_shutdown_manager_v1_0_2
-axi_dwidth_converter_v2_1_22=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_22
-shell_utils_addr_remap_v1_0_1=$RDI_DATADIR/xsim/ip/shell_utils_addr_remap_v1_0_1
-v_hdmi_rx1_v1_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx1_v1_0_0
-ieee802d3_rs_fec_v1_0_18=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v1_0_18
-mult_gen_v12_0_16=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_16
-processing_system7_v5_5_6=$RDI_DATADIR/xsim/ip/processing_system7_v5_5_6
-noc_nps4_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps4_v1_0_0
-axis_switch_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_switch_sc_v1_1
-lib_bmg_v1_0_13=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_13
-xbip_bram18k_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_6
-cordic_v6_0_16=$RDI_DATADIR/xsim/ip/cordic_v6_0_16
-tmr_sem_v1_0_15=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_15
-axis_dwidth_converter_v1_1_21=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_21
-xlslice_v1_0_2=$RDI_DATADIR/xsim/ip/xlslice_v1_0_2
-xtlm=$RDI_DATADIR/xsim/ip/xtlm
-rs_encoder_v9_0_16=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_16
-axis_ila_ct_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_ct_v1_0_0
-v_uhdsdi_audio_v1_1_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_1_0
-v_tpg_v8_1_0=$RDI_DATADIR/xsim/ip/v_tpg_v8_1_0
-c_counter_binary_v12_0_14=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_14
-common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1
-axis_switch_v1_1_22=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_22
-rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1
-rs_toolbox_v9_0_8=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_8
-v_letterbox_v1_1_0=$RDI_DATADIR/xsim/ip/v_letterbox_v1_1_0
-high_speed_selectio_wiz_v3_6_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_6_1
-axi_chip2chip_v5_0_9=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_9
-v_demosaic_v1_1_0=$RDI_DATADIR/xsim/ip/v_demosaic_v1_1_0
-v_multi_scaler_v1_2_0=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_2_0
-ieee802d3_200g_rs_fec_v2_0_0=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v2_0_0
-axi_memory_init_v1_0_3=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_3
-high_speed_selectio_wiz_v3_4_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_4_1
-duc_ddc_compiler_v3_0_15=$RDI_DATADIR/xsim/ip/duc_ddc_compiler_v3_0_15
-ai_noc=$RDI_DATADIR/xsim/ip/ai_noc
-bs_mux_v1_0_0=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_0
-ecc_v2_0_13=$RDI_DATADIR/xsim/ip/ecc_v2_0_13
-axis_interconnect_v1_1_18=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_18
-cmac_v2_6_2=$RDI_DATADIR/xsim/ip/cmac_v2_6_2
-high_speed_selectio_wiz_v3_3_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_3_1
-axi_pcie_v2_9_4=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_4
-rld3_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_0
-sim_qdma_sc_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_sc_v1_0
-v_axi4s_remap_v1_0_14=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_14
-system_cache_v4_0_6=$RDI_DATADIR/xsim/ip/system_cache_v4_0_6
-axi_vfifo_ctrl_v2_0_24=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_24
-ernic_v1_0_2=$RDI_DATADIR/xsim/ip/ernic_v1_0_2
-multi_channel_25g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_11
-oddr_v1_0_2=$RDI_DATADIR/xsim/ip/oddr_v1_0_2
-mem_pl_v1_0_0=$RDI_DATADIR/xsim/ip/mem_pl_v1_0_0
-fit_timer_v2_0_10=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_10
-v_axi4s_vid_out_v4_0_11=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_11
-v_letterbox_v1_0_16=$RDI_DATADIR/xsim/ip/v_letterbox_v1_0_16
-clk_gen_sim_v1_0_0=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_0
-lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0
-axi_traffic_gen_v2_0_23=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v2_0_23
-gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux
-lte_rach_detector_v3_1_8=$RDI_DATADIR/xsim/ip/lte_rach_detector_v3_1_8
-lte_fft_v2_1_3=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_3
-g709_rs_decoder_v2_2_9=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_9
-lte_3gpp_channel_estimator_v2_0_17=$RDI_DATADIR/xsim/ip/lte_3gpp_channel_estimator_v2_0_17
-g975_efec_i4_v1_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_18
-stm_v1_0_0=$RDI_DATADIR/xsim/ip/stm_v1_0_0
-xbip_pipe_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_6
-axi_perf_mon_v5_0_24=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_24
-axi_timebase_wdt_v3_0_14=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_14
-fec_5g_common_v1_0_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_0_1
-g709_fec_v2_4_2=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_2
-v_scenechange_v1_0_4=$RDI_DATADIR/xsim/ip/v_scenechange_v1_0_4
-displayport_v8_1_3=$RDI_DATADIR/xsim/ip/displayport_v8_1_3
-spdif_v2_0_23=$RDI_DATADIR/xsim/ip/spdif_v2_0_23
-dp_videoaxi4s_bridge_v1_0_1=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_1
-noc_nps6_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps6_v1_0_0
-sem_v4_1_13=$RDI_DATADIR/xsim/ip/sem_v4_1_13
-gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4
-axi_mmu_v2_1_20=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_20
-nvmeha_v1_0_3=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_3
-v_vid_in_axi4s_v4_0_9=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_9
-v_gamma_lut_v1_0_8=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_0_8
-axi_traffic_gen_v3_0_8=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_8
-tmr_inject_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_4
-axis_accelerator_adapter_v2_1_16=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_16
-hdcp22_rng_v1_0_1=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_1
-rama_v1_1_7_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_7_lib
-trace_s2mm_v1_0_0=$RDI_DATADIR/xsim/ip/trace_s2mm_v1_0_0
-xbip_counter_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_6
-v_mix_v5_1_0=$RDI_DATADIR/xsim/ip/v_mix_v5_1_0
-dft_v4_2_1=$RDI_DATADIR/xsim/ip/dft_v4_2_1
-ta_dma_v1_0_6=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_6
-blk_mem_gen_v8_4_4=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_4
-axi_ethernet_buffer_v2_0_23=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_23
-stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0
-lte_3gpp_mimo_decoder_v3_0_16=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_decoder_v3_0_16
-ieee802d3_50g_rs_fec_v2_0_6=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_6
-xbip_dsp48_acc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_6
-axi_sg_v4_1_13=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_13
-v_hdmi_tx1_v1_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx1_v1_0_0
-v_hdmi_tx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v2_0_0
-v_tc_v6_2_1=$RDI_DATADIR/xsim/ip/v_tc_v6_2_1
-noc_nsu_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nsu_v1_0_0
-high_speed_selectio_wiz_v3_2_3=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_2_3
-qdriv_pl_v1_0_2=$RDI_DATADIR/xsim/ip/qdriv_pl_v1_0_2
-axi_uart16550_v2_0_24=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_24
-microblaze_v11_0_4=$RDI_DATADIR/xsim/ip/microblaze_v11_0_4
-advanced_io_wizard_phy_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_0
-mdm_v3_2_19=$RDI_DATADIR/xsim/ip/mdm_v3_2_19
-versal_cips_ps_vip_v1_0_0=$RDI_DATADIR/xsim/ip/versal_cips_ps_vip_v1_0_0
-v_hcresampler_v1_0_16=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_0_16
-lte_3gpp_mimo_encoder_v4_0_15=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_encoder_v4_0_15
-axis_clock_converter_v1_1_23=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_23
-v_scenechange_v1_1_0=$RDI_DATADIR/xsim/ip/v_scenechange_v1_1_0
-mpegtsmux_v1_0_2=$RDI_DATADIR/xsim/ip/mpegtsmux_v1_0_2
-axi_sideband_util_v1_0_6=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_6
-dsp_macro_v1_0_1=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_1
-ll_compress_v1_0_0=$RDI_DATADIR/xsim/ip/ll_compress_v1_0_0
-sim_ddr_v1_0=$RDI_DATADIR/xsim/ip/sim_ddr_v1_0
-gtwizard_ultrascale_v1_7_9=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_9
-vid_phy_controller_v2_1_9=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_9
-ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig
-axi_apb_bridge_v3_0_17=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_17
-xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0
-rst_vip_v1_0_4=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_4
-xbip_dsp48_multadd_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_6
-canfd_v3_0_1=$RDI_DATADIR/xsim/ip/canfd_v3_0_1
-axis_broadcaster_v1_1_21=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_21
-mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2
-lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2
-pr_bitstream_monitor_v1_0_2=$RDI_DATADIR/xsim/ip/pr_bitstream_monitor_v1_0_2
-amm_axi_bridge_v1_0_8=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_8
-canfd_v2_0_4=$RDI_DATADIR/xsim/ip/canfd_v2_0_4
-polar_v1_0_6=$RDI_DATADIR/xsim/ip/polar_v1_0_6
-can_v5_0_25=$RDI_DATADIR/xsim/ip/can_v5_0_25
-axi_timer_v2_0_24=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_24
-jesd204_v7_2_10=$RDI_DATADIR/xsim/ip/jesd204_v7_2_10
-axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0
-c_mux_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_6
-axi_firewall_v1_1_1=$RDI_DATADIR/xsim/ip/axi_firewall_v1_1_1
-v_axi4s_remap_v1_1_0=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_1_0
-adc_dac_if_phy_v1_0_0=$RDI_DATADIR/xsim/ip/adc_dac_if_phy_v1_0_0
-microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6
-axi_tg_lib=$RDI_DATADIR/xsim/ip/axi_tg_lib
-dfx_controller_v1_0_1=$RDI_DATADIR/xsim/ip/dfx_controller_v1_0_1
-cic_compiler_v4_0_15=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_15
-processing_system7_vip_v1_0_10=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_10
-axi_intc_v4_1_15=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_15
-audio_clock_recovery_unit_v1_0_2=$RDI_DATADIR/xsim/ip/audio_clock_recovery_unit_v1_0_2
-axi_protocol_converter_v2_1_22=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_22
-remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4
-versal_cips_v2_1_0=$RDI_DATADIR/xsim/ip/versal_cips_v2_1_0
-g975_efec_i7_v2_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_18
-v_hscaler_v1_1_0=$RDI_DATADIR/xsim/ip/v_hscaler_v1_1_0
-axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4
-pcie_dma_versal_v2_0_1=$RDI_DATADIR/xsim/ip/pcie_dma_versal_v2_0_1
-v_tpg_v8_0_4=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_4
-c_compare_v12_0_6=$RDI_DATADIR/xsim/ip/c_compare_v12_0_6
-viterbi_v9_1_12=$RDI_DATADIR/xsim/ip/viterbi_v9_1_12
-pr_decoupler_v1_0_9=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_9
-axi_bram_ctrl_v4_1_4=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_4
-fc32_rs_fec_v1_0_16=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_16
-pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0
-axi_register_slice_v2_1_22=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_22
-dfx_axi_shutdown_manager_v1_0_0=$RDI_DATADIR/xsim/ip/dfx_axi_shutdown_manager_v1_0_0
-soft_ecc_proxy_v1_0_0=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_0_0
-hdcp_keymngmt_blk_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_0
-gig_ethernet_pcs_pma_v16_2_1=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_2_1
-sim_qdma_cpp_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_cpp_v1_0
-ddr4_pl_v1_0_3=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_3
-axi_vdma_v6_3_10=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_10
-xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0
-xbip_accum_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_6
-axi_emc_v3_0_22=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_22
-jesd204c_v4_2_3=$RDI_DATADIR/xsim/ip/jesd204c_v4_2_3
-axi_epc_v2_0_25=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_25
-gig_ethernet_pcs_pma_v16_1_9=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_1_9
-v_vscaler_v1_1_0=$RDI_DATADIR/xsim/ip/v_vscaler_v1_1_0
-generic_baseblocks_v2_1_0=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_0
-usxgmii_v1_2_0=$RDI_DATADIR/xsim/ip/usxgmii_v1_2_0
-ieee802d3_400g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v1_0_11
-dft_v4_1_1=$RDI_DATADIR/xsim/ip/dft_v4_1_1
-v_frmbuf_rd_v2_2_0=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_2_0
-ieee802d3_25g_rs_fec_v1_0_18=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_18
-ethernet_1_10_25g_v2_6_0=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_6_0
-v_frmbuf_wr_v2_2_0=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_2_0
-tmr_manager_v1_0_6=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_6
-trace_hub_v1_1_0=$RDI_DATADIR/xsim/ip/trace_hub_v1_1_0
-axi_iic_v2_0_25=$RDI_DATADIR/xsim/ip/axi_iic_v2_0_25
-pc_cfr_v6_4_0=$RDI_DATADIR/xsim/ip/pc_cfr_v6_4_0
-v_tpg_v7_0_16=$RDI_DATADIR/xsim/ip/v_tpg_v7_0_16
-lmb_bram_if_cntlr_v4_0_19=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_19
-v_vcresampler_v1_0_16=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_0_16
-axi_ethernetlite_v3_0_21=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_21
-ldpc_v2_0_6=$RDI_DATADIR/xsim/ip/ldpc_v2_0_6
-c_gate_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_6
-v_mix_v5_0_1=$RDI_DATADIR/xsim/ip/v_mix_v5_0_1
-audio_formatter_v1_0_4=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_4
-flexo_100g_rs_fec_v1_0_16=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_16
-uram_rd_back_v1_0_1=$RDI_DATADIR/xsim/ip/uram_rd_back_v1_0_1
-ptp_1588_timer_syncer_v1_0_1=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v1_0_1
-ieee802d3_clause74_fec_v1_0_8=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_8
-axis_cap_ctrl_v1_0_0=$RDI_DATADIR/xsim/ip/axis_cap_ctrl_v1_0_0
-common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0
-xlconstant_v1_1_7=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_7
-xsdbm_v2_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v2_0_0
-etrnic_v1_1_3=$RDI_DATADIR/xsim/ip/etrnic_v1_1_3
-pci64_v5_0_11=$RDI_DATADIR/xsim/ip/pci64_v5_0_11
-axi_gpio_v2_0_24=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_24
-dfx_decoupler_v1_0_1=$RDI_DATADIR/xsim/ip/dfx_decoupler_v1_0_1
-tcc_encoder_3gpplte_v4_0_16=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_16
-axi_ahblite_bridge_v3_0_19=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_19
-in_system_ibert_v1_0_12=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_12
-axis_register_slice_v1_1_22=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_22
-util_idelay_ctrl_v1_0_2=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_2
-xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0
-pci32_v5_0_12=$RDI_DATADIR/xsim/ip/pci32_v5_0_12
-v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0
-axi_cdma_v4_1_22=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_22
-axi_master_burst_v2_0_7=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_7
-hdcp22_cipher_dp_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_0
-v_hcresampler_v1_1_0=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_1_0
-sid_v8_0_15=$RDI_DATADIR/xsim/ip/sid_v8_0_15
-ahblite_axi_bridge_v3_0_17=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_17
-zynq_ultra_ps_e_v3_3_3=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_3
-timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4
-axi4svideo_bridge_v1_0_11=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_11
-xbip_multadd_v3_0_15=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_15
-axis_data_fifo_v1_1_23=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_23
-c_shift_ram_v12_0_14=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_14
-xbip_dsp48_mult_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_6
-noc_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_0
-gtwizard_ultrascale_v1_6_10=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_10
-axis_data_fifo_v2_0_4=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_4
-rs_decoder_v9_0_17=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_17
-i2s_receiver_v1_0_4=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_4
-perf_axi_tg_v1_0_11=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_11
-interlaken_v2_4_7=$RDI_DATADIR/xsim/ip/interlaken_v2_4_7
-xfft_v7_2_11=$RDI_DATADIR/xsim/ip/xfft_v7_2_11
-smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0
-g709_fec_v2_3_6=$RDI_DATADIR/xsim/ip/g709_fec_v2_3_6
-axis_ila_intf_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_intf_v1_0_0
-tsn_endpoint_ethernet_mac_block_v1_0_7=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_7
-v_hdmi_rx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v2_0_0
-v_uhdsdi_audio_v2_0_3=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_3
-axi_utils_v2_0_6=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_6
-sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1
-vid_edid_v1_0_0=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_0
-lte_dl_channel_encoder_v3_0_16=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v3_0_16
-axi_dma_v7_1_23=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_23
-emb_fifo_gen_v1_0_2=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_2
-c_mux_bus_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_6
-axi_mm2s_mapper_v1_1_21=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_21
-tcc_encoder_3gpp_v5_0_16=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_16
-av_pat_gen_v2_0_0=$RDI_DATADIR/xsim/ip/av_pat_gen_v2_0_0
-srio_gen2_v4_1_9=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_9
-fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6
-ten_gig_eth_mac_v15_1_9=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_9
-dfx_bitstream_monitor_v1_0_0=$RDI_DATADIR/xsim/ip/dfx_bitstream_monitor_v1_0_0
-displayport_v7_0_0=$RDI_DATADIR/xsim/ip/displayport_v7_0_0
-v_vcresampler_v1_1_0=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_1_0
-axis_dwidth_converter_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_sc_v1_1
-l_ethernet_v3_2_0=$RDI_DATADIR/xsim/ip/l_ethernet_v3_2_0
-xxv_ethernet_v3_3_0=$RDI_DATADIR/xsim/ip/xxv_ethernet_v3_3_0
-xpm=$RDI_DATADIR/xsim/ip/xpm
-nvme_tc_v2_0_0=$RDI_DATADIR/xsim/ip/nvme_tc_v2_0_0
-ieee802d3_200g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v1_0_11
-ats_switch_v1_0_3=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_3
-axi_data_fifo_v2_1_21=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_21
-zynq_ultra_ps_e_vip_v1_0_8=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_8
-fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4
-mutex_v2_1_11=$RDI_DATADIR/xsim/ip/mutex_v2_1_11
-lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0
-sim_rst_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_rst_gen_v1_0_2
-xbip_dsp48_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_6
-floating_point_v7_0_18=$RDI_DATADIR/xsim/ip/floating_point_v7_0_18
-v_smpte_uhdsdi_v1_0_8=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_8
-axis_vio_v1_0_2=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_2
-ieee802d3_rs_fec_v2_0_10=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_10
-lte_ul_channel_decoder_v4_0_17=$RDI_DATADIR/xsim/ip/lte_ul_channel_decoder_v4_0_17
-xbip_utils_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_10
-aes_v1_1_2=$RDI_DATADIR/xsim/ip/aes_v1_1_2
-div_gen_v5_1_17=$RDI_DATADIR/xsim/ip/div_gen_v5_1_17
-v_smpte_sdi_v3_0_9=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_9
-lte_dl_channel_encoder_v4_0_2=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v4_0_2
-tcc_decoder_3gppmm_v2_0_20=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_20
-axis_protocol_checker_v2_0_6=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_6
-fir_compiler_v5_2_6=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_6
-av_pat_gen_v1_0_1=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_1
-xbip_dsp48_multacc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_6
-advanced_io_wizard_v1_0_3=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_3
-v_tc_v6_1_13=$RDI_DATADIR/xsim/ip/v_tc_v6_1_13
-xpm_cdc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/xpm_cdc_gen_v1_0_0
-mailbox_v2_1_14=$RDI_DATADIR/xsim/ip/mailbox_v2_1_14
-uhdsdi_gt_v2_0_3=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_0_3
-lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2
-noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0
-v_vid_gt_bridge_v1_0_1=$RDI_DATADIR/xsim/ip/v_vid_gt_bridge_v1_0_1
-tri_mode_ethernet_mac_v9_0_17=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_17
-axis_ila_txns_cntr_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_txns_cntr_v1_0_0
-axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0
-emu_perf_common_v1_0=$RDI_DATADIR/xsim/ip/emu_perf_common_v1_0
-dbg_intf=$RDI_DATADIR/xsim/ip/dbg_intf
-clk_vip_v1_0_2=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_2
-axi_stream_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_stream_monitor_v1_1_0
-mipi_dsi_tx_ctrl_v1_0_7=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_7
-axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0
-debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1
-pc_cfr_v6_3_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_3_2
-gmii_to_rgmii_v4_1_0=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_1_0
-ernic_v2_0_0=$RDI_DATADIR/xsim/ip/ernic_v2_0_0
-accelerator_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/accelerator_monitor_v1_1_0
-xbip_dsp48_wrapper_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_4
-axi_pcie3_v3_0_13=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_13
-v_uhdsdi_audio_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_0_1
-v_dp_axi4s_vid_out_v1_0_1=$RDI_DATADIR/xsim/ip/v_dp_axi4s_vid_out_v1_0_1
-axi_mcdma_v1_1_3=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_3
-dist_mem_gen_v8_0_13=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_13
-sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1
-v_frmbuf_rd_v2_1_5=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_1_5
-v_frmbuf_wr_v2_1_5=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_1_5
-axi_crossbar_v2_1_23=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_23
-qdma_v4_0_2=$RDI_DATADIR/xsim/ip/qdma_v4_0_2
-v_hdmi_phy1_v1_0_2=$RDI_DATADIR/xsim/ip/v_hdmi_phy1_v1_0_2
-hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3
-v_smpte_uhdsdi_tx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_0
-xtlm_ipc_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ipc_v1_0
-ten_gig_eth_pcs_pma_v6_0_18=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_18
-interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4
-axi_protocol_checker_v2_0_8=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_8
-sync_ip=$RDI_DATADIR/xsim/ip/sync_ip
-util_reduced_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_4
-util_vector_logic_v2_0_1=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_1
-ba317=$RDI_DATADIR/xsim/ip/ba317
-xtlm_ap_ctrl_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ap_ctrl_v1_0
-high_speed_selectio_wiz_v3_5_2=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_5_2
-quadsgmii_v3_5_0=$RDI_DATADIR/xsim/ip/quadsgmii_v3_5_0
-vby1hs_v1_0_0=$RDI_DATADIR/xsim/ip/vby1hs_v1_0_0
-pc_cfr_v6_1_4=$RDI_DATADIR/xsim/ip/pc_cfr_v6_1_4
-vid_phy_controller_v2_2_7=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_7
-videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5
-fir_compiler_v7_2_15=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_15
-jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi
-hdmi_gt_controller_v1_0_3=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_3
-oran_radio_if_v1_1_0=$RDI_DATADIR/xsim/ip/oran_radio_if_v1_1_0
-v_deinterlacer_v5_1_0=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_1_0
-xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip
-trace_s2mm_v1_1_0=$RDI_DATADIR/xsim/ip/trace_s2mm_v1_1_0
-remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4
-lte_pucch_receiver_v2_0_18=$RDI_DATADIR/xsim/ip/lte_pucch_receiver_v2_0_18
-v_smpte_uhdsdi_rx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_0
-v_csc_v1_0_16=$RDI_DATADIR/xsim/ip/v_csc_v1_0_16
-ieee802d3_50g_rs_fec_v1_0_14=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_14
-emb_mem_gen_v1_0_3=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_3
-lib_srl_fifo_v1_0_2=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_2
-axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0
-mem_tg_v1_0_3=$RDI_DATADIR/xsim/ip/mem_tg_v1_0_3
-mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4
-emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5
-dds_compiler_v6_0_20=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_20
-icap_arb_v1_0_0=$RDI_DATADIR/xsim/ip/icap_arb_v1_0_0
-axi_interface_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_interface_monitor_v1_1_0
-i2s_transmitter_v1_0_4=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_4
-axi_hbicap_v1_0_3=$RDI_DATADIR/xsim/ip/axi_hbicap_v1_0_3
-v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0
-picxo=$RDI_DATADIR/xsim/ip/picxo
-axi_pmon_v1_0_0=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_0
-c_addsub_v12_0_14=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_14
-axi_uartlite_v2_0_26=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_26
-axi_fifo_mm_s_v4_2_4=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_2_4
-mammoth_transcode_v1_0_0=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_0
-tmr_voter_v1_0_3=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_3
-axi_interconnect_v1_7_18=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_18
-v_hscaler_v1_0_16=$RDI_DATADIR/xsim/ip/v_hscaler_v1_0_16
-v_vscaler_v1_0_16=$RDI_DATADIR/xsim/ip/v_vscaler_v1_0_16
-g709_rs_encoder_v2_2_7=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_7
-tmr_comparator_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_4
-mipi_dphy_v4_3_0=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_3_0
-prc_v1_3_4=$RDI_DATADIR/xsim/ip/prc_v1_3_4
-fifo_generator_v13_2_5=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_5
-iomodule_v3_1_6=$RDI_DATADIR/xsim/ip/iomodule_v3_1_6
-axi4stream_vip_v1_1_8=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_8
-v_deinterlacer_v5_0_16=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_0_16
-axi_remapper_tx_v1_0_0=$RDI_DATADIR/xsim/ip/axi_remapper_tx_v1_0_0
-axis_ila_pp_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_pp_v1_0_0
-pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0
-axi_vip_v1_1_8=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_8
-mipi_csi2_rx_ctrl_v1_0_8=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_8
-axi_datamover_v5_1_24=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_24
-v_gamma_lut_v1_1_0=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_1_0
-axis_itct_v1_0_0=$RDI_DATADIR/xsim/ip/axis_itct_v1_0_0
-axi_quad_spi_v3_2_21=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_21
-sim_trig_v1_0_4=$RDI_DATADIR/xsim/ip/sim_trig_v1_0_4
-axis_combiner_v1_1_20=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_20
-displayport_v9_0_3=$RDI_DATADIR/xsim/ip/displayport_v9_0_3
-blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6
-sim_clk_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_2
-v_dual_splitter_v1_0_9=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_9
-v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0
-compact_gt_v1_0_8=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_8
-zynq_ultra_ps_e_v3_2_6=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_2_6
-axi_tlm_ext_v1_0=$RDI_DATADIR/xsim/ip/axi_tlm_ext_v1_0
-xhmc_v1_0_12=$RDI_DATADIR/xsim/ip/xhmc_v1_0_12
-lib_fifo_v1_0_14=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_14
-cpri_v8_11_5=$RDI_DATADIR/xsim/ip/cpri_v8_11_5
-proc_sys_reset_v5_0_13=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_13
-axis_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_0
-tsn_temac_v1_0_5=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_5
-video_frame_crc_v1_0_3=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_3
-axi_amm_bridge_v1_0_12=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_12
-xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2
-qdriv_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/qdriv_pl_phy_v1_0_0
-floating_point_v7_1_11=$RDI_DATADIR/xsim/ip/floating_point_v7_1_11
-axi_tft_v2_0_23=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_23
-noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0
-lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0
-pc_cfr_v6_0_8=$RDI_DATADIR/xsim/ip/pc_cfr_v6_0_8
-ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0
-v_demosaic_v1_0_8=$RDI_DATADIR/xsim/ip/v_demosaic_v1_0_8
-roe_framer_v3_0_1=$RDI_DATADIR/xsim/ip/roe_framer_v3_0_1
-c_accum_v12_0_14=$RDI_DATADIR/xsim/ip/c_accum_v12_0_14
-pc_cfr_v6_2_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_2_2
-xbip_dsp48_macro_v3_0_18=$RDI_DATADIR/xsim/ip/xbip_dsp48_macro_v3_0_18
-axis_ila_adv_trig_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_adv_trig_v1_0_0
-axi_usb2_device_v5_0_23=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_23
-axi_hwicap_v3_0_26=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_26
-axis_mu_v1_0_0=$RDI_DATADIR/xsim/ip/axis_mu_v1_0_0
-audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0
-axis_dbg_sync_v1_0_0=$RDI_DATADIR/xsim/ip/axis_dbg_sync_v1_0_0
-microblaze_v10_0_7=$RDI_DATADIR/xsim/ip/microblaze_v10_0_7
-sd_fec_v1_1_6=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_6
-uhdsdi_gt_v1_0_3=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v1_0_3
-bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0
-xfft_v9_0_19=$RDI_DATADIR/xsim/ip/xfft_v9_0_19
-etrnic_v1_0_4=$RDI_DATADIR/xsim/ip/etrnic_v1_0_4
-mpegtsmux_v1_1_0=$RDI_DATADIR/xsim/ip/mpegtsmux_v1_1_0
-lmb_v10_v3_0_11=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_11
-dft_v4_0_16=$RDI_DATADIR/xsim/ip/dft_v4_0_16
-axi_mcdma_v1_0_8=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_0_8
-ibert_lib_v1_0_7=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_7
-sem_ultra_v3_1_16=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_16
-pcie_axi4lite_tap_v1_0_1=$RDI_DATADIR/xsim/ip/pcie_axi4lite_tap_v1_0_1
-cmac_usplus_v3_1_2=$RDI_DATADIR/xsim/ip/cmac_usplus_v3_1_2
-axi_bram_ctrl_v4_0_14=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_14
-ieee802d3_400g_rs_fec_v2_0_2=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v2_0_2
-switch_core_top_v1_0_8=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_8
-v_multi_scaler_v1_0_4=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_0_4
-v_hdmi_tx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_0
-tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6
-convolution_v9_0_15=$RDI_DATADIR/xsim/ip/convolution_v9_0_15
-iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0
-fec_5g_common_v1_1_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_1
-axis_subset_converter_v1_1_22=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_22
-axi_msg_v1_0_6=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_6
-axis_mem_v1_0_0=$RDI_DATADIR/xsim/ip/axis_mem_v1_0_0
-aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0
-axi_fifo_mm_s_v4_1_19=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_1_19
-ai_pl=$RDI_DATADIR/xsim/ip/ai_pl
-xbip_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_6
-c_reg_fd_v12_0_6=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_6
-shell_utils_msp432_bsl_crc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_0
-xdma_v4_1_8=$RDI_DATADIR/xsim/ip/xdma_v4_1_8
-hdcp22_cipher_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_3
-microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4
-v_csc_v1_1_0=$RDI_DATADIR/xsim/ip/v_csc_v1_1_0
-vfb_v1_0_16=$RDI_DATADIR/xsim/ip/vfb_v1_0_16
-axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub
-axi_firewall_v1_0_10=$RDI_DATADIR/xsim/ip/axi_firewall_v1_0_10
-noc_na_v1_0_0=$RDI_DATADIR/xsim/ip/noc_na_v1_0_0
-cmpy_v6_0_19=$RDI_DATADIR/xsim/ip/cmpy_v6_0_19
-mrmac_v1_3_0=$RDI_DATADIR/xsim/ip/mrmac_v1_3_0
-ddr4_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_0
-bs_switch_v1_0_0=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_0
-v_uhdsdi_vidgen_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_1
-an_lt_v1_0_1=$RDI_DATADIR/xsim/ip/an_lt_v1_0_1

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_stub.v

@@ -1,10 +1,10 @@
 // Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
-// Date        : Tue Aug 29 17:27:14 2023
+// Date        : Tue Aug 29 17:27:13 2023
 // Host        : DESKTOP-RMARCDV running 64-bit major release  (build 9200)
-// Command     : write_verilog -force -mode synth_stub
-//               c:/Users/Stepan/Desktop/4portCompact/S5443Current/S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_stub.v
+// Command     : write_verilog -force -mode synth_stub -rename_top MeasDataFifo -prefix
+//               MeasDataFifo_ MeasDataFifo_stub.v
 // Design      : MeasDataFifo
 // Purpose     : Stub declaration of top-level module interface
 // Device      : xc7s25csga324-2

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_stub.vhdl

@@ -1,10 +1,10 @@
 -- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+-- Date        : Tue Aug 29 17:27:13 2023
 -- Host        : DESKTOP-RMARCDV running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub -rename_top MeasDataFifo -prefix
+--               MeasDataFifo_ MeasDataFifo_stub.vhdl
 -- Design      : MeasDataFifo
 -- Purpose     : Stub declaration of top-level module interface
 -- Device      : xc7s25csga324-2

S5443_M/S5443.srcs/sources_1/new/InternalDsp/InternalDsp.v

@@ -164,6 +164,9 @@ module InternalDsp
 	
 	wire	[17:0]	sinSecondTone	=	secondToneSinCosValues [35:18];			//выделяем из вычитаных данных, значение Cos
 	wire	[17:0]	cosSecondTone	=	secondToneSinCosValues [17:0];			//выделяем из вычитаных данных, значение Sin
+	
+	reg		startMeasDspR;
+	wire	startMeasDspPos	=	(!startMeasDspR&StartMeasDsp_i);
 //================================================================================
 //  ASSIGNMENTS
 
@@ -201,7 +204,7 @@ module InternalDsp
 	assign	MeasDataRdy_o	=	&resultValBus;
 	assign	EndMeas_o		=	stopMeas;
 	
-	assign	NcoCos_o	=	ncoCosFirstTone;
+	assign	NcoCos_o	=	ncoSinSecondTone;
 	assign	NcoSin_o	=	ncoSinSecondTone;
 	assign	MeasWind_o	=	measWind;
 	
@@ -222,6 +225,7 @@ module InternalDsp
 
 always	@(posedge	Clk_i)	begin
 	if	(!Rst_i)	begin
+		startMeasDspR	<=	StartMeasDsp_i;
 		if	(!StartMeas_i)	begin
 			measCtrlReg			<=	MeasCtrl_i;
 			ifFtwLReg			<=	IfFtwL_i;
@@ -239,6 +243,7 @@ always	@(posedge	Clk_i)	begin
 		filterCorrCoefHReg	<=	0;
 		measNumReg			<=	0;
 		windPointsNumReg	<=	0;
+		startMeasDspR		<=	0;
 	end 
 end
 
@@ -327,7 +332,7 @@ ncoFirstTone
 (
 	.Clk_i		(Clk_i),
 	// .Rst_i		(Rst_i|NcoRst_i),
-	.Rst_i		(Rst_i),
+	.Rst_i		(Rst_i|startMeasDspPos),
 	.Val_i		(1'b1),
 	// .PhaseInc_i	({ifFtwHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],ifFtwLReg}),
 	// .PhaseInc_i	(32'h40000000),
@@ -351,7 +356,7 @@ ncoSecondTone
 (
 	.Clk_i		(Clk_i),
 	// .Rst_i		(Rst_i|NcoRst_i),
-	.Rst_i		(Rst_i),
+	.Rst_i		(Rst_i|startMeasDspPos),
 	.Val_i		(1'b1),
 	// .PhaseInc_i	({ifFtwHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],ifFtwLReg}),
 	// .PhaseInc_i	(32'h31eb851e),
@@ -458,11 +463,11 @@ generate
 			.AverageNoizeLvl_i	(averageNoizeLvl),
 			.AdcData_i			(gatedAdcDataBus[g]),
 			.Wind_i				(wind),
-			// .NcoSin_i			(ncoSinFirstTone),
-			// .NcoCos_i			(ncoCosFirstTone),
+			.NcoSin_i			(ncoSinFirstTone),
+			.NcoCos_i			(ncoCosFirstTone),
 			
-			.NcoSin_i			(sinFirstTone),
-			.NcoCos_i			(cosFirstTone),	
+			// .NcoSin_i			(sinFirstTone),
+			// .NcoCos_i			(cosFirstTone),	
 			.NormCoef_i			(windNormCoef),
 
 			.CorrResultIm_o		(resultImBus[g]),
@@ -492,11 +497,11 @@ generate
 			.AverageNoizeLvl_i	(averageNoizeLvl),
 			.AdcData_i			(gatedAdcDataBus[g]),
 			.Wind_i				(wind),
-			// .NcoSin_i			(ncoSinSecondTone),
-			// .NcoCos_i			(ncoCosSecondTone),	
+			.NcoSin_i			(ncoSinSecondTone),
+			.NcoCos_i			(ncoCosSecondTone),	
 			
-			.NcoSin_i			(sinSecondTone),
-			.NcoCos_i			(cosSecondTone),	
+			// .NcoSin_i			(sinSecondTone),
+			// .NcoCos_i			(cosSecondTone),	
 			.NormCoef_i			(windNormCoef),
 
 			.CorrResultIm_o		(resultImBus[g+2]),

S5443_M/min_area_pfile.tmp

@@ -0,0 +1,21 @@
+10000
+1
+3
+4
+1
+0
+0
+9
+8
+8
+8
+8
+256
+256
+256
+256
+0
+0
+0
+0
+0