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@@ -32,7 +32,7 @@ module OscDataFormer
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reg oscDataBusValReg;
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reg oscDataBusValRegReg;
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- reg [DataValCycles-1:0] cycleCnt;
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+ reg [4-1:0] cycleCnt;
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reg [31:0] wrDataCnt;
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wire wrDone = OscWind_i? (wrDataCnt == MeasNum_i):1'b0;
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@@ -81,12 +81,9 @@ module OscDataFormer
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always @(posedge Clk_i) begin
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if (!Rst_i) begin
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if (OscWind_i) begin
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- if (cycleCnt != DataValCycles-1 & AdcDataVal_i) begin
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+ if (AdcDataVal_i) begin
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cycleCnt <= cycleCnt+4'd1;
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end
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- if (cycleCnt == DataValCycles-1) begin
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- cycleCnt <= 4'd0;
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- end
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end else begin
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cycleCnt <= 0;
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end
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@@ -127,7 +124,7 @@ module OscDataFormer
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always @(posedge Clk_i) begin
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if (!Rst_i) begin
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- if (cycleCnt == DataValCycles-1) begin
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+ if (cycleCnt == DataValCycles-1 & AdcDataVal_i) begin
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oscDataBusValReg <= 1'b1;
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end else begin
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oscDataBusValReg <= 1'b0;
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