Ip MeasDataFifo распакована из контейнера.

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/README.txt

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+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required
+#             to simulate the design for a simulator, the directory structure
+#             and the generated exported files.
+#
+################################################################################
+
+1. Simulate Design
+
+To simulate design, cd to the simulator directory and execute the script.
+
+For example:-
+
+% cd questa
+% ./top.sh
+
+The export simulation flow requires the Xilinx pre-compiled simulation library
+components for the target simulator. These components are referred using the
+'-lib_map_path' switch. If this switch is specified, then the export simulation
+will automatically set this library path in the generated script and update,
+copy the simulator setup file(s) in the exported directory.
+
+If '-lib_map_path' is not specified, then the pre-compiled simulation library
+information will not be included in the exported scripts and that may cause
+simulation errors when running this script. Alternatively, you can provide the
+library information using this switch while executing the generated script.
+
+For example:-
+
+% ./top.sh -lib_map_path /design/questa/clibs
+
+Please refer to the generated script header 'Prerequisite' section for more details.
+
+2. Directory Structure
+
+By default, if the -directory switch is not specified, export_simulation will
+create the following directory structure:-
+
+<current_working_directory>/export_sim/<simulator>
+
+For example, if the current working directory is /tmp/test, export_simulation
+will create the following directory path:-
+
+/tmp/test/export_sim/questa
+
+If -directory switch is specified, export_simulation will create a simulator
+sub-directory under the specified directory path.
+
+For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
+command will create the following directory:-
+
+/tmp/test/my_test_area/func_sim/questa
+
+By default, if -simulator is not specified, export_simulation will create a
+simulator sub-directory for each simulator and export the files for each simulator
+in this sub-directory respectively.
+
+IMPORTANT: Please note that the simulation library path must be specified manually
+in the generated script for the respective simulator. Please refer to the generated
+script header 'Prerequisite' section for more details.
+
+3. Exported script and files
+
+Export simulation will create the driver shell script, setup files and copy the
+design sources in the output directory path.
+
+By default, when the -script_name switch is not specified, export_simulation will
+create the following script name:-
+
+<simulation_top>.sh  (Unix)
+When exporting the files for an IP using the -of_objects switch, export_simulation
+will create the following script name:-
+
+<ip-name>.sh  (Unix)
+Export simulation will create the setup files for the target simulator specified
+with the -simulator switch.
+
+For example, if the target simulator is "ies", export_simulation will create the
+'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
+file.
+

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/activehdl/MeasDataFifo.sh

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+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : MeasDataFifo.sh
+# Simulator   : Aldec Active-HDL Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Wed May 03 12:02:59 +0700 2023
+# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: MeasDataFifo.sh [-help]
+# usage: MeasDataFifo.sh [-lib_map_path]
+# usage: MeasDataFifo.sh [-noclean_files]
+# usage: MeasDataFifo.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'MeasDataFifo.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "MeasDataFifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./MeasDataFifo.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="C:/Users/Stepan/Desktop/4portCompact/S5443Current/S5443_M/S5443.cache/compile_simlib/activehdl"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./MeasDataFifo.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: MeasDataFifo.sh [-help]\n\
+Usage: MeasDataFifo.sh [-lib_map_path]\n\
+Usage: MeasDataFifo.sh [-reset_run]\n\
+Usage: MeasDataFifo.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/activehdl/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Wed May 03 12:02:59 +0700 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./MeasDataFifo.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './MeasDataFifo.sh' script.
+
+./MeasDataFifo.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./MeasDataFifo.sh -noclean_files
+
+For more information on the script, please type './MeasDataFifo.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/activehdl/compile.do

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+vlib work
+vlib activehdl
+
+vlib activehdl/xpm
+vlib activehdl/xil_defaultlib
+
+vmap xpm activehdl/xpm
+vmap xil_defaultlib activehdl/xil_defaultlib
+
+vlog -work xpm  -sv2k12 \
+"C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work xil_defaultlib  -v2k5 \
+"../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/activehdl/file_info.txt

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+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+MeasDataFifo_sim_netlist.v,verilog,xil_defaultlib,../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/activehdl/glbl.v

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+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/activehdl/simulate.do

@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+MeasDataFifo -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.MeasDataFifo xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {MeasDataFifo.udo}
+
+run -all
+
+endsim
+
+quit -force

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/activehdl/wave.do

@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/ies/MeasDataFifo.sh

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+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : MeasDataFifo.sh
+# Simulator   : Cadence Incisive Enterprise Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Wed May 03 12:02:59 +0700 2023
+# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: MeasDataFifo.sh [-help]
+# usage: MeasDataFifo.sh [-lib_map_path]
+# usage: MeasDataFifo.sh [-noclean_files]
+# usage: MeasDataFifo.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'MeasDataFifo.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xpm xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="ies_lib"
+
+# Script info
+echo -e "MeasDataFifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  irun $irun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.MeasDataFifo \
+       -f run.f \
+       -top glbl \
+       glbl.v
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./MeasDataFifo.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./MeasDataFifo.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: MeasDataFifo.sh [-help]\n\
+Usage: MeasDataFifo.sh [-lib_map_path]\n\
+Usage: MeasDataFifo.sh [-reset_run]\n\
+Usage: MeasDataFifo.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/ies/README.txt

@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Wed May 03 12:02:59 +0700 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./MeasDataFifo.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './MeasDataFifo.sh' script.
+
+./MeasDataFifo.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./MeasDataFifo.sh -noclean_files
+
+For more information on the script, please type './MeasDataFifo.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/ies/file_info.txt

@@ -0,0 +1,5 @@
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+MeasDataFifo_sim_netlist.v,verilog,xil_defaultlib,../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/ies/glbl.v

@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/ies/run.f

@@ -0,0 +1,14 @@
+-makelib ies_lib/xpm -sv \
+  "C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib ies_lib/xpm \
+  "C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  glbl.v
+-endlib
+

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/modelsim/MeasDataFifo.sh

@@ -0,0 +1,167 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : MeasDataFifo.sh
+# Simulator   : Mentor Graphics ModelSim Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Wed May 03 12:02:59 +0700 2023
+# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: MeasDataFifo.sh [-help]
+# usage: MeasDataFifo.sh [-lib_map_path]
+# usage: MeasDataFifo.sh [-noclean_files]
+# usage: MeasDataFifo.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'MeasDataFifo.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "MeasDataFifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim  -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./MeasDataFifo.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="C:/Users/Stepan/Desktop/4portCompact/S5443Current/S5443_M/S5443.cache/compile_simlib/modelsim"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="modelsim_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./MeasDataFifo.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: MeasDataFifo.sh [-help]\n\
+Usage: MeasDataFifo.sh [-lib_map_path]\n\
+Usage: MeasDataFifo.sh [-reset_run]\n\
+Usage: MeasDataFifo.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/modelsim/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Wed May 03 12:02:59 +0700 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./MeasDataFifo.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './MeasDataFifo.sh' script.
+
+./MeasDataFifo.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./MeasDataFifo.sh -noclean_files
+
+For more information on the script, please type './MeasDataFifo.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/modelsim/compile.do

@@ -0,0 +1,14 @@
+vlib modelsim_lib/work
+vlib modelsim_lib/msim
+
+vlib modelsim_lib/msim/xil_defaultlib
+
+vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+
+vlog -work xil_defaultlib  -incr \
+"../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v" \
+
+
+vlog -work xil_defaultlib \
+"glbl.v"
+

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/modelsim/file_info.txt

@@ -0,0 +1,2 @@
+MeasDataFifo_sim_netlist.v,verilog,xil_defaultlib,../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/modelsim/glbl.v

@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/modelsim/simulate.do

@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -voptargs="+acc" -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.MeasDataFifo xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {MeasDataFifo.udo}
+
+run -all
+
+quit -force

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/modelsim/wave.do

@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/questa/MeasDataFifo.sh

@@ -0,0 +1,174 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : MeasDataFifo.sh
+# Simulator   : Mentor Graphics Questa Advanced Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Wed May 03 12:02:59 +0700 2023
+# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: MeasDataFifo.sh [-help]
+# usage: MeasDataFifo.sh [-lib_map_path]
+# usage: MeasDataFifo.sh [-noclean_files]
+# usage: MeasDataFifo.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'MeasDataFifo.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "MeasDataFifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  source elaborate.do 2>&1 | tee -a elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim  -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./MeasDataFifo.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="C:/Users/Stepan/Desktop/4portCompact/S5443Current/S5443_M/S5443.cache/compile_simlib/questa"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="questa_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./MeasDataFifo.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: MeasDataFifo.sh [-help]\n\
+Usage: MeasDataFifo.sh [-lib_map_path]\n\
+Usage: MeasDataFifo.sh [-reset_run]\n\
+Usage: MeasDataFifo.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/questa/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Wed May 03 12:02:59 +0700 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./MeasDataFifo.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './MeasDataFifo.sh' script.
+
+./MeasDataFifo.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./MeasDataFifo.sh -noclean_files
+
+For more information on the script, please type './MeasDataFifo.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/questa/compile.do

@@ -0,0 +1,22 @@
+vlib questa_lib/work
+vlib questa_lib/msim
+
+vlib questa_lib/msim/xpm
+vlib questa_lib/msim/xil_defaultlib
+
+vmap xpm questa_lib/msim/xpm
+vmap xil_defaultlib questa_lib/msim/xil_defaultlib
+
+vlog -work xpm  -sv \
+"C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm  -93 \
+"C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work xil_defaultlib  \
+"../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/questa/elaborate.do

@@ -0,0 +1 @@
+vopt +acc=npr -l elaborate.log -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.MeasDataFifo xil_defaultlib.glbl -o MeasDataFifo_opt

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/questa/file_info.txt

@@ -0,0 +1,5 @@
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+MeasDataFifo_sim_netlist.v,verilog,xil_defaultlib,../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/questa/glbl.v

@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/questa/simulate.do

@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -lib xil_defaultlib MeasDataFifo_opt
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {MeasDataFifo.udo}
+
+run -all
+
+quit -force

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/questa/wave.do

@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/riviera/MeasDataFifo.sh

@@ -0,0 +1,153 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : MeasDataFifo.sh
+# Simulator   : Aldec Riviera-PRO Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Wed May 03 12:02:59 +0700 2023
+# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: MeasDataFifo.sh [-help]
+# usage: MeasDataFifo.sh [-lib_map_path]
+# usage: MeasDataFifo.sh [-noclean_files]
+# usage: MeasDataFifo.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'MeasDataFifo.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "MeasDataFifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./MeasDataFifo.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="C:/Users/Stepan/Desktop/4portCompact/S5443Current/S5443_M/S5443.cache/compile_simlib/riviera"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./MeasDataFifo.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: MeasDataFifo.sh [-help]\n\
+Usage: MeasDataFifo.sh [-lib_map_path]\n\
+Usage: MeasDataFifo.sh [-reset_run]\n\
+Usage: MeasDataFifo.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/riviera/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Wed May 03 12:02:59 +0700 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./MeasDataFifo.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './MeasDataFifo.sh' script.
+
+./MeasDataFifo.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./MeasDataFifo.sh -noclean_files
+
+For more information on the script, please type './MeasDataFifo.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/riviera/compile.do

@@ -0,0 +1,22 @@
+vlib work
+vlib riviera
+
+vlib riviera/xpm
+vlib riviera/xil_defaultlib
+
+vmap xpm riviera/xpm
+vmap xil_defaultlib riviera/xil_defaultlib
+
+vlog -work xpm  -sv2k12 \
+"C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work xil_defaultlib  -v2k5 \
+"../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/riviera/file_info.txt

@@ -0,0 +1,5 @@
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+MeasDataFifo_sim_netlist.v,verilog,xil_defaultlib,../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/riviera/glbl.v

@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/riviera/simulate.do

@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+MeasDataFifo -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.MeasDataFifo xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {MeasDataFifo.udo}
+
+run -all
+
+endsim
+
+quit -force

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/riviera/wave.do

@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/vcs/MeasDataFifo.sh

@@ -0,0 +1,229 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : MeasDataFifo.sh
+# Simulator   : Synopsys Verilog Compiler Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Wed May 03 12:02:59 +0700 2023
+# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: MeasDataFifo.sh [-help]
+# usage: MeasDataFifo.sh [-lib_map_path]
+# usage: MeasDataFifo.sh [-noclean_files]
+# usage: MeasDataFifo.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'MeasDataFifo.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Command line options
+vlogan_opts="-full64"
+vhdlan_opts="-full64"
+vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
+vcs_sim_opts="-ucli -licqueue -l simulate.log"
+
+# Design libraries
+design_libs=(xpm xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="vcs_lib"
+
+# Script info
+echo -e "MeasDataFifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  vlogan -work xpm $vlogan_opts -sverilog \
+    "C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+    "C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vhdlan -work xpm $vhdlan_opts \
+    "C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k \
+    "$ref_dir/../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v" \
+  2>&1 | tee -a vlogan.log
+
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k \
+    glbl.v \
+  2>&1 | tee -a vlogan.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  vcs $vcs_elab_opts xil_defaultlib.MeasDataFifo xil_defaultlib.glbl -o MeasDataFifo_simv
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  ./MeasDataFifo_simv $vcs_sim_opts -do simulate.do
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./MeasDataFifo.sh -help\" for more information)\n"
+        exit 1
+      fi
+      create_lib_mappings $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+      create_lib_mappings $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Define design library mappings
+create_lib_mappings()
+{
+  file="synopsys_sim.setup"
+  if [[ -e $file ]]; then
+    if [[ ($1 == "") ]]; then
+      return
+    else
+      rm -rf $file
+    fi
+  fi
+
+  touch $file
+
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    mapping="$lib:$sim_lib_dir/$lib"
+    echo $mapping >> $file
+  done
+
+  if [[ ($lib_map_path != "") ]]; then
+    incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
+    echo $incl_ref >> $file
+  fi
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ucli.key MeasDataFifo_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc MeasDataFifo_simv.daidir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./MeasDataFifo.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: MeasDataFifo.sh [-help]\n\
+Usage: MeasDataFifo.sh [-lib_map_path]\n\
+Usage: MeasDataFifo.sh [-reset_run]\n\
+Usage: MeasDataFifo.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/vcs/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Wed May 03 12:02:59 +0700 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./MeasDataFifo.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './MeasDataFifo.sh' script.
+
+./MeasDataFifo.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./MeasDataFifo.sh -noclean_files
+
+For more information on the script, please type './MeasDataFifo.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/vcs/file_info.txt

@@ -0,0 +1,5 @@
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+MeasDataFifo_sim_netlist.v,verilog,xil_defaultlib,../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/vcs/glbl.v

@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/vcs/simulate.do

@@ -0,0 +1,2 @@
+run
+quit

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xcelium/MeasDataFifo.sh

@@ -0,0 +1,175 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : MeasDataFifo.sh
+# Simulator   : Cadence Xcelium Parallel Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Wed May 03 12:02:59 +0700 2023
+# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: MeasDataFifo.sh [-help]
+# usage: MeasDataFifo.sh [-lib_map_path]
+# usage: MeasDataFifo.sh [-noclean_files]
+# usage: MeasDataFifo.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'MeasDataFifo.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xpm xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="xcelium_lib"
+
+# Script info
+echo -e "MeasDataFifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  xrun $xrun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.MeasDataFifo \
+       -f run.f \
+       -top glbl \
+       glbl.v
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./MeasDataFifo.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./MeasDataFifo.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: MeasDataFifo.sh [-help]\n\
+Usage: MeasDataFifo.sh [-lib_map_path]\n\
+Usage: MeasDataFifo.sh [-reset_run]\n\
+Usage: MeasDataFifo.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xcelium/README.txt

@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Wed May 03 12:02:59 +0700 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./MeasDataFifo.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './MeasDataFifo.sh' script.
+
+./MeasDataFifo.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./MeasDataFifo.sh -noclean_files
+
+For more information on the script, please type './MeasDataFifo.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xcelium/file_info.txt

@@ -0,0 +1,5 @@
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+MeasDataFifo_sim_netlist.v,verilog,xil_defaultlib,../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xcelium/glbl.v

@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xcelium/run.f

@@ -0,0 +1,14 @@
+-makelib xcelium_lib/xpm -sv \
+  "C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib xcelium_lib/xpm \
+  "C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  glbl.v
+-endlib
+

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xsim/MeasDataFifo.sh

@@ -0,0 +1,212 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# Filename    : MeasDataFifo.sh
+# Simulator   : Xilinx Vivado Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Wed May 03 12:02:59 +0700 2023
+# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
+#
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: MeasDataFifo.sh [-help]
+# usage: MeasDataFifo.sh [-lib_map_path]
+# usage: MeasDataFifo.sh [-noclean_files]
+# usage: MeasDataFifo.sh [-reset_run]
+#
+#*********************************************************************************************************
+
+# Command line options
+xv_boost_lib_path=C:/Xilinx/Vivado/2020.2/tps/boost_1_64_0
+xvlog_opts="--relax"
+
+
+# Script info
+echo -e "MeasDataFifo.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot MeasDataFifo xil_defaultlib.MeasDataFifo xil_defaultlib.glbl -log elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  xsim MeasDataFifo -key {Behavioral:sim_1:Functional:MeasDataFifo} -tclbatch cmd.tcl -log simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./MeasDataFifo.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy xsim.ini file
+copy_setup_file()
+{
+  file="xsim.ini"
+  lib_map_path="C:/Xilinx/Vivado/2020.2/data/xsim"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      cp $src_file .
+    fi
+
+    # Map local design libraries to xsim.ini
+    map_local_libs
+
+  fi
+}
+
+# Map local design libraries
+map_local_libs()
+{
+  updated_mappings=()
+  local_mappings=()
+
+  # Local design libraries
+  local_libs=()
+
+  if [[ 0 == ${#local_libs[@]} ]]; then
+    return
+  fi
+
+  file="xsim.ini"
+  file_backup="xsim.ini.bak"
+
+  if [[ -e $file ]]; then
+    rm -f $file_backup
+    # Create a backup copy of the xsim.ini file
+    cp $file $file_backup
+    # Read libraries from backup file and search in local library collection
+    while read -r line
+    do
+      IN=$line
+      # Split mapping entry with '=' delimiter to fetch library name and mapping
+      read lib_name mapping <<<$(IFS="="; echo $IN)
+      # If local library found, then construct the local mapping and add to local mapping collection
+      if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        local_mappings+=("$lib_name")
+      fi
+      # Add to updated library mapping collection
+      updated_mappings+=("$line")
+    done < "$file_backup"
+    # Append local libraries not found originally from xsim.ini
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        updated_mappings+=("$line")
+      fi
+    done
+    # Write updated mappings in xsim.ini
+    rm -f $file
+    for (( i=0; i<${#updated_mappings[*]}; i++ )); do
+      lib_name="${updated_mappings[i]}"
+      echo $lib_name >> $file
+    done
+  else
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      mapping="$lib_name=xsim.dir/$lib_name"
+      echo $mapping >> $file
+    done
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb MeasDataFifo.wdb xsim.dir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./MeasDataFifo.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: MeasDataFifo.sh [-help]\n\
+Usage: MeasDataFifo.sh [-lib_map_path]\n\
+Usage: MeasDataFifo.sh [-reset_run]\n\
+Usage: MeasDataFifo.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xsim/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2020.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Wed May 03 12:02:59 +0700 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./MeasDataFifo.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './MeasDataFifo.sh' script.
+
+./MeasDataFifo.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./MeasDataFifo.sh -noclean_files
+
+For more information on the script, please type './MeasDataFifo.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xsim/cmd.tcl

@@ -0,0 +1,12 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run -all
+quit

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xsim/elab.opt

@@ -0,0 +1 @@
+--relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot MeasDataFifo xil_defaultlib.MeasDataFifo xil_defaultlib.glbl -log elaborate.log

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xsim/file_info.txt

@@ -0,0 +1,2 @@
+MeasDataFifo_sim_netlist.v,verilog,xil_defaultlib,../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xsim/glbl.v

@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xsim/vlog.prj

@@ -0,0 +1,6 @@
+verilog xil_defaultlib  \
+"../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v" \
+
+verilog xil_defaultlib "glbl.v"
+
+nosort

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xsim/xsim.ini

@@ -0,0 +1,497 @@
+std=$RDI_DATADIR/xsim/vhdl/std
+ieee=$RDI_DATADIR/xsim/vhdl/ieee
+ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed
+vl=$RDI_DATADIR/xsim/vhdl/vl
+synopsys=$RDI_DATADIR/xsim/vhdl/synopsys
+uvm=$RDI_DATADIR/xsim/system_verilog/uvm
+secureip=$RDI_DATADIR/xsim/verilog/secureip
+unisim=$RDI_DATADIR/xsim/vhdl/unisim
+unimacro=$RDI_DATADIR/xsim/vhdl/unimacro
+unifast=$RDI_DATADIR/xsim/vhdl/unifast
+unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver
+unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver
+unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver
+simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver
+axi_clock_converter_v2_1_21=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_21
+axis_dbg_stub_v1_0_0=$RDI_DATADIR/xsim/ip/axis_dbg_stub_v1_0_0
+xlconcat_v2_1_4=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_4
+lte_fft_v2_0_20=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_20
+axi_remapper_rx_v1_0_0=$RDI_DATADIR/xsim/ip/axi_remapper_rx_v1_0_0
+noc_ncrb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_ncrb_v1_0_0
+lut_buffer_v1_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v1_0_0
+system_cache_v5_0_3=$RDI_DATADIR/xsim/ip/system_cache_v5_0_3
+rld3_pl_v1_0_4=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_4
+ernic_v3_0_0=$RDI_DATADIR/xsim/ip/ernic_v3_0_0
+xfft_v9_1_5=$RDI_DATADIR/xsim/ip/xfft_v9_1_5
+pr_axi_shutdown_manager_v1_0_2=$RDI_DATADIR/xsim/ip/pr_axi_shutdown_manager_v1_0_2
+axi_dwidth_converter_v2_1_22=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_22
+shell_utils_addr_remap_v1_0_1=$RDI_DATADIR/xsim/ip/shell_utils_addr_remap_v1_0_1
+v_hdmi_rx1_v1_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx1_v1_0_0
+ieee802d3_rs_fec_v1_0_18=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v1_0_18
+mult_gen_v12_0_16=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_16
+processing_system7_v5_5_6=$RDI_DATADIR/xsim/ip/processing_system7_v5_5_6
+noc_nps4_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps4_v1_0_0
+axis_switch_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_switch_sc_v1_1
+lib_bmg_v1_0_13=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_13
+xbip_bram18k_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_6
+cordic_v6_0_16=$RDI_DATADIR/xsim/ip/cordic_v6_0_16
+tmr_sem_v1_0_15=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_15
+axis_dwidth_converter_v1_1_21=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_21
+xlslice_v1_0_2=$RDI_DATADIR/xsim/ip/xlslice_v1_0_2
+xtlm=$RDI_DATADIR/xsim/ip/xtlm
+rs_encoder_v9_0_16=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_16
+axis_ila_ct_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_ct_v1_0_0
+v_uhdsdi_audio_v1_1_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_1_0
+v_tpg_v8_1_0=$RDI_DATADIR/xsim/ip/v_tpg_v8_1_0
+c_counter_binary_v12_0_14=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_14
+common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1
+axis_switch_v1_1_22=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_22
+rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1
+rs_toolbox_v9_0_8=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_8
+v_letterbox_v1_1_0=$RDI_DATADIR/xsim/ip/v_letterbox_v1_1_0
+high_speed_selectio_wiz_v3_6_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_6_1
+axi_chip2chip_v5_0_9=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_9
+v_demosaic_v1_1_0=$RDI_DATADIR/xsim/ip/v_demosaic_v1_1_0
+v_multi_scaler_v1_2_0=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_2_0
+ieee802d3_200g_rs_fec_v2_0_0=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v2_0_0
+axi_memory_init_v1_0_3=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_3
+high_speed_selectio_wiz_v3_4_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_4_1
+duc_ddc_compiler_v3_0_15=$RDI_DATADIR/xsim/ip/duc_ddc_compiler_v3_0_15
+ai_noc=$RDI_DATADIR/xsim/ip/ai_noc
+bs_mux_v1_0_0=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_0
+ecc_v2_0_13=$RDI_DATADIR/xsim/ip/ecc_v2_0_13
+axis_interconnect_v1_1_18=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_18
+cmac_v2_6_2=$RDI_DATADIR/xsim/ip/cmac_v2_6_2
+high_speed_selectio_wiz_v3_3_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_3_1
+axi_pcie_v2_9_4=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_4
+rld3_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_0
+sim_qdma_sc_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_sc_v1_0
+v_axi4s_remap_v1_0_14=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_14
+system_cache_v4_0_6=$RDI_DATADIR/xsim/ip/system_cache_v4_0_6
+axi_vfifo_ctrl_v2_0_24=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_24
+ernic_v1_0_2=$RDI_DATADIR/xsim/ip/ernic_v1_0_2
+multi_channel_25g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_11
+oddr_v1_0_2=$RDI_DATADIR/xsim/ip/oddr_v1_0_2
+mem_pl_v1_0_0=$RDI_DATADIR/xsim/ip/mem_pl_v1_0_0
+fit_timer_v2_0_10=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_10
+v_axi4s_vid_out_v4_0_11=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_11
+v_letterbox_v1_0_16=$RDI_DATADIR/xsim/ip/v_letterbox_v1_0_16
+clk_gen_sim_v1_0_0=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_0
+lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0
+axi_traffic_gen_v2_0_23=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v2_0_23
+gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux
+lte_rach_detector_v3_1_8=$RDI_DATADIR/xsim/ip/lte_rach_detector_v3_1_8
+lte_fft_v2_1_3=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_3
+g709_rs_decoder_v2_2_9=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_9
+lte_3gpp_channel_estimator_v2_0_17=$RDI_DATADIR/xsim/ip/lte_3gpp_channel_estimator_v2_0_17
+g975_efec_i4_v1_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_18
+stm_v1_0_0=$RDI_DATADIR/xsim/ip/stm_v1_0_0
+xbip_pipe_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_6
+axi_perf_mon_v5_0_24=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_24
+axi_timebase_wdt_v3_0_14=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_14
+fec_5g_common_v1_0_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_0_1
+g709_fec_v2_4_2=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_2
+v_scenechange_v1_0_4=$RDI_DATADIR/xsim/ip/v_scenechange_v1_0_4
+displayport_v8_1_3=$RDI_DATADIR/xsim/ip/displayport_v8_1_3
+spdif_v2_0_23=$RDI_DATADIR/xsim/ip/spdif_v2_0_23
+dp_videoaxi4s_bridge_v1_0_1=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_1
+noc_nps6_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps6_v1_0_0
+sem_v4_1_13=$RDI_DATADIR/xsim/ip/sem_v4_1_13
+gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4
+axi_mmu_v2_1_20=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_20
+nvmeha_v1_0_3=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_3
+v_vid_in_axi4s_v4_0_9=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_9
+v_gamma_lut_v1_0_8=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_0_8
+axi_traffic_gen_v3_0_8=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_8
+tmr_inject_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_4
+axis_accelerator_adapter_v2_1_16=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_16
+hdcp22_rng_v1_0_1=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_1
+rama_v1_1_7_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_7_lib
+trace_s2mm_v1_0_0=$RDI_DATADIR/xsim/ip/trace_s2mm_v1_0_0
+xbip_counter_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_6
+v_mix_v5_1_0=$RDI_DATADIR/xsim/ip/v_mix_v5_1_0
+dft_v4_2_1=$RDI_DATADIR/xsim/ip/dft_v4_2_1
+ta_dma_v1_0_6=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_6
+blk_mem_gen_v8_4_4=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_4
+axi_ethernet_buffer_v2_0_23=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_23
+stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0
+lte_3gpp_mimo_decoder_v3_0_16=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_decoder_v3_0_16
+ieee802d3_50g_rs_fec_v2_0_6=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_6
+xbip_dsp48_acc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_6
+axi_sg_v4_1_13=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_13
+v_hdmi_tx1_v1_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx1_v1_0_0
+v_hdmi_tx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v2_0_0
+v_tc_v6_2_1=$RDI_DATADIR/xsim/ip/v_tc_v6_2_1
+noc_nsu_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nsu_v1_0_0
+high_speed_selectio_wiz_v3_2_3=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_2_3
+qdriv_pl_v1_0_2=$RDI_DATADIR/xsim/ip/qdriv_pl_v1_0_2
+axi_uart16550_v2_0_24=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_24
+microblaze_v11_0_4=$RDI_DATADIR/xsim/ip/microblaze_v11_0_4
+advanced_io_wizard_phy_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_0
+mdm_v3_2_19=$RDI_DATADIR/xsim/ip/mdm_v3_2_19
+versal_cips_ps_vip_v1_0_0=$RDI_DATADIR/xsim/ip/versal_cips_ps_vip_v1_0_0
+v_hcresampler_v1_0_16=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_0_16
+lte_3gpp_mimo_encoder_v4_0_15=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_encoder_v4_0_15
+axis_clock_converter_v1_1_23=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_23
+v_scenechange_v1_1_0=$RDI_DATADIR/xsim/ip/v_scenechange_v1_1_0
+mpegtsmux_v1_0_2=$RDI_DATADIR/xsim/ip/mpegtsmux_v1_0_2
+axi_sideband_util_v1_0_6=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_6
+dsp_macro_v1_0_1=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_1
+ll_compress_v1_0_0=$RDI_DATADIR/xsim/ip/ll_compress_v1_0_0
+sim_ddr_v1_0=$RDI_DATADIR/xsim/ip/sim_ddr_v1_0
+gtwizard_ultrascale_v1_7_9=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_9
+vid_phy_controller_v2_1_9=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_9
+ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig
+axi_apb_bridge_v3_0_17=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_17
+xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0
+rst_vip_v1_0_4=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_4
+xbip_dsp48_multadd_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_6
+canfd_v3_0_1=$RDI_DATADIR/xsim/ip/canfd_v3_0_1
+axis_broadcaster_v1_1_21=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_21
+mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2
+lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2
+pr_bitstream_monitor_v1_0_2=$RDI_DATADIR/xsim/ip/pr_bitstream_monitor_v1_0_2
+amm_axi_bridge_v1_0_8=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_8
+canfd_v2_0_4=$RDI_DATADIR/xsim/ip/canfd_v2_0_4
+polar_v1_0_6=$RDI_DATADIR/xsim/ip/polar_v1_0_6
+can_v5_0_25=$RDI_DATADIR/xsim/ip/can_v5_0_25
+axi_timer_v2_0_24=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_24
+jesd204_v7_2_10=$RDI_DATADIR/xsim/ip/jesd204_v7_2_10
+axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0
+c_mux_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_6
+axi_firewall_v1_1_1=$RDI_DATADIR/xsim/ip/axi_firewall_v1_1_1
+v_axi4s_remap_v1_1_0=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_1_0
+adc_dac_if_phy_v1_0_0=$RDI_DATADIR/xsim/ip/adc_dac_if_phy_v1_0_0
+microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6
+axi_tg_lib=$RDI_DATADIR/xsim/ip/axi_tg_lib
+dfx_controller_v1_0_1=$RDI_DATADIR/xsim/ip/dfx_controller_v1_0_1
+cic_compiler_v4_0_15=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_15
+processing_system7_vip_v1_0_10=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_10
+axi_intc_v4_1_15=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_15
+audio_clock_recovery_unit_v1_0_2=$RDI_DATADIR/xsim/ip/audio_clock_recovery_unit_v1_0_2
+axi_protocol_converter_v2_1_22=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_22
+remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4
+versal_cips_v2_1_0=$RDI_DATADIR/xsim/ip/versal_cips_v2_1_0
+g975_efec_i7_v2_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_18
+v_hscaler_v1_1_0=$RDI_DATADIR/xsim/ip/v_hscaler_v1_1_0
+axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4
+pcie_dma_versal_v2_0_1=$RDI_DATADIR/xsim/ip/pcie_dma_versal_v2_0_1
+v_tpg_v8_0_4=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_4
+c_compare_v12_0_6=$RDI_DATADIR/xsim/ip/c_compare_v12_0_6
+viterbi_v9_1_12=$RDI_DATADIR/xsim/ip/viterbi_v9_1_12
+pr_decoupler_v1_0_9=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_9
+axi_bram_ctrl_v4_1_4=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_4
+fc32_rs_fec_v1_0_16=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_16
+pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0
+axi_register_slice_v2_1_22=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_22
+dfx_axi_shutdown_manager_v1_0_0=$RDI_DATADIR/xsim/ip/dfx_axi_shutdown_manager_v1_0_0
+soft_ecc_proxy_v1_0_0=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_0_0
+hdcp_keymngmt_blk_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_0
+gig_ethernet_pcs_pma_v16_2_1=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_2_1
+sim_qdma_cpp_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_cpp_v1_0
+ddr4_pl_v1_0_3=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_3
+axi_vdma_v6_3_10=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_10
+xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0
+xbip_accum_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_6
+axi_emc_v3_0_22=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_22
+jesd204c_v4_2_3=$RDI_DATADIR/xsim/ip/jesd204c_v4_2_3
+axi_epc_v2_0_25=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_25
+gig_ethernet_pcs_pma_v16_1_9=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_1_9
+v_vscaler_v1_1_0=$RDI_DATADIR/xsim/ip/v_vscaler_v1_1_0
+generic_baseblocks_v2_1_0=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_0
+usxgmii_v1_2_0=$RDI_DATADIR/xsim/ip/usxgmii_v1_2_0
+ieee802d3_400g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v1_0_11
+dft_v4_1_1=$RDI_DATADIR/xsim/ip/dft_v4_1_1
+v_frmbuf_rd_v2_2_0=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_2_0
+ieee802d3_25g_rs_fec_v1_0_18=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_18
+ethernet_1_10_25g_v2_6_0=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_6_0
+v_frmbuf_wr_v2_2_0=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_2_0
+tmr_manager_v1_0_6=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_6
+trace_hub_v1_1_0=$RDI_DATADIR/xsim/ip/trace_hub_v1_1_0
+axi_iic_v2_0_25=$RDI_DATADIR/xsim/ip/axi_iic_v2_0_25
+pc_cfr_v6_4_0=$RDI_DATADIR/xsim/ip/pc_cfr_v6_4_0
+v_tpg_v7_0_16=$RDI_DATADIR/xsim/ip/v_tpg_v7_0_16
+lmb_bram_if_cntlr_v4_0_19=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_19
+v_vcresampler_v1_0_16=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_0_16
+axi_ethernetlite_v3_0_21=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_21
+ldpc_v2_0_6=$RDI_DATADIR/xsim/ip/ldpc_v2_0_6
+c_gate_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_6
+v_mix_v5_0_1=$RDI_DATADIR/xsim/ip/v_mix_v5_0_1
+audio_formatter_v1_0_4=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_4
+flexo_100g_rs_fec_v1_0_16=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_16
+uram_rd_back_v1_0_1=$RDI_DATADIR/xsim/ip/uram_rd_back_v1_0_1
+ptp_1588_timer_syncer_v1_0_1=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v1_0_1
+ieee802d3_clause74_fec_v1_0_8=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_8
+axis_cap_ctrl_v1_0_0=$RDI_DATADIR/xsim/ip/axis_cap_ctrl_v1_0_0
+common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0
+xlconstant_v1_1_7=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_7
+xsdbm_v2_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v2_0_0
+etrnic_v1_1_3=$RDI_DATADIR/xsim/ip/etrnic_v1_1_3
+pci64_v5_0_11=$RDI_DATADIR/xsim/ip/pci64_v5_0_11
+axi_gpio_v2_0_24=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_24
+dfx_decoupler_v1_0_1=$RDI_DATADIR/xsim/ip/dfx_decoupler_v1_0_1
+tcc_encoder_3gpplte_v4_0_16=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_16
+axi_ahblite_bridge_v3_0_19=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_19
+in_system_ibert_v1_0_12=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_12
+axis_register_slice_v1_1_22=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_22
+util_idelay_ctrl_v1_0_2=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_2
+xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0
+pci32_v5_0_12=$RDI_DATADIR/xsim/ip/pci32_v5_0_12
+v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0
+axi_cdma_v4_1_22=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_22
+axi_master_burst_v2_0_7=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_7
+hdcp22_cipher_dp_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_0
+v_hcresampler_v1_1_0=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_1_0
+sid_v8_0_15=$RDI_DATADIR/xsim/ip/sid_v8_0_15
+ahblite_axi_bridge_v3_0_17=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_17
+zynq_ultra_ps_e_v3_3_3=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_3
+timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4
+axi4svideo_bridge_v1_0_11=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_11
+xbip_multadd_v3_0_15=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_15
+axis_data_fifo_v1_1_23=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_23
+c_shift_ram_v12_0_14=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_14
+xbip_dsp48_mult_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_6
+noc_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_0
+gtwizard_ultrascale_v1_6_10=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_10
+axis_data_fifo_v2_0_4=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_4
+rs_decoder_v9_0_17=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_17
+i2s_receiver_v1_0_4=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_4
+perf_axi_tg_v1_0_11=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_11
+interlaken_v2_4_7=$RDI_DATADIR/xsim/ip/interlaken_v2_4_7
+xfft_v7_2_11=$RDI_DATADIR/xsim/ip/xfft_v7_2_11
+smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0
+g709_fec_v2_3_6=$RDI_DATADIR/xsim/ip/g709_fec_v2_3_6
+axis_ila_intf_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_intf_v1_0_0
+tsn_endpoint_ethernet_mac_block_v1_0_7=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_7
+v_hdmi_rx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v2_0_0
+v_uhdsdi_audio_v2_0_3=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_3
+axi_utils_v2_0_6=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_6
+sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1
+vid_edid_v1_0_0=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_0
+lte_dl_channel_encoder_v3_0_16=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v3_0_16
+axi_dma_v7_1_23=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_23
+emb_fifo_gen_v1_0_2=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_2
+c_mux_bus_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_6
+axi_mm2s_mapper_v1_1_21=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_21
+tcc_encoder_3gpp_v5_0_16=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_16
+av_pat_gen_v2_0_0=$RDI_DATADIR/xsim/ip/av_pat_gen_v2_0_0
+srio_gen2_v4_1_9=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_9
+fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6
+ten_gig_eth_mac_v15_1_9=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_9
+dfx_bitstream_monitor_v1_0_0=$RDI_DATADIR/xsim/ip/dfx_bitstream_monitor_v1_0_0
+displayport_v7_0_0=$RDI_DATADIR/xsim/ip/displayport_v7_0_0
+v_vcresampler_v1_1_0=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_1_0
+axis_dwidth_converter_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_sc_v1_1
+l_ethernet_v3_2_0=$RDI_DATADIR/xsim/ip/l_ethernet_v3_2_0
+xxv_ethernet_v3_3_0=$RDI_DATADIR/xsim/ip/xxv_ethernet_v3_3_0
+xpm=$RDI_DATADIR/xsim/ip/xpm
+nvme_tc_v2_0_0=$RDI_DATADIR/xsim/ip/nvme_tc_v2_0_0
+ieee802d3_200g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v1_0_11
+ats_switch_v1_0_3=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_3
+axi_data_fifo_v2_1_21=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_21
+zynq_ultra_ps_e_vip_v1_0_8=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_8
+fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4
+mutex_v2_1_11=$RDI_DATADIR/xsim/ip/mutex_v2_1_11
+lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0
+sim_rst_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_rst_gen_v1_0_2
+xbip_dsp48_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_6
+floating_point_v7_0_18=$RDI_DATADIR/xsim/ip/floating_point_v7_0_18
+v_smpte_uhdsdi_v1_0_8=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_8
+axis_vio_v1_0_2=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_2
+ieee802d3_rs_fec_v2_0_10=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_10
+lte_ul_channel_decoder_v4_0_17=$RDI_DATADIR/xsim/ip/lte_ul_channel_decoder_v4_0_17
+xbip_utils_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_10
+aes_v1_1_2=$RDI_DATADIR/xsim/ip/aes_v1_1_2
+div_gen_v5_1_17=$RDI_DATADIR/xsim/ip/div_gen_v5_1_17
+v_smpte_sdi_v3_0_9=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_9
+lte_dl_channel_encoder_v4_0_2=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v4_0_2
+tcc_decoder_3gppmm_v2_0_20=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_20
+axis_protocol_checker_v2_0_6=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_6
+fir_compiler_v5_2_6=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_6
+av_pat_gen_v1_0_1=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_1
+xbip_dsp48_multacc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_6
+advanced_io_wizard_v1_0_3=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_3
+v_tc_v6_1_13=$RDI_DATADIR/xsim/ip/v_tc_v6_1_13
+xpm_cdc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/xpm_cdc_gen_v1_0_0
+mailbox_v2_1_14=$RDI_DATADIR/xsim/ip/mailbox_v2_1_14
+uhdsdi_gt_v2_0_3=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_0_3
+lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2
+noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0
+v_vid_gt_bridge_v1_0_1=$RDI_DATADIR/xsim/ip/v_vid_gt_bridge_v1_0_1
+tri_mode_ethernet_mac_v9_0_17=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_17
+axis_ila_txns_cntr_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_txns_cntr_v1_0_0
+axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0
+emu_perf_common_v1_0=$RDI_DATADIR/xsim/ip/emu_perf_common_v1_0
+dbg_intf=$RDI_DATADIR/xsim/ip/dbg_intf
+clk_vip_v1_0_2=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_2
+axi_stream_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_stream_monitor_v1_1_0
+mipi_dsi_tx_ctrl_v1_0_7=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_7
+axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0
+debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1
+pc_cfr_v6_3_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_3_2
+gmii_to_rgmii_v4_1_0=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_1_0
+ernic_v2_0_0=$RDI_DATADIR/xsim/ip/ernic_v2_0_0
+accelerator_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/accelerator_monitor_v1_1_0
+xbip_dsp48_wrapper_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_4
+axi_pcie3_v3_0_13=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_13
+v_uhdsdi_audio_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_0_1
+v_dp_axi4s_vid_out_v1_0_1=$RDI_DATADIR/xsim/ip/v_dp_axi4s_vid_out_v1_0_1
+axi_mcdma_v1_1_3=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_3
+dist_mem_gen_v8_0_13=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_13
+sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1
+v_frmbuf_rd_v2_1_5=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_1_5
+v_frmbuf_wr_v2_1_5=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_1_5
+axi_crossbar_v2_1_23=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_23
+qdma_v4_0_2=$RDI_DATADIR/xsim/ip/qdma_v4_0_2
+v_hdmi_phy1_v1_0_2=$RDI_DATADIR/xsim/ip/v_hdmi_phy1_v1_0_2
+hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3
+v_smpte_uhdsdi_tx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_0
+xtlm_ipc_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ipc_v1_0
+ten_gig_eth_pcs_pma_v6_0_18=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_18
+interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4
+axi_protocol_checker_v2_0_8=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_8
+sync_ip=$RDI_DATADIR/xsim/ip/sync_ip
+util_reduced_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_4
+util_vector_logic_v2_0_1=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_1
+ba317=$RDI_DATADIR/xsim/ip/ba317
+xtlm_ap_ctrl_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ap_ctrl_v1_0
+high_speed_selectio_wiz_v3_5_2=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_5_2
+quadsgmii_v3_5_0=$RDI_DATADIR/xsim/ip/quadsgmii_v3_5_0
+vby1hs_v1_0_0=$RDI_DATADIR/xsim/ip/vby1hs_v1_0_0
+pc_cfr_v6_1_4=$RDI_DATADIR/xsim/ip/pc_cfr_v6_1_4
+vid_phy_controller_v2_2_7=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_7
+videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5
+fir_compiler_v7_2_15=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_15
+jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi
+hdmi_gt_controller_v1_0_3=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_3
+oran_radio_if_v1_1_0=$RDI_DATADIR/xsim/ip/oran_radio_if_v1_1_0
+v_deinterlacer_v5_1_0=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_1_0
+xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip
+trace_s2mm_v1_1_0=$RDI_DATADIR/xsim/ip/trace_s2mm_v1_1_0
+remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4
+lte_pucch_receiver_v2_0_18=$RDI_DATADIR/xsim/ip/lte_pucch_receiver_v2_0_18
+v_smpte_uhdsdi_rx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_0
+v_csc_v1_0_16=$RDI_DATADIR/xsim/ip/v_csc_v1_0_16
+ieee802d3_50g_rs_fec_v1_0_14=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_14
+emb_mem_gen_v1_0_3=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_3
+lib_srl_fifo_v1_0_2=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_2
+axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0
+mem_tg_v1_0_3=$RDI_DATADIR/xsim/ip/mem_tg_v1_0_3
+mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4
+emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5
+dds_compiler_v6_0_20=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_20
+icap_arb_v1_0_0=$RDI_DATADIR/xsim/ip/icap_arb_v1_0_0
+axi_interface_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_interface_monitor_v1_1_0
+i2s_transmitter_v1_0_4=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_4
+axi_hbicap_v1_0_3=$RDI_DATADIR/xsim/ip/axi_hbicap_v1_0_3
+v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0
+picxo=$RDI_DATADIR/xsim/ip/picxo
+axi_pmon_v1_0_0=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_0
+c_addsub_v12_0_14=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_14
+axi_uartlite_v2_0_26=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_26
+axi_fifo_mm_s_v4_2_4=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_2_4
+mammoth_transcode_v1_0_0=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_0
+tmr_voter_v1_0_3=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_3
+axi_interconnect_v1_7_18=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_18
+v_hscaler_v1_0_16=$RDI_DATADIR/xsim/ip/v_hscaler_v1_0_16
+v_vscaler_v1_0_16=$RDI_DATADIR/xsim/ip/v_vscaler_v1_0_16
+g709_rs_encoder_v2_2_7=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_7
+tmr_comparator_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_4
+mipi_dphy_v4_3_0=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_3_0
+prc_v1_3_4=$RDI_DATADIR/xsim/ip/prc_v1_3_4
+fifo_generator_v13_2_5=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_5
+iomodule_v3_1_6=$RDI_DATADIR/xsim/ip/iomodule_v3_1_6
+axi4stream_vip_v1_1_8=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_8
+v_deinterlacer_v5_0_16=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_0_16
+axi_remapper_tx_v1_0_0=$RDI_DATADIR/xsim/ip/axi_remapper_tx_v1_0_0
+axis_ila_pp_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_pp_v1_0_0
+pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0
+axi_vip_v1_1_8=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_8
+mipi_csi2_rx_ctrl_v1_0_8=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_8
+axi_datamover_v5_1_24=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_24
+v_gamma_lut_v1_1_0=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_1_0
+axis_itct_v1_0_0=$RDI_DATADIR/xsim/ip/axis_itct_v1_0_0
+axi_quad_spi_v3_2_21=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_21
+sim_trig_v1_0_4=$RDI_DATADIR/xsim/ip/sim_trig_v1_0_4
+axis_combiner_v1_1_20=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_20
+displayport_v9_0_3=$RDI_DATADIR/xsim/ip/displayport_v9_0_3
+blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6
+sim_clk_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_2
+v_dual_splitter_v1_0_9=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_9
+v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0
+compact_gt_v1_0_8=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_8
+zynq_ultra_ps_e_v3_2_6=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_2_6
+axi_tlm_ext_v1_0=$RDI_DATADIR/xsim/ip/axi_tlm_ext_v1_0
+xhmc_v1_0_12=$RDI_DATADIR/xsim/ip/xhmc_v1_0_12
+lib_fifo_v1_0_14=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_14
+cpri_v8_11_5=$RDI_DATADIR/xsim/ip/cpri_v8_11_5
+proc_sys_reset_v5_0_13=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_13
+axis_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_0
+tsn_temac_v1_0_5=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_5
+video_frame_crc_v1_0_3=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_3
+axi_amm_bridge_v1_0_12=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_12
+xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2
+qdriv_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/qdriv_pl_phy_v1_0_0
+floating_point_v7_1_11=$RDI_DATADIR/xsim/ip/floating_point_v7_1_11
+axi_tft_v2_0_23=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_23
+noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0
+lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0
+pc_cfr_v6_0_8=$RDI_DATADIR/xsim/ip/pc_cfr_v6_0_8
+ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0
+v_demosaic_v1_0_8=$RDI_DATADIR/xsim/ip/v_demosaic_v1_0_8
+roe_framer_v3_0_1=$RDI_DATADIR/xsim/ip/roe_framer_v3_0_1
+c_accum_v12_0_14=$RDI_DATADIR/xsim/ip/c_accum_v12_0_14
+pc_cfr_v6_2_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_2_2
+xbip_dsp48_macro_v3_0_18=$RDI_DATADIR/xsim/ip/xbip_dsp48_macro_v3_0_18
+axis_ila_adv_trig_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_adv_trig_v1_0_0
+axi_usb2_device_v5_0_23=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_23
+axi_hwicap_v3_0_26=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_26
+axis_mu_v1_0_0=$RDI_DATADIR/xsim/ip/axis_mu_v1_0_0
+audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0
+axis_dbg_sync_v1_0_0=$RDI_DATADIR/xsim/ip/axis_dbg_sync_v1_0_0
+microblaze_v10_0_7=$RDI_DATADIR/xsim/ip/microblaze_v10_0_7
+sd_fec_v1_1_6=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_6
+uhdsdi_gt_v1_0_3=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v1_0_3
+bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0
+xfft_v9_0_19=$RDI_DATADIR/xsim/ip/xfft_v9_0_19
+etrnic_v1_0_4=$RDI_DATADIR/xsim/ip/etrnic_v1_0_4
+mpegtsmux_v1_1_0=$RDI_DATADIR/xsim/ip/mpegtsmux_v1_1_0
+lmb_v10_v3_0_11=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_11
+dft_v4_0_16=$RDI_DATADIR/xsim/ip/dft_v4_0_16
+axi_mcdma_v1_0_8=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_0_8
+ibert_lib_v1_0_7=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_7
+sem_ultra_v3_1_16=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_16
+pcie_axi4lite_tap_v1_0_1=$RDI_DATADIR/xsim/ip/pcie_axi4lite_tap_v1_0_1
+cmac_usplus_v3_1_2=$RDI_DATADIR/xsim/ip/cmac_usplus_v3_1_2
+axi_bram_ctrl_v4_0_14=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_14
+ieee802d3_400g_rs_fec_v2_0_2=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v2_0_2
+switch_core_top_v1_0_8=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_8
+v_multi_scaler_v1_0_4=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_0_4
+v_hdmi_tx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_0
+tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6
+convolution_v9_0_15=$RDI_DATADIR/xsim/ip/convolution_v9_0_15
+iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0
+fec_5g_common_v1_1_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_1
+axis_subset_converter_v1_1_22=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_22
+axi_msg_v1_0_6=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_6
+axis_mem_v1_0_0=$RDI_DATADIR/xsim/ip/axis_mem_v1_0_0
+aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0
+axi_fifo_mm_s_v4_1_19=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_1_19
+ai_pl=$RDI_DATADIR/xsim/ip/ai_pl
+xbip_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_6
+c_reg_fd_v12_0_6=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_6
+shell_utils_msp432_bsl_crc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_0
+xdma_v4_1_8=$RDI_DATADIR/xsim/ip/xdma_v4_1_8
+hdcp22_cipher_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_3
+microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4
+v_csc_v1_1_0=$RDI_DATADIR/xsim/ip/v_csc_v1_1_0
+vfb_v1_0_16=$RDI_DATADIR/xsim/ip/vfb_v1_0_16
+axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub
+axi_firewall_v1_0_10=$RDI_DATADIR/xsim/ip/axi_firewall_v1_0_10
+noc_na_v1_0_0=$RDI_DATADIR/xsim/ip/noc_na_v1_0_0
+cmpy_v6_0_19=$RDI_DATADIR/xsim/ip/cmpy_v6_0_19
+mrmac_v1_3_0=$RDI_DATADIR/xsim/ip/mrmac_v1_3_0
+ddr4_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_0
+bs_switch_v1_0_0=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_0
+v_uhdsdi_vidgen_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_1
+an_lt_v1_0_1=$RDI_DATADIR/xsim/ip/an_lt_v1_0_1

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo.veo

@@ -0,0 +1,72 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:fifo_generator:13.2
+// IP Revision: 5
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+MeasDataFifo your_instance_name (
+  .clk(clk),      // input wire clk
+  .srst(srst),    // input wire srst
+  .din(din),      // input wire [255 : 0] din
+  .wr_en(wr_en),  // input wire wr_en
+  .rd_en(rd_en),  // input wire rd_en
+  .dout(dout),    // output wire [255 : 0] dout
+  .full(full),    // output wire full
+  .empty(empty)  // output wire empty
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file MeasDataFifo.v when simulating
+// the core, MeasDataFifo. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo.vho

@@ -0,0 +1,89 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:fifo_generator:13.2
+-- IP Revision: 5
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT MeasDataFifo
+  PORT (
+    clk : IN STD_LOGIC;
+    srst : IN STD_LOGIC;
+    din : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
+    wr_en : IN STD_LOGIC;
+    rd_en : IN STD_LOGIC;
+    dout : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
+    full : OUT STD_LOGIC;
+    empty : OUT STD_LOGIC
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : MeasDataFifo
+  PORT MAP (
+    clk => clk,
+    srst => srst,
+    din => din,
+    wr_en => wr_en,
+    rd_en => rd_en,
+    dout => dout,
+    full => full,
+    empty => empty
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file MeasDataFifo.vhd when simulating
+-- the core, MeasDataFifo. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo.xdc

@@ -0,0 +1,64 @@
+ 
+ 
+ 
+ 
+ 
+
+################################################################################
+# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+
+#------------------------------------------------------------------------------#
+#                         Native FIFO Constraints                              #
+#------------------------------------------------------------------------------#
+
+
+
+
+################################################################################
+

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_clocks.xdc

@@ -0,0 +1,69 @@
+################################################################################
+# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+#------------------------------------------------------------------------------#
+#                         Native FIFO Constraints                              #
+#------------------------------------------------------------------------------#
+
+#set wr_clock          [get_clocks -of_objects [get_ports wr_clk]]
+#set rd_clock          [get_clocks -of_objects [get_ports rd_clk]]
+#set wr_clk_period     [get_property PERIOD $wr_clock]
+#set rd_clk_period     [get_property PERIOD $rd_clock]
+#set skew_value [expr {(($wr_clk_period < $rd_clk_period) ? $wr_clk_period : $rd_clk_period)} ]
+
+
+# Set max delay on cross clock domain path for Block/Distributed RAM based FIFO
+
+## set_max_delay -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*rd_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].wr_stg_inst/Q_reg_reg[*]] -datapath_only [get_property -min PERIOD $rd_clock]
+## set_bus_skew -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*rd_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].wr_stg_inst/Q_reg_reg[*]] $skew_value
+
+## set_max_delay -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*wr_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].rd_stg_inst/Q_reg_reg[*]] -datapath_only [get_property -min PERIOD $wr_clock]
+## set_bus_skew -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*wr_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].rd_stg_inst/Q_reg_reg[*]] $skew_value
+#set_false_path -from [get_cells -hierarchical -filter {NAME =~ *gsckt_wrst.gic_rst.sckt_wrst_i_reg}] -to [get_cells -hierarchical -filter {NAME =~ *gsckt_wrst.gic_rst.garst_sync_ic[1].rd_rst_inst/Q_reg_reg[0]}]
+#set_false_path -from [get_cells -hierarchical -filter {NAME =~ *gsckt_wrst.gic_rst.garst_sync_ic[3].rd_rst_inst/Q_reg_reg[0]}] -to [get_cells -hierarchical -filter {NAME =~ *gsckt_wrst.gic_rst.garst_sync_ic[1].rd_rst_wr_inst/Q_reg_reg[0]}]
+################################################################################

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_ooc.xdc

@@ -0,0 +1,57 @@
+# (c) Copyright 2012-2023 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+# DO NOT MODIFY THIS FILE.
+# #########################################################
+#
+# This XDC is used only in OOC mode for synthesis, implementation
+#
+# #########################################################
+
+
+create_clock -period 10 -name clk [get_ports clk]
+
+

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/doc/fifo_generator_v13_2_changelog.txt

@@ -0,0 +1,254 @@
+2020.2:
+ * Version 13.2 (Rev. 5)
+ * No changes
+
+2020.1.1:
+ * Version 13.2 (Rev. 5)
+ * No changes
+
+2020.1:
+ * Version 13.2 (Rev. 5)
+ * No changes
+
+2019.2.2:
+ * Version 13.2 (Rev. 5)
+ * No changes
+
+2019.2.1:
+ * Version 13.2 (Rev. 5)
+ * No changes
+
+2019.2:
+ * Version 13.2 (Rev. 5)
+ * General: IP Waivers update in constraint files. No functional changes
+ * Revision change in one or more subcores
+
+2019.1.3:
+ * Version 13.2 (Rev. 4)
+ * No changes
+
+2019.1.2:
+ * Version 13.2 (Rev. 4)
+ * No changes
+
+2019.1.1:
+ * Version 13.2 (Rev. 4)
+ * No changes
+
+2019.1:
+ * Version 13.2 (Rev. 4)
+ * Bug Fix: Destination Clock not connected properly for some XPM_CDC instances when in common clock mode. Conditions added to connect the correct clock
+ * Other: IP Waivers added in constraint files. No functional changes
+ * Revision change in one or more subcores
+
+2018.3.1:
+ * Version 13.2 (Rev. 3)
+ * No changes
+
+2018.3:
+ * Version 13.2 (Rev. 3)
+ * Feature Enhancement: None
+ * Other: Reduced simulation warnings in Behavioral model. No functional changes
+ * Revision change in one or more subcores
+
+2018.2:
+ * Version 13.2 (Rev. 2)
+ * No changes
+
+2018.1:
+ * Version 13.2 (Rev. 2)
+ * Bug Fix: Enable Safety Circuit option was unintentionally made available for user selection when Enable Reset Synchronization is not selected. This unintentional enablement is corrected and Enable Safety Circuit is available for user selection only if Enable Reset Synchronization option is selected
+ * Bug Fix: REQP-1839 DRC warning removed from example test bench
+ * Bug Fix: Read Data Count in behavioral model is updated to start with a valid value when Enable Reset Synchronization option is not selected
+ * Other: As FIFO Generator core uses XPM_CDC module, user must ensure that the wr_rst and rd_rst overlap for at least C_SYNCHRONIZER_STAGE+1 slowest clock cycles if Enable Reset Synchronization option is disabled
+
+2017.4:
+ * Version 13.2 (Rev. 1)
+ * Revision change in one or more subcores
+
+2017.3:
+ * Version 13.2
+ * Feature Enhancement: Enable Safety Circuit option is made default for BRAM based FIFOs when Asynchronous Reset is selected
+ * Feature Enhancement: All outputs are made synchronous to respective clock domain when Enable Safety Circuit option is selected
+ * Feature Enhancement: All outputs are invalid for reset duration + 60 slowest clock cycles when Enable Safety Circuit option is selected
+ * Feature Enhancement: All outputs are invalid for reset duration + 30 slowest clock cycles when Enable Safety Circuit option is not selected
+ * Feature Enhancement: The outputs of FIFO Generator may be Xs for initial few clock cycles if the core is configured without reset. It is recommended to wait for 15 slowest clock cycles at the beginning of behavioral simulation (from time 0) before accessing the FIFO
+
+2017.2:
+ * Version 13.1 (Rev. 4)
+ * No changes
+
+2017.1:
+ * Version 13.1 (Rev. 4)
+ * Bug Fix: FIFO Generator core was constructing the buit-in FIFO sub-optimally for 2K-deep and 36-bit wide configuration. This is corrected to use the optimal FIFO structure
+ * Bug Fix: In order to enable the tool to perform the recovery check on the reset, set_false_path for reset is kept only from the input port to the first flop where it connects to
+ * Feature Enhancement: Updated the FIFO Generator's constraints to improve tool performance processing its XDC
+ * Other: Internal device family change, no functional changes
+ * Revision change in one or more subcores
+
+2016.4:
+ * Version 13.1 (Rev. 3)
+ * Port Change: None
+ * Bug Fix: Supported features table in the first page of GUI updated to reflect the asymmetry support for common clock BRAM FIFO
+ * Feature Enhancement: None
+ * Revision change in one or more subcores
+
+2016.3:
+ * Version 13.1 (Rev. 2)
+ * Port Change: wr_rst_busy and rd_rst_busy ports made available if safety circuit is enabled
+ * Bug Fix: Fixed issue which was causing the m_axis_tvalid to go high after the reset is released and no valid data written to the FIFO
+ * Feature Enhancement: Safety circuit is made independent of Output Register and Enable Reset Synchronization options
+ * Other: Added support for future devices
+ * Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
+ * Revision change in one or more subcores
+
+2016.2:
+ * Version 13.1 (Rev. 1)
+ * Revision change in one or more subcores
+
+2016.1:
+ * Version 13.1
+ * Delivering only Verilog behavioral model.
+ * Constraint(s) for Independent Clocks Distributed RAM FIFO is changed, which may issue a CDC-1 warning that can be safely ignored.
+ * Output Register option is updated to offer either Embedded Register or Fabric Register or Both Embedded and Fabric Registers.
+ * Updated the FIFO Generator GUI to provide Embedded Register option for Built-in FIFO when ECC mode in selected.
+ * Programmable Full and Programmable Empty Threshold range has been reduced for UltraScale and UltraScale+ Built-in FIFO configurations. For more information on the exact threshold range change, refer the PG(057)
+ * Programmable Full and Programmable Empty Threshold values were reset to its default values when the previous version of the core is upgraded to the latest version. This has been corrected
+ * Revision change in one or more subcores
+
+2015.4.2:
+ * Version 13.0 (Rev. 1)
+ * No changes
+
+2015.4.1:
+ * Version 13.0 (Rev. 1)
+ * No changes
+
+2015.4:
+ * Version 13.0 (Rev. 1)
+ * Fixed safety circuit related warnings in Behavioral model
+ * Revision change in one or more subcores
+
+2015.3:
+ * Version 13.0
+ * Additional safety circuit option provided for asynchronous reset configurations.
+ * Delivering only VHDL behavioral model.
+ * Added asymmetric port width support for 7-series Common Clock Block RAM FIFO
+ * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
+
+2015.2.1:
+ * Version 12.0 (Rev. 4)
+ * No changes
+
+2015.2:
+ * Version 12.0 (Rev. 4)
+ * No changes
+
+2015.1:
+ * Version 12.0 (Rev. 4)
+ * Delivering  non encrypted behavioral models.
+ * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock ports
+ * Enabling behavioral simulation for Built-in FIFO configurations changes the simulation file names and delivery structure.
+ * Supported devices and production status are now determined automatically, to simplify support for future devices
+
+2014.4.1:
+ * Version 12.0 (Rev. 3)
+ * No changes
+
+2014.4:
+ * Version 12.0 (Rev. 3)
+ * Reduced DRC warnings.
+ * Internal device family change, no functional changes
+ * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
+
+2014.3:
+ * Version 12.0 (Rev. 2)
+ * Added support for Asynchronous AXI Stream Packet FIFO for UltraScale devices.
+ * Added support for write data count and read data count for Asynchronous AXI Stream Packet FIFO for UltraScale devices.
+ * Added support for write data count and read data count for Common Clock Block RAM FIFO when Asymmetric Port Width option is enabled for UltraScale devices.
+ * Added support for Low Latency Built-in FIFO for UltraScale devices.
+
+2014.2:
+ * Version 12.0 (Rev. 1)
+ * Repackaged to improve internal automation, no functional changes.
+
+2014.1:
+ * Version 12.0
+ * Asynchronous reset port (rst) for Built-in FIFO configurations is removed for UltraScale Built-in FIFO configurations. When upgrading from previously released core, 'rst' port will be replaced by 'srst' port.
+ * Synchronous reset (srst) mechanism is changed now for UltraScale devices. FIFO Generator will now provide wr_rst_busy and rd_rst_busy output ports. When wr_rst_busy is active low, the core is ready for write operation and when rd_rst_busy is active low, the core is ready for read operation.
+ * Added asymmetric port width support for Common Clock Block RAM FIFO, Common Clock Built-in FIFO and Independent Clocks Built-in FIFO configurations for UltraScale Devices
+ * Added 'sleep' input port for Common Clock Built-in FIFO and Independent Clocks Built-in FIFO configurations only for UltraScale Devices
+ * Internal device family name change, no functional changes
+
+2013.4:
+ * Version 11.0 (Rev. 1)
+ * Added support for Ultrascale devices
+ * Common Clock Builtin FIFO is set as default implementation type only for UltraScale devices
+ * Embedded Register option is always ON for Block RAM and Builtin FIFOs only for UltraScale devices
+ * Reset is sampled with respect to wr_clk/clk and then synchronized before the use in FIFO Generator only for UltraScale devices
+
+2013.3:
+ * Version 11.0
+ * AXI ID Tags (s_axi_wid and m_axi_wid) are now determined by AXI protocol type (AXI4, AXI3). When upgrading from previously released core, these signals will be removed when AXI_Type = AXI4_Full.
+ * AXI Lock signals (s_axi_awlock, m_axi_awlock, s_axi_arlock and m_axi_arlock) are now determined by AXI Protocol type (AXI4, AXI3). When upgrading from previously released core, these signals width will reduce from 2-bits to 1-bit when AXI_Type=AXI4_Full
+ * Removed restriction on packet size in AXI4 Stream FIFO mode. Now, the packet size can be up to FIFO depth
+ * Enhanced support for IP Integrator
+ * Reduced warnings in synthesis and simulation
+ * Added support for Cadence IES and Synopsys VCS simulators
+ * Improved GUI speed and responsiveness, no functional changes
+ * Increased the maximum number of synchronization stages from 4 to 8. The minimum FIFO depth is limited to 32 when number of synchronization stages is > 4
+
+2013.2:
+ * Version 10.0 (Rev. 1)
+ * Constraints processing order changed
+
+2013.1:
+ * Version 10.0
+ * Native Vivado Release
+ * There have been no functional or interface changes to this IP.  The version number has changed to support unique versioning in Vivado starting with 2013.1.
+
+(c) Copyright 2002 - 2020 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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+Xilinx products are not designed or intended to be fail-
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+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.

S5443_M/S5443.srcs/sources_1/new/FftDataFiltering/DecimFilterWrapper.v

@@ -21,9 +21,9 @@
 module	DecimFilterWrapper
 #(	
 	parameter	AdcDataWidth		=	14,
-	parameter	N	=	2,
+	parameter	N	=	4,
 	parameter	M	=	1,
-	parameter	FilteredDataWidth	=	26,
+	parameter	FilteredDataWidth	=	28,
 	parameter	FirOutDataWidth		=	48,
 	parameter	FirOutCutBit		=	42
 )
@@ -63,18 +63,67 @@ module	DecimFilterWrapper
 	
 	reg		[24-1:0]	ifFtwLReg;
 	reg		[24-1:0]	ifFtwHReg;
+	
+	reg		[FilteredDataWidth-1:0]	outData;
+	
+	localparam	maxWidthForR2	=	5'd18;	//msb for R = 2;
+	localparam	maxWidthForR3	=	5'd21;	//msb for R = 3;
+	localparam	maxWidthForR4	=	5'd22;	//msb for R = 4;
+	localparam	maxWidthForR5	=	5'd24;	//msb for R = 5;
+	localparam	maxWidthForR6	=	5'd25;	//msb for R = 6;
+	localparam	maxWidthForR7	=	5'd26;	//msb for R = 7;
+	localparam	maxWidthForR8	=	5'd26;	//msb for R = 8;
+	localparam	maxWidthForR9	=	5'd27;	//msb for R = 9;
+	localparam	maxWidthForR10	=	5'd28;	//msb for R = 10;
+	
 //================================================================================
 //	ASSIGNMENTS
 //================================================================================
 
-	assign	FilteredAdcDataI_o		=	decimDataI[FilteredDataWidth-1-:AdcDataWidth+2];
-	assign	FilteredAdcDataQ_o		=	decimDataQ[FilteredDataWidth-1-:AdcDataWidth+2];
-	assign	FilteredDataVal_o		=	decimDataValI&decimDataValQ;
+	assign	FilteredAdcDataI_o	=	decimDataI[FilteredDataWidth-1-:AdcDataWidth+2];
+	assign	FilteredAdcDataQ_o	=	decimDataQ[FilteredDataWidth-1-:AdcDataWidth+2];
+	assign	FilteredDataVal_o	=	decimDataValI&decimDataValQ;
 	
 //================================================================================
 //	CODING
 //================================================================================
 
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		case(DecimFactor_i)
+			3'd2:	begin
+						outData	<=	{{FilteredDataWidth-maxWidthForR2{decimDataI[FilteredDataWidth-1]}},decimDataI[maxWidthForR2-1:0]};
+					end
+			3'd3:	begin
+						outData	<=	decimDataI[maxWidthForR3-1:0];
+					end
+			3'd4:	begin
+						outData	<=	decimDataI[maxWidthForR4-1:0];
+					end
+			3'd5:	begin
+						outData	<=	decimDataI[maxWidthForR5-1:0];
+					end
+			3'd6:	begin
+						outData	<=	decimDataI[maxWidthForR6-1:0];
+					end
+			3'd7:	begin
+						outData	<=	decimDataI[maxWidthForR7-1:0];
+					end
+			3'd8:	begin
+						outData	<=	decimDataI[maxWidthForR8-1:0];
+					end
+			3'd9:	begin
+						outData	<=	decimDataI[maxWidthForR9-1:0];
+					end
+			3'd10:	begin
+						outData	<=	decimDataI[maxWidthForR10-1:0];
+					end
+		endcase
+	end	else	begin
+		outData	<=	5'd0;
+	end
+end
+
 always	@(posedge	Clk_i)	begin
 	if	(!Rst_i)	begin
 		ifFtwLReg	<=	IfFtwL_i;
@@ -153,8 +202,8 @@ cicFilterInstI
 	.Clk_i			(Clk_i),
 	.Rst_i			(Rst_i),
 	.DecimFactor_i	(DecimFactor_i),
-	// .Data_i			({{12{AdcData_i[AdcDataWidth-1]}},AdcData_i}),
-	.Data_i			(adcCosResult),
+	.Data_i			({{14{AdcData_i[AdcDataWidth-1]}},AdcData_i}),
+	// .Data_i			(adcCosResult),
 	.DataNd_i		(OscWind_i),
 	.Data_o			(decimDataI),
 	.DataValid_o	(decimDataValI)
@@ -173,8 +222,8 @@ cicFilterInstQ
 	.Clk_i			(Clk_i),
 	.Rst_i			(Rst_i),
 	.DecimFactor_i	(DecimFactor_i),
-	// .Data_i			({{12{AdcData_i[AdcDataWidth-1]}},AdcData_i}),
-	.Data_i			(adcSinResult),
+	.Data_i			({{14{AdcData_i[AdcDataWidth-1]}},AdcData_i}),
+	// .Data_i			(adcSinResult),
 	.DataNd_i		(OscWind_i),
 	.Data_o			(decimDataQ),
 	.DataValid_o	(decimDataValQ)
@@ -196,6 +245,3 @@ endmodule
 
 
 
-
-
-

S5443_M/S5443.srcs/sources_1/new/S5443TopPulseProfileTb.v

@@ -71,7 +71,7 @@ module S5443TopPulseProfileTb;
 	
 	//COMMANDS	FOR REG_MAP
 	parameter	[31:0]	MeasCmdBypass	=	{8'h11,8'h0,8'h63,8'h1};
-	parameter	[31:0]	MeasCmdFft 		=	{8'h11,8'h0,8'h63,8'h9};
+	parameter	[31:0]	MeasCmdFft 		=	{8'h11,8'h0,8'h63,4'h0,3'd3,1'b1};
 	// parameter	[31:0]	MeasCmd 		=	{8'h11,8'h0,8'h53,8'h0};
 	parameter	[31:0]	MeasCmd =	{8'h11,8'h3e,8'h63,8'h0};
 	parameter	[31:0]	AdcCtrl =	{8'h12,24'h2};